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1. 发明授权

US09202940B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US09202940B2
公开(公告)日：2015-12-01
申请号：US14239375
申请日：2012-07-31
申请人： Tsuyoshi Kawakami , Yoshiyuki Nakaki , Yoshio Fujii , Hiroshi Watanabe , Shuhei Nakata , Kohei Ebihara , Akihiko Furukawa
发明人： Tsuyoshi Kawakami , Yoshiyuki Nakaki , Yoshio Fujii , Hiroshi Watanabe , Shuhei Nakata , Kohei Ebihara , Akihiko Furukawa
IPC分类号： H01L29/06 , H01L29/872 , H01L29/861 , H01L29/16
CPC分类号： H01L29/8725 , H01L29/0619 , H01L29/0623 , H01L29/1608 , H01L29/8611 , H01L29/872
摘要： A semiconductor device having high breakdown voltage and high reliability without forming an embedded injection layer with high position accuracy. The semiconductor device includes a base as an active area of a second conductivity type formed on a surface layer of a semiconductor layer of a first conductivity type to constitute a semiconductor element; guard rings as a plurality of first impurity regions of the second conductivity type formed on the surface layer of the semiconductor layer spaced apart from each other to respectively surround the base in plan view; and an embedded injection layer as a second impurity region of the second conductivity type embedded in the surface layer of the semiconductor layer to connect at least two bottom portions of the plurality of guard rings.
摘要翻译：具有高击穿电压和高可靠性的半导体器件，而不形成具有高定位精度的嵌入式注入层。半导体器件包括形成在第一导电类型的半导体层的表面层上的第二导电类型的有源区的基底，以构成半导体元件; 保护环作为多个第一导电类型的第一杂质区域，形成在半导体层的表面层上彼此间隔开以在平面图中分别包围基底; 以及作为第二导电类型的第二杂质区域的嵌入式注入层，其嵌入在半导体层的表面层中，以连接多个保护环的至少两个底部。

2. 发明授权

US08492836B2 Power semiconductor device 有权
标题翻译：功率半导体器件
公开(公告)号：US08492836B2
公开(公告)日：2013-07-23
申请号：US13500659
申请日：2009-10-14
申请人： Naruhisa Miura , Shuhei Nakata , Kenichi Ohtsuka , Shoyu Watanabe , Shiro Hino , Akihiko Furukawa
发明人： Naruhisa Miura , Shuhei Nakata , Kenichi Ohtsuka , Shoyu Watanabe , Shiro Hino , Akihiko Furukawa
IPC分类号： H01L29/66
CPC分类号： H01L29/7811 , H01L29/0615 , H01L29/0638 , H01L29/0696 , H01L29/1095 , H01L29/1608 , H01L29/42368 , H01L29/42372 , H01L29/66068
摘要： In a semiconductor device according to the present invention, a p-type well region disposed in an outer peripheral portion of the power semiconductor device is divided into two parts, that is, an inside and an outside, and a field oxide film having a greater film thickness than the gate insulating film is provided on a well region at the outside to an inside of an inner periphery of the well region. Therefore, it is possible to prevent, in the gate insulating film, a dielectric breakdown due to the voltage generated by the flow of the displacement current in switching.
摘要翻译：在根据本发明的半导体器件中，设置在功率半导体器件的外周部分中的p型阱区被分成两部分，即内部和外部，并且具有更大的场氧化物膜膜厚比栅极绝缘膜设置在外部的阱区域到阱区的内周的内侧。因此，可以防止在栅极绝缘膜中由于切换中的位移电流的流动而产生的电压引起的电介质击穿。

3. 发明申请

US20110012133A1 SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：硅碳化硅半导体器件及其制造方法
公开(公告)号：US20110012133A1
公开(公告)日：2011-01-20
申请号：US12921250
申请日：2009-03-04
申请人： Shoyu Watanabe , Shuhei Nakata , Kenichi Ohtsuka
发明人： Shoyu Watanabe , Shuhei Nakata , Kenichi Ohtsuka
IPC分类号： H01L29/772 , H01L21/20
CPC分类号： H01L29/7802 , H01L21/047 , H01L29/0642 , H01L29/0878 , H01L29/1608 , H01L29/32 , H01L29/66068
摘要： A silicon carbide MOSFET that exhibits a high source-to-drain withstand voltage and that involves a smaller difference between gate-to-drain capacitance achieved in an activated state and gate-to-drain capacitance achieved in a deactivated state. A silicon carbide drift layer of a first conductivity type is provided on a silicon carbide substrate of a first conductivity type; a pair of base regions are provided in a surface layer portion of the silicon carbide drift layer and exhibit a second conductivity type; a pair of source regions are provided in interiors of surface layer portions of the pair of base regions and exhibit a first conductivity type; and semi-insulating regions are provided between the silicon carbide substrate and the pair of base regions.
摘要翻译：表现出高的源极 - 漏极耐受电压并且在激活状态下实现的栅 - 漏电容与在去激活状态下实现的栅 - 漏电容之间的较小差异的碳化硅MOSFET。在第一导电类型的碳化硅衬底上提供第一导电类型的碳化硅漂移层; 在碳化硅漂移层的表层部分设置一对基区，呈现第二导电型; 一对源极区域设置在一对基极区域的表层部分的内部并呈现出第一导电类型; 并且在碳化硅衬底和一对基极区之间设置半绝缘区域。

4. 发明授权

US6031345A Color CRT having a self-converging deflection yoke 失效
标题翻译：彩色CRT具有自会聚偏转线圈
公开(公告)号：US6031345A
公开(公告)日：2000-02-29
申请号：US655646
申请日：1996-05-30
申请人： Shuhei Nakata
发明人： Shuhei Nakata
IPC分类号： H01J29/50 , H01J29/56 , H01J29/66 , H01J29/68 , H01J29/70 , H01J29/76 , G09G1/28
CPC分类号： H01J29/705
摘要： In a color CRT having an in-line electron gun and a self-converging deflection yoke, a first quadrupole electro-magnetic coil is provided on the deflection yoke, and is wider at the screen side than at the neck side, and a second quadrupole electro-magnetic coil which is provided on the deflection yoke and which is wider at the neck side than at the screen side. The main lens of the in-line electron gun may have a cross section of a race-track shape. A deflection electrode provided for deflecting the side beams may be provided in the vicinity of the main lens of the in-line electron gun. A quadrupole electric-field lens may be additionally provided for correcting an astigma of the side beam, provided in the vicinity of the deflection electrode.
摘要翻译：在具有串联电子枪和自会聚偏转线圈的彩色CRT中，偏转线圈上设置有第一四极电磁线圈，并且在屏幕侧比在颈侧宽，第二四极杆设置在偏转线圈上并且在颈部侧比在屏幕侧更宽的电磁线圈。直列电子枪的主透镜可以具有赛道形状的横截面。设置用于偏转侧光束的偏转电极可以设置在直列式电子枪的主透镜附近。可以额外设置四极电场透镜，用于校正设置在偏转电极附近的侧光束的散光。

5. 发明授权

US09525057B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US09525057B2
公开(公告)日：2016-12-20
申请号：US14400025
申请日：2013-03-12
申请人： Naruhisa Miura , Shiro Hino , Akihiko Furukawa , Yuji Abe , Shuhei Nakata , Masayuki Imaizumi , Yasuhiro Kagawa
发明人： Naruhisa Miura , Shiro Hino , Akihiko Furukawa , Yuji Abe , Shuhei Nakata , Masayuki Imaizumi , Yasuhiro Kagawa
IPC分类号： H01L29/08 , H01L29/78 , H01L21/04 , H01L29/10 , H01L29/423 , H01L29/06 , H01L29/66 , H01L29/808 , H01L29/16
CPC分类号： H01L29/7802 , H01L21/046 , H01L29/0615 , H01L29/0619 , H01L29/086 , H01L29/1033 , H01L29/1095 , H01L29/1608 , H01L29/42356 , H01L29/66068 , H01L29/66893 , H01L29/7813 , H01L29/7827 , H01L29/7836 , H01L29/8083
摘要： A source region of a MOSFET includes: a source contact region connected to a source pad; a source extension region adjacent to a channel region in a well region; and a source resistance control region arranged between the source extension region and the source contact region. The source resistance control region is different in an impurity concentration from the source extension region and the source contact region. These three regions are connected in series between the source pad and the channel region in the well region.
摘要翻译： MOSFET的源极区域包括：源极接触区域，连接到源极焊盘; 源极延伸区域，其邻近阱区域中的沟道区域; 以及源极电阻控制区域，其布置在源极延伸区域和源极接触区域之间。源极电阻控制区域与源极延伸区域和源极接触区域的杂质浓度不同。这三个区域串联连接在源极区和阱区中的沟道区之间。

6. 发明授权

US09293572B2 Power semiconductor device 有权
标题翻译：功率半导体器件
公开(公告)号：US09293572B2
公开(公告)日：2016-03-22
申请号：US13806534
申请日：2010-06-24
申请人： Akihiko Furukawa , Yasuhiro Kagawa , Naruhisa Miura , Shiro Hino , Shuhei Nakata , Kenichi Ohtsuka , Shoyu Watanabe , Masayuki Imaizumi
发明人： Akihiko Furukawa , Yasuhiro Kagawa , Naruhisa Miura , Shiro Hino , Shuhei Nakata , Kenichi Ohtsuka , Shoyu Watanabe , Masayuki Imaizumi
IPC分类号： H01L29/15 , H01L29/78 , H01L29/66 , H01L27/088 , H01L29/06 , H01L21/04 , H01L29/45
CPC分类号： H01L29/78 , H01L21/0485 , H01L27/088 , H01L29/0696 , H01L29/45 , H01L29/6606 , H01L29/66068 , H01L29/7805 , H01L29/7815
摘要： In a high speed switching power semiconductor device having a sense pad, a high voltage is generated during switching operations in well regions under the sense pad due to a displacement current flowing through its flow path with a resistance, whereby the power semiconductor device sometimes breaks down by dielectric breakdown of a thin insulating film such as a gate insulating film. In a power semiconductor device according to the invention, sense-pad well contact holes are provided on well regions positioned under the sense pad and penetrate a field insulating film thicker than the gate insulating film to connect to the source pad, thereby improving reliability.
摘要翻译：在具有感测焊盘的高速开关电力半导体器件中，由于位移电流通过其流动路径而具有电阻，在感测焊盘下的阱区域的开关操作期间产生高电压，由此功率半导体器件有时会分解通过诸如栅极绝缘膜的薄绝缘膜的电介质击穿。在根据本发明的功率半导体器件中，感测焊盘井接触孔设置在位于感测焊盘下方的阱区上，并穿透比栅极绝缘膜更厚的场绝缘膜以连接到源极焊盘，从而提高可靠性。

7. 发明授权

US09105715B2 Semiconductor device and method for manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US09105715B2
公开(公告)日：2015-08-11
申请号：US13146654
申请日：2009-04-30
申请人： Naruhisa Miura , Shuhei Nakata , Kenichi Ohtsuka , Shoyu Watanabe , Naoki Yutani
发明人： Naruhisa Miura , Shuhei Nakata , Kenichi Ohtsuka , Shoyu Watanabe , Naoki Yutani
IPC分类号： H01L29/66 , H01L29/78 , H01L29/10 , H01L29/06 , H01L29/16 , H01L29/423 , H01L29/45 , H01L29/49
CPC分类号： H01L29/7811 , H01L23/53209 , H01L29/0611 , H01L29/0615 , H01L29/0638 , H01L29/0696 , H01L29/1095 , H01L29/1608 , H01L29/42372 , H01L29/4238 , H01L29/45 , H01L29/4916 , H01L29/4941 , H01L29/4975 , H01L29/66068 , H01L29/7805 , H01L2924/0002 , H01L2924/00
摘要： In a cell region of a first major surface of a semiconductor substrate of a first conductivity type, a first well of a second conductivity type is in an upper surface. A diffusion region of a first conductivity type is in the upper surface in the first well. A first gate insulating film is on the first well, and a first gate electrode on the first gate insulating film. A second well of a second conductivity type is in the upper surface of the first major surface on a peripheral portion of the cell region. A second gate insulating film is on the second well, and a thick field oxide film is on the peripheral side than the second gate insulating film. A second gate electrode is sequentially on the second gate insulating film and the field oxide film and electrically connected to the first gate electrode. A first electrode is connected to the first, second well and the diffusion region. A second electrode is connected on a second major surface of the semiconductor substrate. A gate wiring is on the field oxide film, going around a periphery of the cell region, and electrically connected to the second gate electrode. The gate wiring is a silicide of a constituting substance of the second gate electrode.
摘要翻译：在第一导电类型的半导体衬底的第一主表面的单元区域中，第二导电类型的第一阱位于上表面。第一导电类型的扩散区位于第一阱的上表面。第一栅极绝缘膜在第一阱上，第一栅极电极在第一栅极绝缘膜上。第二导电类型的第二阱在电池区域的周边部分的第一主表面的上表面中。第二栅绝缘膜在第二阱上，厚场氧化膜位于比第二栅极绝缘膜更外侧。第二栅电极顺序地在第二栅极绝缘膜和场氧化物膜上电连接到第一栅电极。第一电极连接到第一，第二阱和扩散区。第二电极连接在半导体衬底的第二主表面上。栅极布线在场氧化膜上，绕电池区的周围，并电连接到第二栅电极。栅极布线是第二栅电极的构成物质的硅化物。

8. 发明授权

US08723259B2 Silicon carbide semiconductor device 有权
标题翻译：碳化硅半导体器件
公开(公告)号：US08723259B2
公开(公告)日：2014-05-13
申请号：US13146812
申请日：2010-02-23
申请人： Yukiyasu Nakao , Masayuki Imaizumi , Shuhei Nakata , Naruhisa Miura
发明人： Yukiyasu Nakao , Masayuki Imaizumi , Shuhei Nakata , Naruhisa Miura
IPC分类号： H01L29/66
CPC分类号： H01L29/1608 , H01L21/0465 , H01L29/0615 , H01L29/0657 , H01L29/0696 , H01L29/1095 , H01L29/42372 , H01L29/45 , H01L29/66068 , H01L29/7396 , H01L29/7811 , H01L29/7816
摘要： A SiC semiconductor device capable of increasing a switching speed without destroying a gate insulating film. In addition, in a SiC-MOSFET including an n-type semiconductor substrate formed of SiC, a p-type semiconductor layer is entirely or partially provided on an upper surface of a p-type well layer that has a largest area of the transverse plane among a plurality of p-type well layers provided in an n-type drift layer and is arranged on an outermost periphery immediately below a gate electrode pad. It is preferable that a concentration of an impurity contained in the p-type semiconductor layer be larger than that of the p-type well layer.
摘要翻译：一种能够提高开关速度而不破坏栅极绝缘膜的SiC半导体器件。此外，在由SiC构成的n型半导体基板的SiC-MOSFET中，p型半导体层全部或部分设置在p型阱层的上表面上，该p型阱层的横面为最大面积在设置在n型漂移层中的多个p型阱层之中，并且布置在栅电极焊盘正下方的最外周。 p型半导体层中含有的杂质的浓度优选大于p型阱层的浓度。

9. 发明授权

US08629498B2 Power semiconductor device and method for manufacturing the power semiconductor device 有权
标题翻译：功率半导体器件及其制造方法
公开(公告)号：US08629498B2
公开(公告)日：2014-01-14
申请号：US13319742
申请日：2009-07-15
申请人： Shoyu Watanabe , Shuhei Nakata , Naruhisa Miura
发明人： Shoyu Watanabe , Shuhei Nakata , Naruhisa Miura
IPC分类号： H01L29/66
CPC分类号： H01L29/7811 , H01L29/0696 , H01L29/1095 , H01L29/1608 , H01L29/66068
摘要： In a power semiconductor device that switches at a high speed, a displacement current flows at a time of switching, so that a high voltage occurs which may cause breakdown of a thin insulating film such as a gate insulating film. A semiconductor device includes: a semiconductor substrate of a first conductivity type; a drift layer of the first conductivity type formed on a first main surface of the semiconductor substrate; a first well region of a second conductivity type formed in a part of a surface layer of the drift layer; a second well region of the second conductivity type formed in a part of the surface layer of the drift layer at a distance from the first well region, the second well region having a smaller area than that of the first well region when seen above an upper surface thereof; a low-resistance region of the first conductivity type formed in a surface layer of the first well region, the low-resistance region having a higher impurity concentration than that of the first well region; a gate insulating film formed on and in contact with a surface of the first well region; and a gate electrode formed on and in contact with a surface of the gate insulating film.
摘要翻译：在高速切换的功率半导体器件中，位移电流在切换时流动，从而产生可能导致诸如栅极绝缘膜的薄绝缘膜破坏的高电压。半导体器件包括：第一导电类型的半导体衬底; 形成在所述半导体衬底的第一主表面上的所述第一导电类型的漂移层; 形成在漂移层的表面层的一部分中的第二导电类型的第一阱区; 第二导电类型的第二阱区形成在距第一阱区一定距离的漂移层的表面层的一部分中，第二阱区的面积比第一阱区的面积小，当在上部表面形成在第一阱区的表面层中的第一导电类型的低电阻区域，低电阻区域的杂质浓度高于第一阱区域; 形成在第一阱区的表面上并与其接触的栅极绝缘膜; 以及形成在栅极绝缘膜的表面上并与栅极绝缘膜的表面接触的栅电极。

10. 发明申请

US20110284874A1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20110284874A1
公开(公告)日：2011-11-24
申请号：US13146654
申请日：2009-04-30
申请人： Naruhisa Miura , Shuhei Nakata , Kenichi Ohtsuka , Shoyu Watanabe , Naoki Yutani
发明人： Naruhisa Miura , Shuhei Nakata , Kenichi Ohtsuka , Shoyu Watanabe , Naoki Yutani
IPC分类号： H01L29/78 , H01L21/8238
CPC分类号： H01L29/7811 , H01L23/53209 , H01L29/0611 , H01L29/0615 , H01L29/0638 , H01L29/0696 , H01L29/1095 , H01L29/1608 , H01L29/42372 , H01L29/4238 , H01L29/45 , H01L29/4916 , H01L29/4941 , H01L29/4975 , H01L29/66068 , H01L29/7805 , H01L2924/0002 , H01L2924/00
摘要： In a cell region of a first major surface of a semiconductor substrate of a first conductivity type, a first well of a second conductivity type is in an upper surface. A diffusion region of a first conductivity type is in the upper surface in the first well. A first gate insulating film is on the first well, and a first gate electrode on the first gate insulating film. A second well of a second conductivity type is in the upper surface of the first major surface on a peripheral portion of the cell region. A second gate insulating film is on the second well, and a thick field oxide film is on the peripheral side than the second gate insulating film. A second gate electrode is sequentially on the second gate insulating film and the field oxide film and electrically connected to the first gate electrode. A first electrode is connected to the first, second well and the diffusion region. A second electrode is connected on a second major surface of the semiconductor substrate. A gate wiring is on the field oxide film, going around a periphery of the cell region, and electrically connected to the second gate electrode. The gate wiring is a silicide of a constituting substance of the second gate electrode.
摘要翻译：在第一导电类型的半导体衬底的第一主表面的单元区域中，第二导电类型的第一阱位于上表面。第一导电类型的扩散区位于第一阱的上表面。第一栅极绝缘膜在第一阱上，第一栅极电极在第一栅极绝缘膜上。第二导电类型的第二阱在电池区域的周边部分的第一主表面的上表面中。第二栅绝缘膜在第二阱上，厚场氧化膜位于比第二栅极绝缘膜更外侧。第二栅电极顺序地在第二栅极绝缘膜和场氧化物膜上电连接到第一栅电极。第一电极连接到第一，第二阱和扩散区。第二电极连接在半导体衬底的第二主表面上。栅极布线位于场氧化膜上，绕着单元区域的周边，并与第二栅电极电连接。栅极布线是第二栅电极的构成物质的硅化物。

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