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1. 发明授权

US09105715B2 Semiconductor device and method for manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US09105715B2
公开(公告)日：2015-08-11
申请号：US13146654
申请日：2009-04-30
申请人： Naruhisa Miura , Shuhei Nakata , Kenichi Ohtsuka , Shoyu Watanabe , Naoki Yutani
发明人： Naruhisa Miura , Shuhei Nakata , Kenichi Ohtsuka , Shoyu Watanabe , Naoki Yutani
IPC分类号： H01L29/66 , H01L29/78 , H01L29/10 , H01L29/06 , H01L29/16 , H01L29/423 , H01L29/45 , H01L29/49
CPC分类号： H01L29/7811 , H01L23/53209 , H01L29/0611 , H01L29/0615 , H01L29/0638 , H01L29/0696 , H01L29/1095 , H01L29/1608 , H01L29/42372 , H01L29/4238 , H01L29/45 , H01L29/4916 , H01L29/4941 , H01L29/4975 , H01L29/66068 , H01L29/7805 , H01L2924/0002 , H01L2924/00
摘要： In a cell region of a first major surface of a semiconductor substrate of a first conductivity type, a first well of a second conductivity type is in an upper surface. A diffusion region of a first conductivity type is in the upper surface in the first well. A first gate insulating film is on the first well, and a first gate electrode on the first gate insulating film. A second well of a second conductivity type is in the upper surface of the first major surface on a peripheral portion of the cell region. A second gate insulating film is on the second well, and a thick field oxide film is on the peripheral side than the second gate insulating film. A second gate electrode is sequentially on the second gate insulating film and the field oxide film and electrically connected to the first gate electrode. A first electrode is connected to the first, second well and the diffusion region. A second electrode is connected on a second major surface of the semiconductor substrate. A gate wiring is on the field oxide film, going around a periphery of the cell region, and electrically connected to the second gate electrode. The gate wiring is a silicide of a constituting substance of the second gate electrode.
摘要翻译：在第一导电类型的半导体衬底的第一主表面的单元区域中，第二导电类型的第一阱位于上表面。第一导电类型的扩散区位于第一阱的上表面。第一栅极绝缘膜在第一阱上，第一栅极电极在第一栅极绝缘膜上。第二导电类型的第二阱在电池区域的周边部分的第一主表面的上表面中。第二栅绝缘膜在第二阱上，厚场氧化膜位于比第二栅极绝缘膜更外侧。第二栅电极顺序地在第二栅极绝缘膜和场氧化物膜上电连接到第一栅电极。第一电极连接到第一，第二阱和扩散区。第二电极连接在半导体衬底的第二主表面上。栅极布线在场氧化膜上，绕电池区的周围，并电连接到第二栅电极。栅极布线是第二栅电极的构成物质的硅化物。

2. 发明申请

US20110284874A1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20110284874A1
公开(公告)日：2011-11-24
申请号：US13146654
申请日：2009-04-30
申请人： Naruhisa Miura , Shuhei Nakata , Kenichi Ohtsuka , Shoyu Watanabe , Naoki Yutani
发明人： Naruhisa Miura , Shuhei Nakata , Kenichi Ohtsuka , Shoyu Watanabe , Naoki Yutani
IPC分类号： H01L29/78 , H01L21/8238
CPC分类号： H01L29/7811 , H01L23/53209 , H01L29/0611 , H01L29/0615 , H01L29/0638 , H01L29/0696 , H01L29/1095 , H01L29/1608 , H01L29/42372 , H01L29/4238 , H01L29/45 , H01L29/4916 , H01L29/4941 , H01L29/4975 , H01L29/66068 , H01L29/7805 , H01L2924/0002 , H01L2924/00
摘要： In a cell region of a first major surface of a semiconductor substrate of a first conductivity type, a first well of a second conductivity type is in an upper surface. A diffusion region of a first conductivity type is in the upper surface in the first well. A first gate insulating film is on the first well, and a first gate electrode on the first gate insulating film. A second well of a second conductivity type is in the upper surface of the first major surface on a peripheral portion of the cell region. A second gate insulating film is on the second well, and a thick field oxide film is on the peripheral side than the second gate insulating film. A second gate electrode is sequentially on the second gate insulating film and the field oxide film and electrically connected to the first gate electrode. A first electrode is connected to the first, second well and the diffusion region. A second electrode is connected on a second major surface of the semiconductor substrate. A gate wiring is on the field oxide film, going around a periphery of the cell region, and electrically connected to the second gate electrode. The gate wiring is a silicide of a constituting substance of the second gate electrode.
摘要翻译：在第一导电类型的半导体衬底的第一主表面的单元区域中，第二导电类型的第一阱位于上表面。第一导电类型的扩散区位于第一阱的上表面。第一栅极绝缘膜在第一阱上，第一栅极电极在第一栅极绝缘膜上。第二导电类型的第二阱在电池区域的周边部分的第一主表面的上表面中。第二栅绝缘膜在第二阱上，厚场氧化膜位于比第二栅极绝缘膜更外侧。第二栅电极顺序地在第二栅极绝缘膜和场氧化物膜上电连接到第一栅电极。第一电极连接到第一，第二阱和扩散区。第二电极连接在半导体衬底的第二主表面上。栅极布线位于场氧化膜上，绕着单元区域的周边，并与第二栅电极电连接。栅极布线是第二栅电极的构成物质的硅化物。

3. 发明申请

US20140191251A1 SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：硅碳化硅半导体器件及其制造方法
公开(公告)号：US20140191251A1
公开(公告)日：2014-07-10
申请号：US14240017
申请日：2011-09-21
申请人： Yoichiro Tarui , Eisuke Suekawa , Naoki Yutani , Shiro Hino , Naruhisa Miura , Masayuki Imaizumi
发明人： Yoichiro Tarui , Eisuke Suekawa , Naoki Yutani , Shiro Hino , Naruhisa Miura , Masayuki Imaizumi
IPC分类号： H01L29/78 , H01L29/16 , H01L21/02 , H01L29/66
CPC分类号： H01L29/78 , H01L21/02529 , H01L21/046 , H01L21/0485 , H01L29/086 , H01L29/1608 , H01L29/66068 , H01L29/66477 , H01L29/7802
摘要： It is expected that both reduction of the resistance of a source region and reduction of a leakage current in a gate oxide film be achieved in an MOSFET in a silicon carbide semiconductor device. A leakage current to occur in a gate oxide film of the MOSFET is suppressed by reducing roughness at an interface between a source region and the gate oxide film. If an impurity concentration is to become high at a surface portion of the source region, the gate oxide film is formed by dry oxidation or CVD process. If the gate oxide film is formed by wet oxidation, the impurity concentration at the surface portion of the source region is controlled at a low level.
摘要翻译：期望在碳化硅半导体器件中的MOSFET中实现源极区域的电阻降低和栅极氧化膜中的漏电流的减小。通过减少源极区域和栅极氧化物膜之间的界面处的粗糙度来抑制在MOSFET的栅极氧化膜中发生的漏电流。如果杂质浓度在源极区的表面部分变高，则通过干法氧化或CVD法形成栅极氧化膜。如果通过湿式氧化形成栅极氧化膜，则源极区域的表面部分处的杂质浓度被控制在低水平。

4. 发明授权

US09362391B2 Silicon carbide semiconductor device and method of manufacturing the same 有权
标题翻译：碳化硅半导体器件及其制造方法
公开(公告)号：US09362391B2
公开(公告)日：2016-06-07
申请号：US14240017
申请日：2011-09-21
申请人： Yoichiro Tarui , Eisuke Suekawa , Naoki Yutani , Shiro Hino , Naruhisa Miura , Masayuki Imaizumi
发明人： Yoichiro Tarui , Eisuke Suekawa , Naoki Yutani , Shiro Hino , Naruhisa Miura , Masayuki Imaizumi
IPC分类号： H01L29/78 , H01L29/66 , H01L29/08 , H01L29/16 , H01L21/04 , H01L21/02
CPC分类号： H01L29/78 , H01L21/02529 , H01L21/046 , H01L21/0485 , H01L29/086 , H01L29/1608 , H01L29/66068 , H01L29/66477 , H01L29/7802
摘要： It is expected that both reduction of the resistance of a source region and reduction of a leakage current in a gate oxide film be achieved in an MOSFET in a silicon carbide semiconductor device. A leakage current to occur in a gate oxide film of the MOSFET is suppressed by reducing roughness at an interface between a source region and the gate oxide film. If an impurity concentration is to become high at a surface portion of the source region, the gate oxide film is formed by dry oxidation or CVD process. If the gate oxide film is formed by wet oxidation, the impurity concentration at the surface portion of the source region is controlled at a low level.
摘要翻译：期望在碳化硅半导体器件中的MOSFET中实现源极区域的电阻降低和栅极氧化膜中的漏电流的减小。通过减少源极区域和栅极氧化物膜之间的界面处的粗糙度来抑制在MOSFET的栅极氧化膜中发生的漏电流。如果杂质浓度在源极区的表面部分变高，则通过干法氧化或CVD法形成栅极氧化膜。如果通过湿式氧化形成栅极氧化膜，则源极区域的表面部分处的杂质浓度被控制在低水平。

5. 发明申请

US20110001209A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20110001209A1
公开(公告)日：2011-01-06
申请号：US12867283
申请日：2009-03-12
申请人： Hiroshi Watanabe , Naoki Yutani , Kenichi Ohtsuka , Kenichi Kuroda , Masayuki Imaizumi , Yoshinori Matsuno
发明人： Hiroshi Watanabe , Naoki Yutani , Kenichi Ohtsuka , Kenichi Kuroda , Masayuki Imaizumi , Yoshinori Matsuno
IPC分类号： H01L29/47
CPC分类号： H01L29/872 , H01L21/0495 , H01L24/05 , H01L29/0619 , H01L29/1608 , H01L29/6606 , H01L2924/12032 , H01L2924/1306 , H01L2924/13091 , H01L2924/00
摘要： In a termination structure in which a JTE layer is provided, a level or defect existing at an interface between a semiconductor layer and an insulating film, or a minute amount of adventitious impurities that infiltrate into the semiconductor interface from the insulating film or from an outside through the insulating film becomes a source or a breakdown point of a leakage current, which deteriorates a breakdown voltage. A semiconductor device includes: an n− type semiconductor layer formed on an n+ type semiconductor substrate; a first electrode that is formed on the n− type semiconductor layer and functions as a Schottky electrode; a GR layer that is a first p type semiconductor layer formed on a surface of the n− type semiconductor layer below an end of the first electrode and a perimeter thereof; a JTE layer that is formed of a second p type semiconductor layer formed on a bottom and a lateral surface of a groove arranged in a ring shape around the GR layer apart from the GR layer, in a surface of the n− typesemiconductor layer; an insulating film provided so as to cover the GR layer and the JTE layer; and a second electrode that is an Ohmic electrode formed below a rear surface of the n+ type semiconductor substrate.
摘要翻译：在提供JTE层的端接结构中，存在于半导体层和绝缘膜之间的界面处的水平或缺陷，或从绝缘膜或外部渗透到半导体界面的少量不定性杂质通过绝缘膜成为漏电流的源极或击穿点，这会降低击穿电压。半导体器件包括：形成在n +型半导体衬底上的n型半导体层; 形成在n型半导体层上并用作肖特基电极的第一电极; GR层，其是形成在所述第一电极的端部下方的所述n型半导体层的表面上的第一p型半导体层及其周边; 在所述n型半导体层的表面中形成由形成在所述GR层之外的围绕所述GR层的环状的槽的底部和侧面上形成的第二p型半导体层的JTE层; 设置为覆盖GR层和JTE层的绝缘膜; 以及形成在n +型半导体衬底的后表面下方的欧姆电极的第二电极。

6. 发明授权

US08963276B2 Semiconductor device including a cell array having first cells and second cells interspersed around the arrangement of the first cells 有权
标题翻译：包括具有第一单元的单元阵列和第二单元的半导体器件散布在第一单元的排列周围
公开(公告)号：US08963276B2
公开(公告)日：2015-02-24
申请号：US13883073
申请日：2011-12-22
申请人： Hiroshi Watanabe , Naoki Yutani , Yoshiyuki Nakaki , Kenichi Ohtsuka
发明人： Hiroshi Watanabe , Naoki Yutani , Yoshiyuki Nakaki , Kenichi Ohtsuka
IPC分类号： H01L27/095 , H01L29/872 , H01L29/66 , H01L27/02 , H01L29/06 , H01L29/16
CPC分类号： H01L29/872 , H01L27/0207 , H01L29/0619 , H01L29/0623 , H01L29/1608 , H01L29/6606
摘要： A semiconductor device that can achieve a high-speed operation at a time of switching, and the like. The semiconductor device includes: a p-type buried layer buried within an n−-type semiconductor layer; and a p-type surface layer formed in a central portion of each of cells. In a contact cell, the p-type buried layer is in contact with the p-type surface layer. The semiconductor device further includes: a p+-type contact layer formed on the p-type surface layer of the contact cell; and an anode electrode provided on the n−-type semiconductor layer. The anode electrode forms a Schottky junction with the n−-type semiconductor layer and forms an ohmic junction with the p+-type contact layer.
摘要翻译：可以在切换时实现高速运转的半导体装置等。半导体器件包括：埋在n型半导体层内的p型掩埋层; 以及形成在每个单元的中心部分的p型表面层。在接触电池中，p型掩埋层与p型表面层接触。半导体器件还包括：形成在接触单元的p型表面层上的p +型接触层; 以及设置在n型半导体层上的阳极电极。阳极与n型半导体层形成肖特基结，并与p +型接触层形成欧姆结。

7. 发明申请

US20120028453A1 METHOD FOR MANUFACTURING SILICON CARBIDE SEMICONDUCTOR DEVICE 有权
标题翻译：制造碳化硅半导体器件的方法
公开(公告)号：US20120028453A1
公开(公告)日：2012-02-02
申请号：US13258941
申请日：2009-09-01
申请人： Yoshinori Matsuno , Kenichi Ohtsuka , Naoki Yutani , Kenichi Kuroda , Hiroshi Watanabe , Shozo Shikama
发明人： Yoshinori Matsuno , Kenichi Ohtsuka , Naoki Yutani , Kenichi Kuroda , Hiroshi Watanabe , Shozo Shikama
IPC分类号： H01L21/265
CPC分类号： H01L21/046 , H01L21/0495 , H01L29/1608 , H01L29/6606 , H01L29/872
摘要： An object is to provide a method for manufacturing a silicon carbide semiconductor device in which a time required for removing a sacrificial oxide film can be shortened and damage to a surface of the silicon carbide layer can be reduced. The method for manufacturing a silicon carbide semiconductor device includes: (a) performing ion implantation to a silicon carbide layer; (b) performing activation annealing to the ion-implanted silicon carbide layer 2; (c) removing a surface layer of the silicon carbide layer 2, to which the activation annealing has been performed, by dry etching; (d) forming a sacrificial oxide film on a surface layer of the silicon carbide layer, to which the dry etching has been performed, by performing sacrificial oxidation thereto; and (e) removing the sacrificial oxide film by wet etching.
摘要翻译：本发明的目的是提供一种用于制造碳化硅半导体器件的方法，其中可以缩短去除牺牲氧化膜所需的时间，并且可以降低对碳化硅层的表面的损坏。制造碳化硅半导体器件的方法包括：（a）对碳化硅层进行离子注入; （b）对离子注入碳化硅层2进行激活退火; （c）通过干蚀刻去除已经进行了活化退火的碳化硅层2的表面层; （d）通过对其进行牺牲氧化，在已经进行了干蚀刻的碳化硅层的表面层上形成牺牲氧化膜; 和（e）通过湿蚀刻去除牺牲氧化膜。

8. 发明申请

US20130221477A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20130221477A1
公开(公告)日：2013-08-29
申请号：US13883073
申请日：2011-12-22
申请人： Hiroshi Watanabe , Naoki Yutani , Yoshiyuki Nakaki , Kenichi Ohtsuka
发明人： Hiroshi Watanabe , Naoki Yutani , Yoshiyuki Nakaki , Kenichi Ohtsuka
IPC分类号： H01L29/872
CPC分类号： H01L29/872 , H01L27/0207 , H01L29/0619 , H01L29/0623 , H01L29/1608 , H01L29/6606
摘要： A semiconductor device that can achieve a high-speed operation at a time of switching, and the like. The semiconductor device includes: a p-type buried layer buried within an n−-type semiconductor layer; and a p-type surface layer formed in a central portion of each of cells. In a contact cell, the p-type buried layer is in contact with the p-type surface layer. The semiconductor device further includes: a p+-type contact layer formed on the p-type surface layer of the contact cell; and an anode electrode provided on the n−-type semiconductor layer. The anode electrode forms a Schottky junction with the n−-type semiconductor layer and forms an ohmic junction with the p+-type contact layer.
摘要翻译：可以在切换时实现高速运转的半导体装置等。半导体器件包括：埋在n型半导体层内的p型掩埋层; 以及形成在每个单元的中心部分的p型表面层。在接触电池中，p型掩埋层与p型表面层接触。半导体器件还包括：形成在接触单元的p型表面层上的p +型接触层; 以及设置在n型半导体层上的阳极电极。阳极与n型半导体层形成肖特基结，并与p +型接触层形成欧姆结。

9. 发明申请

US20090098719A1 METHOD FOR MANUFACTURING SILICON CARBIDE SEMICONDUCTOR DEVICE 有权
标题翻译：制造碳化硅半导体器件的方法
公开(公告)号：US20090098719A1
公开(公告)日：2009-04-16
申请号：US12188676
申请日：2008-08-08
申请人： Yoshinori MATSUNO , Kenichi Ohtsuka , Kenichi Kuroda , Shozo Shikama , Naoki Yutani
发明人： Yoshinori MATSUNO , Kenichi Ohtsuka , Kenichi Kuroda , Shozo Shikama , Naoki Yutani
IPC分类号： H01L21/04
CPC分类号： H01L21/0495 , H01L29/6606
摘要： An object of the invention is to provide a method for manufacturing a silicon carbide semiconductor device having constant characteristics with reduced variations in forward characteristics. The method for manufacturing the silicon carbide semiconductor device according to the invention includes the steps of: (a) preparing a silicon carbide substrate; (b) forming an epitaxial layer on a first main surface of the silicon carbide substrate; (c) forming a protective film on the epitaxial layer; (d) forming a first metal layer on a second main surface of the silicon carbide substrate; (e) applying heat treatment to the silicon carbide substrate at a predetermined temperature to form an ohmic junction between the first metal layer and the second main surface of the silicon carbide substrate; (f) removing the protective film; (g) forming a second metal layer on the epitaxial layer; and (h) applying heat treatment to the silicon carbide substrate at a temperature from 400° C. to 600° C. to form a Schottky junction of desired characteristics between the second metal layer and the epitaxial layer.
摘要翻译：本发明的目的是提供一种制造具有恒定特性并减小正向特性变化的碳化硅半导体器件的方法。根据本发明的制造碳化硅半导体器件的方法包括以下步骤：（a）制备碳化硅衬底; （b）在所述碳化硅衬底的第一主表面上形成外延层; （c）在外延层上形成保护膜; （d）在所述碳化硅衬底的第二主表面上形成第一金属层; （e）在预定温度下对所述碳化硅衬底进行热处理以在所述第一金属层和所述碳化硅衬底的所述第二主表面之间形成欧姆结; （f）去除保护膜; （g）在所述外延层上形成第二金属层; 和（h）在400℃至600℃的温度下对所述碳化硅衬底进行热处理以在所述第二金属层和所述外延层之间形成所需特性的肖特基结。

10. 发明授权

US09059193B2 Epitaxial wafer and semiconductor element 有权
标题翻译：外延晶片和半导体元件
公开(公告)号：US09059193B2
公开(公告)日：2015-06-16
申请号：US13514201
申请日：2010-12-27
申请人： Kenichi Ohtsuka , Kenichi Kuroda , Hiroshi Watanabe , Naoki Yutani , Hiroaki Sumitani
发明人： Kenichi Ohtsuka , Kenichi Kuroda , Hiroshi Watanabe , Naoki Yutani , Hiroaki Sumitani
IPC分类号： H01L29/15 , H01L29/66 , C30B23/02 , C30B25/02 , C30B29/36 , H01L21/02 , H01L29/10 , H01L29/16 , H01L29/872 , H01L21/04 , H01L29/78
CPC分类号： H01L29/66068 , C30B23/02 , C30B25/02 , C30B29/36 , H01L21/02378 , H01L21/02433 , H01L21/02447 , H01L21/02496 , H01L21/02529 , H01L21/02576 , H01L21/0495 , H01L29/107 , H01L29/1095 , H01L29/1608 , H01L29/7802 , H01L29/7827 , H01L29/872
摘要： A silicon carbide semiconductor element, including: i) an n-type silicon carbide substrate doped with a dopant, such as nitrogen, at a concentration C, wherein the substrate has a lattice constant that decreases with doping; ii) an n-type silicon carbide epitaxially-grown layer doped with the dopant, but at a smaller concentration than the substrate; and iii) an n-type buffer layer doped with the dopant, and arranged between the substrate and the epitaxially-grown layer, wherein the buffer layer has a multilayer structure in which two or more layers having the same thickness are laminated, and is configured such that, based on a number of layers (N) in the multilayer structure, a doping concentration of a K-th layer from a silicon carbide epitaxially-grown layer side is C·K/(N+1).
摘要翻译：一种碳化硅半导体元件，包括：i）以浓度C掺杂有诸如氮的掺杂剂的n型碳化硅衬底，其中所述衬底具有随着掺杂而降低的晶格常数; ii）掺杂有掺杂剂但以比衬底更小的浓度的n型碳化硅外延生长层; 并且iii）掺杂有掺杂剂的n型缓冲层，并且布置在所述衬底和所述外延生长层之间，其中所述缓冲层具有其中层叠具有相同厚度的两层或更多层的多层结构，并且被配置使得基于多层结构中的多个层（N），来自碳化硅外延生长层的第K层的掺杂浓度为C·K /（N + 1）。

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