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1. 发明授权

US09870230B2 Method and apparatus for tuning a processor to improve its performance 有权
公开(公告)号：US09870230B2
公开(公告)日：2018-01-16
申请号：US12737476
申请日：2009-06-12
申请人： Simon Andrew Ford , Stephen John Hill
发明人： Simon Andrew Ford , Stephen John Hill
IPC分类号： G06F9/30 , G06F9/38 , G06F11/34
CPC分类号： G06F9/3844 , G06F11/3409 , G06F11/3466 , G06F2201/81 , G06F2201/815 , G06F2201/875 , G06F2201/88 , G06F2201/885 , Y02B70/16 , Y02D10/34
摘要： A data processing apparatus comprising a processor for executing a data processing process and a processor for executing a tuning process is disclosed. The data processing apparatus is arranged such that the tuning process which is a different process to the data processing process can access the parameters of speculative mechanisms of the data processing process and tune the parameters so that the mechanisms speculate differently and in this way the performance of this data processing process can be improved.

2. 发明授权

US08675006B2 Apparatus and method for communicating between a central processing unit and a graphics processing unit 有权
标题翻译：用于在中央处理单元和图形处理单元之间进行通信的装置和方法
公开(公告)号：US08675006B2
公开(公告)日：2014-03-18
申请号：US12461418
申请日：2009-08-11
申请人： Simon Andrew Ford , Sean Tristram Ellis , Edward Charles Plowman
发明人： Simon Andrew Ford , Sean Tristram Ellis , Edward Charles Plowman
IPC分类号： G06F15/167 , G06F1/20 , G06F13/14 , G06T1/60
CPC分类号： G06F9/3877 , G06F9/30076 , G06F9/30181 , G06F9/30189 , G06F9/3851 , G06T1/20
摘要： A shared memory is provided accessible by a central processing unit and a graphics processing unit. A bus is provided via which the central processing unit, graphics processing unit and shared memory communicate. A first mechanism controls the graphics processing unit and the central processing unit routes control signals via the bus. An interface is provided between the central processing unit and the graphics processing unit, and an additional mechanism controls the graphics processing unit and the central processing unit provides control signals over the interface. This enables the GPU to continue to be used to handle large batches of graphics processing operations loosely coupled with the operations performed by the CPU, and it is also possible to employ the GPU to perform processing operations on behalf of the CPU in situations where those operations are tightly coupled with the operations performed by the CPU.
摘要翻译：共享存储器由中央处理单元和图形处理单元可访问。提供总线，中央处理单元，图形处理单元和共享存储器通过该总线进行通信。第一机构控制图形处理单元，并且中央处理单元经由总线路由控制信号。在中央处理单元和图形处理单元之间提供接口，并且附加机构控制图形处理单元，中央处理单元通过接口提供控制信号。这使得GPU可以继续用于处理与CPU执行的操作松散耦合的大批图形处理操作，并且还可以在这些操作的情况下使用GPU来代表CPU执行处理操作与CPU执行的操作紧密耦合。

3. 发明授权

US08190807B2 Mapping a computer program to an asymmetric multiprocessing apparatus 有权
标题翻译：将计算机程序映射到不对称多处理装置
公开(公告)号：US08190807B2
公开(公告)日：2012-05-29
申请号：US11976315
申请日：2007-10-23
申请人： Alastair David Reid , Edmund Grimley-Evans , Simon Andrew Ford
发明人： Alastair David Reid , Edmund Grimley-Evans , Simon Andrew Ford
IPC分类号： G06F12/08 , G06F9/45
CPC分类号： G06F11/362 , G06F11/3636
摘要： A computer implemented tool is provided for assisting in the mapping of a computer program to an asymmetric multiprocessing apparatus 2 incorporating an asymmetric memory hierarchy formed of a plurality of memories 12, 14. An at least partial architectural description 22, 40 is provided as an input variable to the tool and used to infer missing annotations within a source computer program 24, such as which functions are to be executed by which execution mechanisms 4, 6, 8 and which variables are to be stored within which memories 12, 14. The tool also adds mapping support commands, such as cache flush commands, cache invalidate commands, DMA move commands and the like as necessary to support the mapping of the computer program to the asymmetric multiprocessing apparatus 2.
摘要翻译：提供了一种计算机实现工具，用于帮助将计算机程序映射到并入由多个存储器12,14组成的非对称存储器层级的非对称多处理装置2.至少部分架构描述22,40被提供为输入变量，用于推断源计算机程序24内的丢失注释，例如要执行哪些功能，执行机构4,6,8以及哪些变量将被存储在哪个存储器12,14中。该工具还需要添加诸如缓存刷新命令，缓存无效命令，DMA移动命令等映射支持命令，以支持计算机程序到不对称多处理装置2的映射。

4. 发明授权

US08185724B2 Monitoring values of signals within an integrated circuit 有权
标题翻译：监控集成电路内的信号值
公开(公告)号：US08185724B2
公开(公告)日：2012-05-22
申请号：US12224671
申请日：2006-03-03
申请人： Simon Andrew Ford , Alastair Reid
发明人： Simon Andrew Ford , Alastair Reid
IPC分类号： G06F9/44 , G06F9/45
CPC分类号： G06F11/364 , G06F11/30
摘要： An integrated circuit, and method of reviewing values of one or more signals occurring within that integrated circuit, are provided. The integrated circuit comprises processing logic for executing a program, and monitoring logic for reviewing values of one or more signals occurring within the integrated circuit as a result of execution of the program. The monitoring logic stores configuration data, which can be software programmed in relation to the signals to be monitored. Further, the monitoring logic makes use of a Bloom filter which, for a value to be reviewed, performs a hash operation on that value in order to reference the configuration data to determine whether that value is either definitely not a value within the range or is potentially a value within the range of values. If the value is determined to be within the set of values, then a trigger signal is generated which can be used to trigger a further monitoring process.
摘要翻译：提供一种集成电路以及检查在该集成电路内发生的一个或多个信号的值的方法。集成电路包括用于执行程序的处理逻辑，以及作为执行程序的结果来检查在集成电路内发生的一个或多个信号的值的监视逻辑。监视逻辑存储配置数据，其可以相对于待监视的信号进行软件编程。此外，监视逻辑利用布隆过滤器，对于要检查的值，对该值执行散列操作，以引用配置数据，以确定该值是否绝对不是该范围内的值，或者是潜在的价值范围内的值。如果该值被确定为在该值集合内，则产生可用于触发进一步监视过程的触发信号。

5. 发明授权

US07937535B2 Managing cache coherency in a data processing apparatus 有权
标题翻译：在数据处理设备中管理高速缓存一致性
公开(公告)号：US07937535B2
公开(公告)日：2011-05-03
申请号：US11709279
申请日：2007-02-22
申请人： Emre Özer , Stuart David Biles , Simon Andrew Ford
发明人： Emre Özer , Stuart David Biles , Simon Andrew Ford
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F12/0831 , G06F12/0822 , Y02D10/13
摘要： Each of plural processing units has a cache, and each cache has indication circuitry containing segment filtering data. The indication circuitry responds to an address specified by an access request from an associated processing unit to reference the segment filtering data to indicate whether the data is either definitely not stored or is potentially stored in that segment. Cache coherency circuitry ensures that data accessed by each processing unit is up-to-date and has snoop indication circuitry whose content is derived from the already-provided segment filtering data. For certain access requests, the cache coherency circuitry initiates a coherency operation during which the snoop indication circuitry determines whether any of the caches requires a snoop operation. For each cache that does, the cache coherency circuitry issues a notification to that cache identifying the snoop operation to be performed.
摘要翻译：多个处理单元中的每一个具有高速缓存，并且每个高速缓存具有包含段过滤数据的指示电路。指示电路响应来自相关联的处理单元的访问请求指定的地址以引用段过滤数据，以指示数据是否被明确地不存储或潜在地存储在该段中。高速缓存一致性电路确保每个处理单元访问的数据是最新的，并且具有其内容源自已经提供的段过滤数据的窥探指示电路。对于某些访问请求，高速缓存一致性电路发起一致性操作，在此期间，窥探指示电路确定是否有任何缓存需要窥探操作。对于每个缓存，高速缓存一致性电路向该缓存发出一个通知，用于标识要执行的侦听操作。

6. 发明授权

US07761693B2 Data processing apparatus and method for performing arithmetic operations in SIMD data processing 有权
标题翻译：用于在SIMD数据处理中执行算术运算的数据处理装置和方法
公开(公告)号：US07761693B2
公开(公告)日：2010-07-20
申请号：US10889362
申请日：2004-07-13
申请人： Dominic Hugo Symes , Simon Andrew Ford
发明人： Dominic Hugo Symes , Simon Andrew Ford
IPC分类号： G06F7/38
CPC分类号： G06F9/345 , G06F7/4812 , G06F9/30014 , G06F9/30018 , G06F9/30021 , G06F9/30032 , G06F9/30036 , G06F9/3004 , G06F9/30043 , G06F9/30109 , G06F9/30112 , G06F9/30116 , G06F9/30138 , G06F9/3016 , G06F9/30167 , G06F9/30181 , G06F2207/3828
摘要： A data processing apparatus includes a register data store that stores data elements, an instruction decoder that decodes an “arithmetic returning high half” instruction, and a data processor that performs data processing operations controlled by the instruction decoder. In response to the decoded arithmetic returning high half instruction, the data processor specifies within the register data store one or more source registers to store a plurality of source data elements of a first size, and one or more destination registers to store a corresponding plurality of resultant data elements of a second size. The second size is half the size of the first size. The processor also performs the following operations in parallel on the plurality of source data elements to produce the corresponding plurality of resultant data elements: perform an arithmetic operation on the source registers specified by the instruction to produce a plurality of corresponding intermediate result data elements, form the resultant data elements from information derived from a high half of a corresponding one of the plurality of intermediate result data elements, store the resultant data elements in the destination register.
摘要翻译：数据处理装置包括存储数据元素的寄存器数据存储器，对“算术返回高一半”指令进行解码的指令译码器，以及进行由指令译码器控制的数据处理动作的数据处理器。响应于解码的算术返回高半指令，数据处理器在寄存器数据存储器内指定一个或多个源寄存器来存储多个第一大小的源数据元，以及一个或多个目标寄存器，以存储对应的多个第二大小的结果数据元素。第二大小是第一大小的一半。处理器还在多个源数据元件上并行地执行以下操作以产生相应的多个结果数据元素：对由指令指定的源寄存器执行算术运算以产生多个对应的中间结果数据元素，形式从多个中间结果数据元素的对应的一个的高半部得到的信息的结果数据元素将结果数据元素存储在目的地寄存器中。

7. 发明授权

US07689811B2 Method and apparatus for constant generation in SIMD processing 有权
标题翻译：用于SIMD处理中恒定生成的方法和装置
公开(公告)号：US07689811B2
公开(公告)日：2010-03-30
申请号：US10889364
申请日：2004-07-13
申请人： Wilco Dijkstra , Simon Andrew Ford , David James Seal
发明人： Wilco Dijkstra , Simon Andrew Ford , David James Seal
IPC分类号： G06F9/40
CPC分类号： G06F9/3004 , G06F9/30025 , G06F9/30032 , G06F9/30036 , G06F9/30109 , G06F9/30112 , G06F9/30116 , G06F9/30138 , G06F9/3016 , G06F9/30167
摘要： A data processing apparatus (2) comprising: a register data store operable to store data elements; an instruction decoder (14, 16) operable to decode an instruction with generated constant, said instruction having a data value associated therewith; a data processor (18) operable to perform data processing operations within parallel processing lanes on at least one source operand in response to a data processing instruction decoded by said instruction decoder (16); and said data processor being operable in response to said decoded instruction with generated constant and associated data value to expand at least a data portion (1210) of said associated data value, said expansion being performed in response to said instruction with generated constant and depending on a selected function, to generate a constant (1240), said generated constant (1240) forming one of said at least one source operands.
摘要翻译：一种数据处理装置（2），包括：可操作以存储数据元素的寄存器数据存储器; 指令解码器（14,16），用于对具有所产生的常数的指令进行解码，所述指令具有与之相关联的数据值; 数据处理器（18），用于响应于由所述指令解码器（16）解码的数据处理指令，在至少一个源操作数上的并行处理通道内进行数据处理操作; 并且所述数据处理器响应于所述经解码的指令而被操作以产生常数和相关联的数据值，以扩展所述关联数据值的至少一个数据部分（1210），所述扩展是响应于所述指令而产生的，并且取决于选择的函数，以产生常数（1240），所述生成常数（1240）形成所述至少一个源操作数之一。

8. 发明授权

US07647480B2 Handling of conditional instructions in a data processing apparatus 有权
标题翻译：在数据处理设备中处理条件指令
公开(公告)号：US07647480B2
公开(公告)日：2010-01-12
申请号：US11632698
申请日：2004-07-27
申请人： Simon Andrew Ford , Andrew Christopher Rose
发明人： Simon Andrew Ford , Andrew Christopher Rose
IPC分类号： G06F9/38
CPC分类号： G06F9/30072 , G06F9/3001 , G06F9/30163
摘要： A data processing apparatus and method of handling conditional instructions in such a data processing apparatus are provided. The data processing apparatus has a pipelined processing unit for executing instructions including at least one conditional instruction from a set of conditional instructions, and a register file having a plurality of registers operable to store data values for access by the pipelined processing unit when executing the instructions. A register specified by an instruction may be either a source register holding a source data value for that instruction or a destination register into which is stored a result data value generated by execution of that instruction. The register file has a predetermined number of read ports via which data values can be read from registers of the register file. The pipelined processing unit is operable when executing the at least one conditional instruction to produce a result data value which, dependent on the existence of the condition specified by that conditional instruction, represents either the result of the computation specified by that conditional instruction or a current data value stored in the destination register for that conditional instruction. Further, each conditional instruction in the set is constrained to specify a register that is both a source register and a destination register for that conditional instruction, thereby reducing the minimum number of read ports required to support execution of that conditional instruction by the pipelined processing unit.
摘要翻译：提供了一种在这种数据处理装置中处理条件指令的数据处理装置和方法。数据处理装置具有流水线处理单元，用于执行包括来自一组条件指令的至少一个条件指令的指令，以及具有多个寄存器的寄存器文件，该多个寄存器可操作以在执行指令时存储由流水线处理单元进行访问的数据值。由指令指定的寄存器可以是保存该指令的源数据值的源寄存器或存储通过执行该指令而生成的结果数据值的目标寄存器。寄存器文件具有预定数量的读取端口，经由该读取端口可以从寄存器文件的寄存器读取数据值。流水线处理单元在执行至少一个条件指令以产生结果数据值时可操作，该结果数据值取决于由该条件指令指定的条件的存在表示由该条件指令指定的计算结果或当前值存储在该条件指令的目标寄存器中的数据值。此外，集合中的每个条件指令被限制为指定用于该条件指令的源寄存器和目的地寄存器的寄存器，由此减少支持由流水线处理单元执行该条件指令所需的读端口的最小数量。

9. 发明申请

US20080189086A1 System and method for modelling a hardware component of a data processing apparatus 有权
标题翻译：用于建模数据处理装置的硬件部件的系统和方法
公开(公告)号：US20080189086A1
公开(公告)日：2008-08-07
申请号：US12007634
申请日：2008-01-14
申请人： Simon Andrew Ford , Paul Halliday Peeling
发明人： Simon Andrew Ford , Paul Halliday Peeling
IPC分类号： G06G7/48 , G06F17/11
CPC分类号： G06F17/5045 , G06F2217/78
摘要： A system and method are provided for modelling a hardware component of a data processing apparatus in order to generate an output identifying a value of an observable property of the hardware component. The system comprises a component model for modelling aspects of the hardware component, and feature extraction logic for extending the component model to cause the component model when executing to output one or more features identifying execution behaviour of the component model. A statistical model is then arranged to receive the one or more features output by the component model, and to generate the output dependent on said one or more features. In accordance with the invention, it is observed that although the component model may not explicitly model features that can be used to effectively predict values of the observable property, features that a statistical model depends on may still be captured in the underlying logic and implementation of the component model, and accordingly by extracting features identifying execution behaviour of the component model, this can provide a suitable input to the statistical model, thereby providing a simple and effective technique for producing values of the observable property of the hardware component.
摘要翻译：提供了一种系统和方法，用于对数据处理设备的硬件组件进行建模，以便生成识别硬件组件的可观察属性的值的输出。该系统包括用于建模硬件组件的组件的组件模型，以及特征提取逻辑，用于在执行组件模型时扩展组件模型以使组件模型输出识别组件模型的执行行为的一个或多个特征。然后布置统计模型以接收由组件模型输出的一个或多个特征，并且产生取决于所述一个或多个特征的输出。根据本发明，可以观察到，尽管组件模型可能未明确地模拟可用于有效预测可观察属性的特征的特征，但是统计模型依赖的特征仍然可以被捕获在基本的逻辑和实现中组件模型，因此通过提取识别组件模型的执行行为的特征，这可以为统计模型提供合适的输入，从而提供用于产生硬件组件的可观察属性值的简单有效的技术。

10. 发明申请

US20080098207A1 Analyzing diagnostic data generated by multiple threads within an instruction stream 审中-公开
标题翻译：分析指令流中多个线程生成的诊断数据
公开(公告)号：US20080098207A1
公开(公告)日：2008-04-24
申请号：US11898363
申请日：2007-09-11
申请人： Alastair David Reid , Simon Andrew Ford , Katherine Elizabeth Kneebone
发明人： Alastair David Reid , Simon Andrew Ford , Katherine Elizabeth Kneebone
IPC分类号： G06F9/44
CPC分类号： G06F11/362 , G06F11/3636
摘要： A diagnostic method for outputting diagnostic data relating to processing of instruction streams stemming from a computer program, at least some of said instructions streams comprising multiple threads is disclosed. The method comprises the steps of: (i) receiving diagnostic data; (ii) reordering said received diagnostic data in dependence upon reordering data, said reordering data comprising data relating to said computer program; and (iii) outputting said reordered diagnostic data. In general, the instructions streams are processed by a plurality of processing units arranged to process at least some of said instructions in parallel, said diagnostic data being received from said plurality of processing units.
摘要翻译：一种用于输出与源自计算机程序的指令流的处理有关的诊断数据的诊断方法，其中包括多个线程的至少一些所述指令流被公开。该方法包括以下步骤：（i）接收诊断数据; （ii）根据重新排序数据对所接收的诊断数据重新排序，所述重排序数据包括与所述计算机程序有关的数据; 和（iii）输出所述重新排序的诊断数据。通常，指令流由多个处理单元处理，多个处理单元被布置为并行处理至少一些所述指令，所述诊断数据从所述多个处理单元接收。

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