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1. 发明授权

US08225262B1 Method of and system for placing clock circuits in an integrated circuit 有权
标题翻译：在集成电路中放置时钟电路的方法和系统
公开(公告)号：US08225262B1
公开(公告)日：2012-07-17
申请号：US12406883
申请日：2009-03-18
申请人： Marvin Tom , Wei Mark Fang , Srinivasan Dasasathyan
发明人： Marvin Tom , Wei Mark Fang , Srinivasan Dasasathyan
IPC分类号： G06F17/50
CPC分类号： G06F17/5054 , G06F2217/62
摘要： A method of placing clock circuits in an integrated circuit is disclosed. The method comprises receiving a circuit design to be implemented in the integrated circuit; identifying portions of the circuit design comprising clock circuits; determining an order of clock circuits to be placed based upon resource requirements of the clock circuits; and placing the portions of the circuit design comprising clock circuits in sites of the integrated circuit. A system for placing clock circuits in an integrated circuit is also disclosed.
摘要翻译：公开了一种在集成电路中放置时钟电路的方法。该方法包括接收要在集成电路中实现的电路设计; 识别包括时钟电路的电路设计的部分; 基于时钟电路的资源需求确定要放置的时钟电路的顺序; 以及将包括时钟电路的电路设计的部分放置在集成电路的位置。还公开了一种用于将集成电路中的时钟电路放置的系统。

2. 发明授权

US07735039B1 Methods of estimating net delays in tile-based PLD architectures 有权
标题翻译：估计基于瓦片的PLD架构的网络延迟的方法
公开(公告)号：US07735039B1
公开(公告)日：2010-06-08
申请号：US11895899
申请日：2007-08-28
申请人： Srinivasan Dasasathyan , Hasan Arslan , Meng Lou , Anirban Rahut
发明人： Srinivasan Dasasathyan , Hasan Arslan , Meng Lou , Anirban Rahut
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F17/5054 , G06F2217/84
摘要： Methods of estimating delays between pins on a tile-based programmable logic device (PLD), by identifying repeat patterns and exploiting these patterns to provide accurate delay estimates. A computer-implemented method can include selecting a sample area in a tile-based PLD and constructing a delay table corresponding to the sample area. Each entry in the delay table includes a base delay value and a description of the fastest available route from a source pin in a source tile to a load pin in the sample area. To estimate a net delay, the base delay value and the description of the route are read from the delay table for specified source and load pins. One or more delay variants (e.g., pin delays and/or crossing penalties) are calculated based on the description of the route. The calculated delay variants are added to the base delay value to obtain an adjusted delay value, which is output.
摘要翻译：通过识别重复模式并利用这些模式来提供准确的延迟估计来估计基于瓦片的可编程逻辑器件（PLD）的引脚之间的延迟的方法。计算机实现的方法可以包括在基于瓦片的PLD中选择样本区域并构建对应于样本区域的延迟表。延迟表中的每个条目包括基本延迟值以及从源块中的源引脚到采样区中的负载引脚的最快可用路由的描述。为了估计净延迟，从延迟表中读取指定的源和负载引脚的基本延迟值和路由的描述。基于路线的描述来计算一个或多个延迟变型（例如，引脚延迟和/或交叉惩罚）。将计算的延迟变量加到基本延迟值中，以获得输出的经调整的延迟值。

3. 发明授权

US07149994B1 Integrated clock and input output placer 有权
标题翻译：集成时钟和输入输出放大器
公开(公告)号：US07149994B1
公开(公告)日：2006-12-12
申请号：US10651786
申请日：2003-08-29
申请人： Srinivasan Dasasathyan , Qiang Wang
发明人： Srinivasan Dasasathyan , Qiang Wang
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： A method (200) of placing inputs, outputs, and clocks in a circuit design can include assigning (205) initial locations to inputs and outputs of the circuit design, selecting (210) at least one component type for the circuit design, and generating (215) a cost function having parameters corresponding to the selected component type. The method further can include annealing (220) the selected component type using the cost function and determining design constraints (225) for the selected component type according to the annealing step. The method can repeat to process additional component types such that design constraints determined for each additional component type do not violate design constraints determined for prior component types.
摘要翻译：在电路设计中放置输入，输出和时钟的方法（200）可包括将初始位置（205）分配给电路设计的输入和输出，选择（210）用于电路设计的至少一个组件类型，以及产生（215）具有与所选择的组件类型相对应的参数的成本函数。该方法还可以包括使用成本函数退火（220）所选择的部件类型，并根据退火步骤确定所选部件类型的设计约束（225）。该方法可以重复处理其他组件类型，以便为每个附加组件类型确定的设计约束不违反为现有组件类型确定的设计约束。

4. 发明授权

US07149993B1 Method, system, and apparatus for incremental design in programmable logic devices using floorplanning 有权
标题翻译：使用布局规划的可编程逻辑器件中增量设计的方法，系统和装置
公开(公告)号：US07149993B1
公开(公告)日：2006-12-12
申请号：US10812550
申请日：2004-03-29
申请人： Rajat Aggarwal , Guenter Stenz , Srinivasan Dasasathyan
发明人： Rajat Aggarwal , Guenter Stenz , Srinivasan Dasasathyan
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： A method of designing a programmable logic device can include receiving a modification to a programmable logic device that has been floorplanned. Modules of the programmable logic device that have been changed by the modification can be identified. The changed modules can be floorplanned thereby determining a placement solution that does not violate boundaries of unchanged modules. The programmable logic device then can be placed and routed.
摘要翻译：设计可编程逻辑器件的方法可以包括接收对已被计划设计的可编程逻辑器件的修改。可以识别通过修改而改变的可编程逻辑器件的模块。更改的模块可以进行布局，从而确定不违反未更改模块边界的布局解决方案。然后，可编程逻辑器件可以放置和布线。

5. 发明授权

US06857115B1 Placement of objects with partial shape restriction 有权
标题翻译：放置具有局部形状限制的物体
公开(公告)号：US06857115B1
公开(公告)日：2005-02-15
申请号：US10215602
申请日：2002-08-08
申请人： Srinivasan Dasasathyan , Guenter Stenz , Sudip K. Nag , Jason H. Anderson
发明人： Srinivasan Dasasathyan , Guenter Stenz , Sudip K. Nag , Jason H. Anderson
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： Application of network flow techniques to constrained optimization problems is disclosed. The present of constrains may lead to infeasible solutions. The infeasible solutions can be removed by an iterative process of changing the structure of the network and/or the associated parameters. Specific applications of the invention to the placement of tristate buffers and clocks in integrated circuits are disclosed.
摘要翻译：公开了网络流技术对约束优化问题的应用。约束的存在可能导致不可行的解决方案。可以通过改变网络结构和/或相关参数的迭代过程来消除不可行的解决方案。公开了本发明在集成电路中放置三态缓冲器和时钟的具体应用。

6. 发明授权

US08448122B1 Implementing sub-circuits with predictable behavior within a circuit design 有权
标题翻译：在电路设计中实现具有可预测行为的子电路
公开(公告)号：US08448122B1
公开(公告)日：2013-05-21
申请号：US12416326
申请日：2009-04-01
申请人： Vishal Suthar , Hasan Arslan , Sridhar Krishnamurthy , Sanjeev Kwatra , Srinivasan Dasasathyan , Rajat Aggarwal , Sudip K. Nag
发明人： Vishal Suthar , Hasan Arslan , Sridhar Krishnamurthy , Sanjeev Kwatra , Srinivasan Dasasathyan , Rajat Aggarwal , Sudip K. Nag
IPC分类号： G06F17/50
CPC分类号： G06F17/5054
摘要： A method of implementing a circuit design within a programmable integrated circuit (IC) can include identifying an implementation directive embedded within a register transfer level (RTL) description of the circuit design and determining components of a sub-circuit of the circuit design, wherein the sub-circuit is specified by a portion of the RTL description associated with the implementation directive. The sub-circuit can be placed for the programmable IC and routed for the programmable IC according to the implementation directive. A programmatic description of the sub-circuit specifying placement and routing information can be output.
摘要翻译：在可编程集成电路（IC）中实现电路设计的方法可以包括识别嵌入在电路设计的寄存器传送电平（RTL）描述内的实现指令并确定电路设计的子电路的组件，其中子电路由与实施指令相关联的RTL描述的一部分指定。可以将子电路放置在可编程IC上，并根据实施指令为可编程IC路由。可以输出指定放置和路由信息的子电路的编程描述。

7. 发明授权

US08418115B1 Routability based placement for multi-die integrated circuits 有权
标题翻译：多模集成电路的基于路由的布局
公开(公告)号：US08418115B1
公开(公告)日：2013-04-09
申请号：US12777991
申请日：2010-05-11
申请人： Marvin Tom , Rajat Aggarwal , Srinivasan Dasasathyan
发明人： Marvin Tom , Rajat Aggarwal , Srinivasan Dasasathyan
IPC分类号： G06F17/5077
CPC分类号： G06F17/5072
摘要： A method of component placement for a multi-die integrated circuit (IC) can include partitioning a plurality of components of a netlist among a plurality of dies of the multi-die IC and selecting a superimposition model specifying a positioning of at least two of the plurality of dies at least partially superimposed with respect to one another. The method also can include assigning, by a processor, components of the netlist to hardware units within each of the plurality of dies according, at least in part, to a wire-length metric calculated using the superimposition model.
摘要翻译：一种用于多芯片集成电路（IC）的部件放置的方法可以包括在多芯片IC的多个裸片之间划分网表的多个部件，并且选择叠加模型，该叠加模型指定至少两个多个模具相对于彼此至少部分地重叠。该方法还可以包括：至少部分地由处理器将网表的组件分配给多个管芯内的硬件单元，至少部分地基于使用叠加模型计算的导线长度度量。

8. 发明授权

US08230377B1 Control set constraint driven force directed analytical placer for programmable integrated circuits 有权
标题翻译：用于可编程集成电路的控制集约束驱动力定向分析仪
公开(公告)号：US08230377B1
公开(公告)日：2012-07-24
申请号：US12429991
申请日：2009-04-24
申请人： Wei Mark Fang , Srinivasan Dasasathyan
发明人： Wei Mark Fang , Srinivasan Dasasathyan
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： A computer-implemented method of globally placing a circuit design on a programmable integrated circuit (IC) includes dividing, by a placement system, the programmable IC into a grid comprising a plurality of cells, assigning each component of a selected component type of the circuit design to one of a plurality of control set groups according to a control set of the component, and calculating a force including a control set force that depends upon overlap of control sets within the plurality of cells. The method further can include applying the force to at least one selected component of the circuit design and assigning components of the circuit design to locations on the programmable IC by solving a set of linear equations that depend upon application of the force to the at least one selected component to create a global placement. The circuit design including the global placement can be output.
摘要翻译：将电路设计全局放置在可编程集成电路（IC）上的计算机实现的方法包括将布置系统将可编程IC划分成包括多个单元的网格，分配电路的所选组件类型的每个组件根据组件的控制组设计为多个控制组组中的一组，并且计算包括依赖于多个单元内的控制组的重叠的控制设定力的力。该方法还可以包括将力施加到电路设计的至少一个选定部件，并通过求解一组依赖于将力施加到至少一个的线性方程组来将电路设计的部件分配给可编程IC上的位置选择的组件来创建全局展示位置。可以输出包括全局放置的电路设计。

9. 发明授权

US08091060B1 Clock domain partitioning of programmable integrated circuits 有权
标题翻译：可编程集成电路的时钟域划分
公开(公告)号：US08091060B1
公开(公告)日：2012-01-03
申请号：US12368435
申请日：2009-02-10
申请人： Marvin Tom , Srinivasan Dasasathyan
发明人： Marvin Tom , Srinivasan Dasasathyan
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F2217/62
摘要： A computer-implemented method of partitioning a circuit design into clock domains for implementation within a programmable integrated circuit (IC) can include storing a plurality of constraints that depend upon a plurality of variables, wherein the plurality of constraints regulate placement of components to different clock regions of the programmable IC. The method can include storing an objective function and determining a result indicating whether a feasible solution exists for clock domain partitioning of the circuit design by minimizing the objective function subject to the plurality of constraints. The result can be output.
摘要翻译：将电路设计划分成用于在可编程集成电路（IC）内实现的时钟域的计算机实现的方法可以包括存储取决于多个变量的多个约束，其中所述多个约束调节部件到不同时钟的放置可编程IC的区域。该方法可以包括存储目标函数并且通过最小化受到多个约束的目标函数来确定指示对电路设计的时钟域划分是否存在可行解的结果。可以输出结果。

10. 发明授权

US08473881B1 Multi-resource aware partitioning for integrated circuits 有权
标题翻译：集成电路的多资源感知分区
公开(公告)号：US08473881B1
公开(公告)日：2013-06-25
申请号：US13007780
申请日：2011-01-17
申请人： Wei Mark Fang , Vishal Suthar , Srinivasan Dasasathyan
发明人： Wei Mark Fang , Vishal Suthar , Srinivasan Dasasathyan
IPC分类号： G06F17/50
CPC分类号： G06F17/5027 , G06F17/5072
摘要： A method of partitioning a circuit design can include identifying a circuit design in which components of the circuit design are assigned to each of a plurality of regions, wherein each region corresponds to a physical portion of an integrated circuit. A maximum oversubscription region can be determined for a selected component type from the plurality of regions. A target region from the plurality of regions can be selected that is adjacent to the region of maximum oversubscription. The method also can include re-assigning, by a processor, a selected number of components of the maximum oversubscription region to the target region.
摘要翻译：分割电路设计的方法可以包括识别其中电路设计的组件被分配给多个区域中的每一个的电路设计，其中每个区域对应于集成电路的物理部分。可以从多个区域中针对所选择的组件类型确定最大超额预订区域。来自多个区域的目标区域可以被选择为与最大超额预订区域相邻。该方法还可以包括由处理器将最大超额预订区域的所选数量的组件重新分配给目标区域。

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