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1. 发明授权

US07735039B1 Methods of estimating net delays in tile-based PLD architectures 有权
标题翻译：估计基于瓦片的PLD架构的网络延迟的方法
公开(公告)号：US07735039B1
公开(公告)日：2010-06-08
申请号：US11895899
申请日：2007-08-28
申请人： Srinivasan Dasasathyan , Hasan Arslan , Meng Lou , Anirban Rahut
发明人： Srinivasan Dasasathyan , Hasan Arslan , Meng Lou , Anirban Rahut
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F17/5054 , G06F2217/84
摘要： Methods of estimating delays between pins on a tile-based programmable logic device (PLD), by identifying repeat patterns and exploiting these patterns to provide accurate delay estimates. A computer-implemented method can include selecting a sample area in a tile-based PLD and constructing a delay table corresponding to the sample area. Each entry in the delay table includes a base delay value and a description of the fastest available route from a source pin in a source tile to a load pin in the sample area. To estimate a net delay, the base delay value and the description of the route are read from the delay table for specified source and load pins. One or more delay variants (e.g., pin delays and/or crossing penalties) are calculated based on the description of the route. The calculated delay variants are added to the base delay value to obtain an adjusted delay value, which is output.
摘要翻译：通过识别重复模式并利用这些模式来提供准确的延迟估计来估计基于瓦片的可编程逻辑器件（PLD）的引脚之间的延迟的方法。计算机实现的方法可以包括在基于瓦片的PLD中选择样本区域并构建对应于样本区域的延迟表。延迟表中的每个条目包括基本延迟值以及从源块中的源引脚到采样区中的负载引脚的最快可用路由的描述。为了估计净延迟，从延迟表中读取指定的源和负载引脚的基本延迟值和路由的描述。基于路线的描述来计算一个或多个延迟变型（例如，引脚延迟和/或交叉惩罚）。将计算的延迟变量加到基本延迟值中，以获得输出的经调整的延迟值。

2. 发明授权

US07424697B1 Assigning inputs of look-up tables to improve a design implementation in a programmable logic device 有权
标题翻译：分配查询表的输入以改善可编程逻辑器件中的设计实现
公开(公告)号：US07424697B1
公开(公告)日：2008-09-09
申请号：US11707317
申请日：2007-02-16
申请人： Hasan Arslan , Anirban Rahut
发明人： Hasan Arslan , Anirban Rahut
IPC分类号： G06F17/50
CPC分类号： G06F17/5054 , G06F17/5031 , G06F2217/84
摘要： Methods for improving an implementation of a design in a programmable logic device (PLD). A topological level of the design implementation is determined for each look-up table (LUT) of the PLD. A subset of the LUTs that are on the critical timing paths of the design implementation is determined. For each LUT in the subset at each topological level, a set combinations is determined for assigning signals to the inputs of the LUT. A current assignment of the signals to the LUT inputs is initialized according to the design implementation. For each LUT in the subset at each topological level, the method determines whether a respective assignment for each combination in the set for the LUT improves a timing metric for the LUT relative to the current assignment for the LUT, and the current assignment is updated when the respective assignment improves the timing metric for the LUT.
摘要翻译：用于改进可编程逻辑器件（PLD）中的设计的实现的方法。为PLD的每个查找表（LUT）确定设计实现的拓扑级别。确定在设计实现的关键定时路径上的LUT的子集。对于每个拓扑级别的子集中的每个LUT，确定用于将信号分配给LUT的输入的集合组合。根据设计实现初始化对LUT输入的信号的当前分配。对于每个拓扑级别的子集中的每个LUT，该方法确定用于LUT的集合中的每个组合的相应分配是否相对于LUT的当前分配改进了LUT的定时度量，并且当相应的分配改进了LUT的定时度量。

3. 发明授权

US08448122B1 Implementing sub-circuits with predictable behavior within a circuit design 有权
标题翻译：在电路设计中实现具有可预测行为的子电路
公开(公告)号：US08448122B1
公开(公告)日：2013-05-21
申请号：US12416326
申请日：2009-04-01
申请人： Vishal Suthar , Hasan Arslan , Sridhar Krishnamurthy , Sanjeev Kwatra , Srinivasan Dasasathyan , Rajat Aggarwal , Sudip K. Nag
发明人： Vishal Suthar , Hasan Arslan , Sridhar Krishnamurthy , Sanjeev Kwatra , Srinivasan Dasasathyan , Rajat Aggarwal , Sudip K. Nag
IPC分类号： G06F17/50
CPC分类号： G06F17/5054
摘要： A method of implementing a circuit design within a programmable integrated circuit (IC) can include identifying an implementation directive embedded within a register transfer level (RTL) description of the circuit design and determining components of a sub-circuit of the circuit design, wherein the sub-circuit is specified by a portion of the RTL description associated with the implementation directive. The sub-circuit can be placed for the programmable IC and routed for the programmable IC according to the implementation directive. A programmatic description of the sub-circuit specifying placement and routing information can be output.
摘要翻译：在可编程集成电路（IC）中实现电路设计的方法可以包括识别嵌入在电路设计的寄存器传送电平（RTL）描述内的实现指令并确定电路设计的子电路的组件，其中子电路由与实施指令相关联的RTL描述的一部分指定。可以将子电路放置在可编程IC上，并根据实施指令为可编程IC路由。可以输出指定放置和路由信息的子电路的编程描述。

4. 发明授权

US09757767B2 Device and method for producing highly porous, crystalline surface coatings 有权
公开(公告)号：US09757767B2
公开(公告)日：2017-09-12
申请号：US14116014
申请日：2012-05-25
申请人： Christof Woell , Osama Shekhah , Matthias Franzreb , Hasan Arslan , Jonas Wohlgemuth , Roland Fischer
发明人： Christof Woell , Osama Shekhah , Matthias Franzreb , Hasan Arslan , Jonas Wohlgemuth , Roland Fischer
IPC分类号： B05D1/02 , B05D1/38 , B05D3/04 , H01L21/67 , B05D3/10 , B05D7/00 , B01D67/00 , B01D71/00 , B05B7/24
CPC分类号： B05D1/38 , B01D67/0072 , B01D71/00 , B01D2323/42 , B05B7/2489 , B05D1/02 , B05D3/0466 , B05D3/0486 , B05D3/107 , B05D7/56 , B05D2203/30 , B05D2401/10 , H01L21/6715 , Y10T428/249953
摘要： The present invention relates to a device, the use thereof and a method for producing highly porous, crystalline surface coatings comprising at least two spraying devices operating in sequential sequence for applying coating agents from the storage vessels (3, 4) to a material arranged on a sample holder (1) and at least one rinsing device (5, 13, 16) for removing unbound molecules from the coated surface.

5. 发明申请

US20140302304A1 DEVICE AND METHOD FOR PRODUCING HIGHLY POROUS, CRYSTALLINE SURFACE COATINGS 有权
标题翻译：用于生产高多孔，晶体表面涂层的装置和方法
公开(公告)号：US20140302304A1
公开(公告)日：2014-10-09
申请号：US14116014
申请日：2012-05-25
申请人： Christof Woell , Osama Shekhah , Matthias Franzreb , Hasan Arslan , Jonas Wohlgemuth , Roland Fischer
发明人： Christof Woell , Osama Shekhah , Matthias Franzreb , Hasan Arslan , Jonas Wohlgemuth , Roland Fischer
IPC分类号： B05B7/24 , B05D1/02
CPC分类号： B05D1/38 , B01D67/0072 , B01D71/00 , B01D2323/42 , B05B7/2489 , B05D1/02 , B05D3/0466 , B05D3/0486 , B05D3/107 , B05D7/56 , B05D2203/30 , B05D2401/10 , H01L21/6715 , Y10T428/249953
摘要： The present invention relates to a device, the use thereof and a method for producing highly porous, crystalline surface coatings comprising at least two spraying devices operating in sequential sequence for applying coating agents from the storage vessels (3, 4) to a material arranged on a sample holder (1) and at least one rinsing device (5, 13, 16) for removing unbound molecules from the coated surface.
摘要翻译：本发明涉及一种装置，其用途和用于生产高度多孔的结晶表面涂层的方法，其包括至少两个按顺序操作的喷涂装置，用于将涂覆剂从储存容器（3,4）施加到布置在样品保持器（1）和用于从涂覆表面去除未结合的分子的至少一个漂洗装置（5,13,16）。

6. 发明授权

US09556085B2 Graphene nanoribbons derived from poly(phenylene ethynylene) polymer, methods of making same, and uses thereof 有权
标题翻译：衍生自聚（亚苯基亚乙炔基）聚合物的石墨烯纳米带，其制备方法及其用途
公开(公告)号：US09556085B2
公开(公告)日：2017-01-31
申请号：US14113457
申请日：2012-04-27
申请人： William R. Dichtel , Hasan Arslan , Fernando J. Uribe-Romo
发明人： William R. Dichtel , Hasan Arslan , Fernando J. Uribe-Romo
IPC分类号： B32B5/16 , C07C2/84 , H01L31/18 , B82Y30/00 , B82Y40/00 , H01L51/00 , C01B31/04 , C08G61/02 , C08G61/10 , H01B1/04 , B82Y10/00 , C07C15/20 , H01L21/02 , H01L29/16
CPC分类号： C07C2/84 , B82Y10/00 , B82Y30/00 , B82Y40/00 , C01B32/184 , C01B2204/06 , C01B2204/065 , C07C15/20 , C08G61/02 , C08G61/10 , C08G2261/148 , C08G2261/3422 , C08G2261/72 , C08G2261/91 , C08G2261/92 , C08G2261/95 , H01B1/04 , H01L21/02527 , H01L21/0262 , H01L29/1606 , H01L31/1884 , H01L51/0045 , Y02E10/50 , Y02E10/549 , Y10S977/734 , Y10S977/842 , Y10S977/932 , Y10T428/2982
摘要： Provided are graphene nanoribbons (GNRs), methods of making GNRs, and uses of the GNRs. The methods can provide control over GNR parameters such as, for example, length, width, and edge composition (e.g., edge functional groups). The methods are based on a metal catalyzed cycloaddition reaction at the carbon-carbon triple bonds of a poly(phenylene ethynylene) polymer. The GNRs can be used in devices such a microelectronic devices.
摘要翻译：提供的是石墨烯纳米带（GNR），制作GNR的方法和GNR的使用。这些方法可以提供GNR参数的控制，例如长度，宽度和边缘组成（例如，边缘功能组）。该方法基于聚（亚苯基亚乙炔基）聚合物的碳 - 碳三键上的金属催化环加成反应。 GNR可用于诸如微电子器件的器件中。

7. 发明申请

US20140212668A1 GRAPHENE NANORIBBONS, METHODS OF MAKING SAME, AND USES THEREOF 有权
标题翻译：石墨纳米粒，其制备方法及其用途
公开(公告)号：US20140212668A1
公开(公告)日：2014-07-31
申请号：US14113457
申请日：2012-04-27
申请人： William R. Dichtel , Hasan Arslan , Fernando J. Uribe-Romo
发明人： William R. Dichtel , Hasan Arslan , Fernando J. Uribe-Romo
IPC分类号： C07C2/84 , C07C15/20
CPC分类号： C07C2/84 , B82Y10/00 , B82Y30/00 , B82Y40/00 , C01B32/184 , C01B2204/06 , C01B2204/065 , C07C15/20 , C08G61/02 , C08G61/10 , C08G2261/148 , C08G2261/3422 , C08G2261/72 , C08G2261/91 , C08G2261/92 , C08G2261/95 , H01B1/04 , H01L21/02527 , H01L21/0262 , H01L29/1606 , H01L31/1884 , H01L51/0045 , Y02E10/50 , Y02E10/549 , Y10S977/734 , Y10S977/842 , Y10S977/932 , Y10T428/2982
摘要： Provided are graphene nanoribbons (GNRs), methods of making GNRs, and uses of the GNRs. The methods can provide control over GNR parameters such as, for example, length, width, and edge composition (e.g., edge functional groups). The methods are based on a metal catalyzed cycloaddition reaction at the carbon-carbon triple bonds of a poly(phenylene ethynylene) polymer. The GNRs can be used in devices such a microelectronic devices.
摘要翻译：提供的是石墨烯纳米带（GNR），制作GNR的方法和GNR的使用。这些方法可以提供GNR参数的控制，例如长度，宽度和边缘组成（例如，边缘功能组）。该方法基于聚（亚苯基亚乙炔基）聚合物的碳 - 碳三键上的金属催化环加成反应。 GNR可用于诸如微电子器件的器件中。

8. 发明授权

US08196081B1 Incremental placement and routing 有权
标题翻译：增量放置和布线
公开(公告)号：US08196081B1
公开(公告)日：2012-06-05
申请号：US12751175
申请日：2010-03-31
申请人： Hasan Arslan , Vinay Verma , Sandor Kalman
发明人： Hasan Arslan , Vinay Verma , Sandor Kalman
IPC分类号： G06F17/50 , G06F9/455
CPC分类号： G06F17/5077 , G06F17/5072 , G06F2217/06
摘要： In one embodiment of the invention, a processor-implemented method is provided for routing of a partially routed circuit design. Modified signals of the partially routed circuit design are determined. A first set of routing constraints are applied by the processor to the unmodified signals of the circuit design. For each logic block of the circuit design, the number of the modified signals and the number of the unmodified signals connected to the logic block are determined. In response to one of the logic blocks having a ratio of the number of modified signals to the number of unmodified signals greater than a threshold ratio, the routing constraints are removed by the processor from one or more of the unmodified signals of the one of the logic blocks. The partially routed circuit design is then routed by the processor according to the remaining routing constraints, and the resulting netlist is stored.
摘要翻译：在本发明的一个实施例中，提供了一种处理器实现的方法来路由部分路由的电路设计。确定部分路由电路设计的修改信号。处理器将第一组路由约束应用于电路设计的未修改信号。对于电路设计的每个逻辑块，确定修改的信号的数量和连接到逻辑块的未修改信号的数量。响应于具有大于阈值比率的修改信号的数量与未修改信号的数量的比率的逻辑块之一，处理器从一个或多个未修改信号中的一个或多个的未修改信号中去除路由约束逻辑块。部分路由的电路设计然后由处理器根据剩余的路由约束进行路由，并且存储所得到的网表。

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