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1. 发明授权

US07735039B1 Methods of estimating net delays in tile-based PLD architectures 有权
标题翻译：估计基于瓦片的PLD架构的网络延迟的方法
公开(公告)号：US07735039B1
公开(公告)日：2010-06-08
申请号：US11895899
申请日：2007-08-28
申请人： Srinivasan Dasasathyan , Hasan Arslan , Meng Lou , Anirban Rahut
发明人： Srinivasan Dasasathyan , Hasan Arslan , Meng Lou , Anirban Rahut
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F17/5054 , G06F2217/84
摘要： Methods of estimating delays between pins on a tile-based programmable logic device (PLD), by identifying repeat patterns and exploiting these patterns to provide accurate delay estimates. A computer-implemented method can include selecting a sample area in a tile-based PLD and constructing a delay table corresponding to the sample area. Each entry in the delay table includes a base delay value and a description of the fastest available route from a source pin in a source tile to a load pin in the sample area. To estimate a net delay, the base delay value and the description of the route are read from the delay table for specified source and load pins. One or more delay variants (e.g., pin delays and/or crossing penalties) are calculated based on the description of the route. The calculated delay variants are added to the base delay value to obtain an adjusted delay value, which is output.
摘要翻译：通过识别重复模式并利用这些模式来提供准确的延迟估计来估计基于瓦片的可编程逻辑器件（PLD）的引脚之间的延迟的方法。计算机实现的方法可以包括在基于瓦片的PLD中选择样本区域并构建对应于样本区域的延迟表。延迟表中的每个条目包括基本延迟值以及从源块中的源引脚到采样区中的负载引脚的最快可用路由的描述。为了估计净延迟，从延迟表中读取指定的源和负载引脚的基本延迟值和路由的描述。基于路线的描述来计算一个或多个延迟变型（例如，引脚延迟和/或交叉惩罚）。将计算的延迟变量加到基本延迟值中，以获得输出的经调整的延迟值。

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