专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08286328B2 Method of fabricating a module, for millimeter wave multi-gigabit wireless systems 有权
标题翻译：用于毫米波多吉比特无线系统的模块制造方法
公开(公告)号：US08286328B2
公开(公告)日：2012-10-16
申请号：US12984035
申请日：2011-01-04
申请人： Stephane Pinel , Joy Laskar
发明人： Stephane Pinel , Joy Laskar
IPC分类号： H01S4/00
CPC分类号： H01P11/007 , H01P1/20327 , H01P1/2039 , H01P11/008 , H01Q1/38 , H01Q21/0006 , H01Q21/0087 , H01Q21/065 , H01Q21/08 , H01Q23/00 , Y10T29/49002 , Y10T29/49016 , Y10T29/4913 , Y10T29/49165 , Y10T156/10
摘要： A method of fabricating an ultra-high frequency module is disclosed. The method includes providing a top layer; drilling the top layer; milling the top layer; providing a bottom; milling the bottom layer to define a bottom layer cavity; aligning the top layer and the bottom layer; and adhering the top layer to the bottom layer. The present invention also includes an ultra-high frequency module operating at ultra-high speeds having a top layer, the top layer defining a top layer cavity; a bottom layer, the bottom layer defining a bottom layer cavity; and an adhesive adhering both the top layer to the bottom layer, wherein the top layer and the bottom layer are formed from a large area panel of a printed circuit board.
摘要翻译：公开了一种制造超高频模块的方法。该方法包括提供顶层; 钻顶层; 研磨顶层; 提供底部研磨底层以限定底层腔; 对齐顶层和底层; 并将顶层粘附到底层。本发明还包括以超高速运行的超高频模块，其具有顶层，顶层限定顶层空腔; 底层，底层限定底层空腔; 以及粘合上层到底层的粘合剂，其中顶层和底层由印刷电路板的大面积面板形成。

2. 发明申请

US20110291872A1 MULTI-GIGABIT ANALOG TO DIGITAL CONVERTER 有权
标题翻译：多数字模拟数字转换器
公开(公告)号：US20110291872A1
公开(公告)日：2011-12-01
申请号：US13056933
申请日：2008-07-31
申请人： Stephane Pinel , Joy Laskar
发明人： Stephane Pinel , Joy Laskar
IPC分类号： H03M1/12
CPC分类号： H03M1/361 , H03K5/08 , H03K5/2472 , H03M1/0636 , H03M1/1215 , H03M1/20
摘要： An analog to digital converter for operating at high speeds can be implemented with a micro-comparator/sampler, an encoder, and a selector. The micro-comparator includes an input from an antenna of a receiver/transceiver system; a transistor pair; reset transistor; cascaded inverters; an inverter circuit; a buffer; and a D flip flop circuit. Depending on the number of micro-comparator/samplers placed in parallel, a number of bits can be generated. For example, 15 bits from 15 different micro-comparator/samplers can be inserted into a 15 to 4 bit encoder to generate 4 bits.
摘要翻译：可以使用微比较器/采样器，编码器和选择器来实现用于高速操作的模数转换器。微型比较器包括来自接收器/收发器系统的天线的输入; 晶体管对; 复位晶体管; 级联逆变器; 逆变器电路; 一个缓冲区和D触发电路。根据并行放置的微比较器/采样器的数量，可以产生多个位。例如，15个不同的微比较器/采样器的15位可以插入15到4位编码器中，以生成4位。

3. 发明授权

US07489201B2 Millimeter-wave cascode amplifier gain boosting technique 失效
标题翻译：毫米波共源共栅放大器增益提升技术
公开(公告)号：US07489201B2
公开(公告)日：2009-02-10
申请号：US11801363
申请日：2007-05-09
申请人： Saikat Sarkar , Padmanava Sen , Stephane Pinel , Joy Laskar
发明人： Saikat Sarkar , Padmanava Sen , Stephane Pinel , Joy Laskar
IPC分类号： H03F3/04
CPC分类号： H03F1/22 , H03F3/191 , H03F3/60 , H03F2200/181 , H03F2200/222 , H03F2200/318 , H03F2200/387
摘要： Disclosed is a gain boosting technique for use with millimeter-wave cascode amplifiers. The exemplary technique may be implemented using a 0.18 μm SiGe process (FT=140 GHz). It has also been shown that the technique is effective for CMOS processes with comparable FT. An exemplary gain-enhanced cascode stage was measured to have higher than 9 dB gain with a 1-dB bandwidth above 6 GHz with a DC power consumption of 13 mW. In addition, one cascode stage without gain boosting may be cascaded with two gain-boosted cascode amplifier stages to implement a three-stage LNA. The measured stable gain is higher than 24 dB at 60 GHz with a 3-dB bandwidth of 3.1 GHz for 25 mW of DC power consumption. It is believed that this is the first 60 GHz LNA with a higher than 20 dB gain using a 0.18 μm SiGe process.
摘要翻译：公开了一种用于毫米波共源共栅放大器的增益技术。可以使用0.18μmSiGe工艺（FT = 140GHz）来实现示例性技术。还已经表明，该技术对于具有相当的FT的CMOS工艺是有效的。测量一个示例性的增益增益共源共栅级，具有高于9 dB的增益，1 GHz带宽高于6 GHz，直流功耗为13 mW。另外，没有增益升压的一个级联级可以与两个增益升压的共源共栅放大器级级联以实现三级LNA。测量的稳定增益在60 GHz时高于24 dB，对于25 mW的直流功耗，3.1 GHz的3 dB带宽。相信这是使用0.18 mum SiGe工艺的第一个60 GHz LNA，具有高于20 dB的增益。

4. 发明授权

US08473535B2 High-speed pulse shaping filter systems and methods 有权
标题翻译：高速脉冲整形滤波系统及方法
公开(公告)号：US08473535B2
公开(公告)日：2013-06-25
申请号：US12327279
申请日：2008-12-03
申请人： Bevin George Perumana , Arun Rachamadugu , Stephane Pinel , Joy Laskar
发明人： Bevin George Perumana , Arun Rachamadugu , Stephane Pinel , Joy Laskar
IPC分类号： G06F17/10
CPC分类号： H03H15/00 , H03H2015/002
摘要： A first system and method relates to an analog current-mode method using branch systems. In the analog current-mode implementation, multiple branches systems can be scaled according to filter coefficients and switched using known data points. Positive coefficients can add current to the summing node, while negative coefficients can remove current from the summing node. Switches can be implemented with quick charge/discharge paths in order to operate at very high data rates. A second system and method relates to a digital look-up table based high-speed implementation. In the digital implementation, outputs can be pre-calculated as an n-bit output word that drives an n-bit DAC. Each bit of the n-bit word can then described as an independent function of the known data points. Each such function can be implemented as a high-speed combinational logic block. Both systems and methods enable the implementation of pulse shaping filters for multi-gigabit per second data transmission.
摘要翻译：第一系统和方法涉及使用分支系统的模拟电流模式方法。在模拟电流模式实现中，可以根据滤波器系数对多个分支系统进行缩放，并使用已知的数据点进行切换。正系数可以向求和节点添加电流，而负系数可以去除求和节点的电流。开关可以通过快速充电/放电路径实现，以便以非常高的数据速率运行。第二系统和方法涉及基于数字查找表的高速实现。在数字实现中，可以将输出预先计算为驱动n位DAC的n位输出字。 n位字的每个位可以被描述为已知数据点的独立函数。每个这样的功能可以被实现为高速组合逻辑块。这两种系统和方法使得能够实现用于千兆位/秒数据传输的脉冲整形滤波器。

5. 发明授权

US08378874B2 Multi-gigabit analog to digital converter 有权
标题翻译：多千兆位模数转换器
公开(公告)号：US08378874B2
公开(公告)日：2013-02-19
申请号：US13056933
申请日：2008-07-31
申请人： Stephane Pinel , Joy Laskar
发明人： Stephane Pinel , Joy Laskar
IPC分类号： H03M1/34
CPC分类号： H03M1/361 , H03K5/08 , H03K5/2472 , H03M1/0636 , H03M1/1215 , H03M1/20
摘要： An analog to digital converter for operating at high speeds can be implemented with a micro-comparator/sampler, an encoder, and a selector. The micro-comparator includes an input from an antenna of a receiver/transceiver system; a transistor pair; reset transistor; cascaded inverters; an inverter circuit; a buffer; and a D flip flop circuit. Depending on the number of micro-comparator/samplers placed in parallel, a number of bits can be generated. For example, 15 bits from 15 different micro-comparator/samplers can be inserted into a 15 to 4 bit encoder to generate 4 bits.
摘要翻译：可以使用微比较器/采样器，编码器和选择器来实现用于高速操作的模数转换器。微型比较器包括来自接收器/收发器系统的天线的输入; 晶体管对; 复位晶体管; 级联逆变器; 逆变器电路; 一个缓冲区和D触发电路。根据并行放置的微比较器/采样器的数量，可以产生多个位。例如，15个不同的微比较器/采样器的15位可以插入15到4位编码器中，以生成4位。

6. 发明授权

US08081948B2 Analog signal processor in a multi-gigabit receiver system 有权
标题翻译：模拟信号处理器在一个多吉比特接收机系统中
公开(公告)号：US08081948B2
公开(公告)日：2011-12-20
申请号：US12447163
申请日：2007-10-25
申请人： Stephane Pinel , Joy Laskar , David Yeh , Bevin George Perumana , Saikat Sarkar
发明人： Stephane Pinel , Joy Laskar , David Yeh , Bevin George Perumana , Saikat Sarkar
IPC分类号： H04B1/16
CPC分类号： G06G7/12
摘要： An analog multi-gigabit receiver and/or transceiver can be implemented for the reception and demodulation of multi-gigabits quadrature phase shift keying (QPSK) modulated using a CMOS (complementary metal-oxide semiconductor) process. Further, an analog multi-gigabit receiver and/or transceiver can be implemented for the reception and demodulation of multi-gigabits binary phase shift keying (BPSK), minimum shift keying (MSK), and/or amplitude shift keying (ASK) signal modulated in CMOS processes.
摘要翻译：可以实现模拟多吉比特接收机和/或收发机用于使用CMOS（互补金属氧化物半导体）工艺调制的多吉比特正交相移键控（QPSK）的接收和解调。此外，可以实现模拟多吉比特接收机和/或收发器用于接收和解调多吉比特二进制相移键控（BPSK），最小移位键控（MSK）和/或幅度键控（ASK）信号调制在CMOS工艺中。

7. 发明授权

US08067987B2 Millimeter-wave wideband voltage controlled oscillator 有权
标题翻译：毫米波宽带压控振荡器
公开(公告)号：US08067987B2
公开(公告)日：2011-11-29
申请号：US12682352
申请日：2008-10-10
申请人： Padmanava Sen , Saikat Sarkar , Stephane Pinel , Joy Laskar , Francesco Barale
发明人： Padmanava Sen , Saikat Sarkar , Stephane Pinel , Joy Laskar , Francesco Barale
IPC分类号： H03L7/00
CPC分类号： H03K23/483 , H03B5/1852 , H03B21/02 , H03J3/185 , H03L7/099 , H03L7/193 , H03L7/24
摘要： A voltage controlled oscillator-phase lock loop (VCO-PLL) system includes a voltage controlled oscillator (VCO) system implementing four-channel architecture, such that two bands support two channels; a phase-locked-loop (PLL) system; and a mixer system. The VCO system further includes a control circuit; a first cross-coupled oscillator system adapted to receive a source voltage; a second cross-coupled oscillator system adapted to receive the source voltage; and a plurality of isolation buffer systems adapted to protect the first and second cross-coupled oscillator systems.
摘要翻译：压控振荡器锁相环（VCO-PLL）系统包括实施四通道架构的压控振荡器（VCO）系统，使得两个频带支持两个通道; 锁相环（PLL）系统; 和搅拌机系统。 VCO系统还包括控制电路; 适于接收源电压的第一交叉耦合振荡器系统; 适于接收源电压的第二交叉耦合振荡器系统; 以及适于保护第一和第二交叉耦合振荡器系统的多个隔离缓冲器系统。

8. 发明授权

US07864113B2 Module, filter, and antenna technology for millimeter waves multi-gigabits wireless systems 有权
标题翻译：毫米波多吉比特无线系统的模块，滤波器和天线技术
公开(公告)号：US07864113B2
公开(公告)日：2011-01-04
申请号：US11394498
申请日：2006-03-31
申请人： Stephane Pinel , Joy Laskar
发明人： Stephane Pinel , Joy Laskar
IPC分类号： H01Q1/38
CPC分类号： H01P11/007 , H01P1/20327 , H01P1/2039 , H01P11/008 , H01Q1/38 , H01Q21/0006 , H01Q21/0087 , H01Q21/065 , H01Q21/08 , H01Q23/00 , Y10T29/49002 , Y10T29/49016 , Y10T29/4913 , Y10T29/49165 , Y10T156/10
摘要： A method of fabricating an ultra-high frequency module is disclosed. The method includes providing a top layer; drilling the top layer; milling the top layer; providing a bottom; milling the bottom layer to define a bottom layer cavity; aligning the top layer and the bottom layer; and adhering the top layer to the bottom layer. The present invention also includes an ultra-high frequency module operating at ultra-high speeds having a top layer, the top layer defining a top layer cavity; a bottom layer, the bottom layer defining a bottom layer cavity; and an adhesive adhering both the top layer to the bottom layer, wherein the top layer and the bottom layer are formed from a large area panel of a printed circuit board.
摘要翻译：公开了一种制造超高频模块的方法。该方法包括提供顶层; 钻顶层; 研磨顶层; 提供底部研磨底层以限定底层腔; 对齐顶层和底层; 并将顶层粘附到底层。本发明还包括以超高速运行的超高频模块，其具有顶层，顶层限定顶层空腔; 底层，底层限定底层空腔; 以及粘合上层到底层的粘合剂，其中顶层和底层由印刷电路板的大面积面板形成。

9. 发明申请

US20100214026A1 MILLIMETER-WAVE WIDEBAND VOLTAGE CONTROLLED OSCILLATOR 有权
标题翻译：毫米波宽频电压控制振荡器
公开(公告)号：US20100214026A1
公开(公告)日：2010-08-26
申请号：US12682352
申请日：2008-10-10
申请人： Padmanava Sen , Saikat Sarkar , Stephane Pinel , Joy Laskar , Francesco Barale
发明人： Padmanava Sen , Saikat Sarkar , Stephane Pinel , Joy Laskar , Francesco Barale
IPC分类号： H03L7/099
CPC分类号： H03K23/483 , H03B5/1852 , H03B21/02 , H03J3/185 , H03L7/099 , H03L7/193 , H03L7/24
摘要： A voltage controlled oscillator-phase lock loop (VCO-PLL) system includes a voltage controlled oscillator (VCO) system implementing four-channel architecture, such that two bands support two channels; a phase-locked-loop (PLL) system; and a mixer system. The VCO system further includes a control circuit; a first cross-coupled oscillator system adapted to receive a source voltage; a second cross-coupled oscillator system adapted to receive the source voltage; and a plurality of isolation buffer systems adapted to protect the first and second cross-coupled oscillator systems.
摘要翻译：压控振荡器锁相环（VCO-PLL）系统包括实施四通道架构的压控振荡器（VCO）系统，使得两个频带支持两个通道; 锁相环（PLL）系统; 和搅拌机系统。 VCO系统还包括控制电路; 适于接收源电压的第一交叉耦合振荡器系统; 适于接收源电压的第二交叉耦合振荡器系统; 以及适于保护第一和第二交叉耦合振荡器系统的多个隔离缓冲器系统。

10. 发明申请

US20090140784A1 HIGH-SPEED PULSE SHAPING FILTER SYSTEMS AND METHODS 有权
标题翻译：高速脉冲形状滤波器系统和方法
公开(公告)号：US20090140784A1
公开(公告)日：2009-06-04
申请号：US12327279
申请日：2008-12-03
申请人： Bevin George PERUMANA , Arun Rachamadugu , Stephane Pinel , Joy Laskar
发明人： Bevin George PERUMANA , Arun Rachamadugu , Stephane Pinel , Joy Laskar
IPC分类号： H03L7/00 , H03K5/01
CPC分类号： H03H15/00 , H03H2015/002
摘要： A first system and method relates to an analog current-mode method using branch systems. In the analog current-mode implementation, multiple branches systems can be scaled according to filter coefficients and switched using known data points. Positive coefficients can add current to the summing node, while negative coefficients can remove current from the summing node. Switches can be implemented with quick charge/discharge paths in order to operate at very high data rates. A second system and method relates to a digital look-up table based high-speed implementation. In the digital implementation, outputs can be pre-calculated as an n-bit output word that drives an n-bit DAC. Each bit of the n-bit word can then described as an independent function of the known data points. Each such function can be implemented as a high-speed combinational logic block. Both systems and methods enable the implementation of pulse shaping filters for multi-gigabit per second data transmission.
摘要翻译：第一系统和方法涉及使用分支系统的模拟电流模式方法。在模拟电流模式实现中，可以根据滤波器系数对多个分支系统进行缩放，并使用已知的数据点进行切换。正系数可以向求和节点添加电流，而负系数可以从求和节点去除电流。开关可以通过快速充电/放电路径实现，以便以非常高的数据速率运行。第二系统和方法涉及基于数字查找表的高速实现。在数字实现中，可以将输出预先计算为驱动n位DAC的n位输出字。 n位字的每个位可以被描述为已知数据点的独立函数。每个这样的功能可以被实现为高速组合逻辑块。这两种系统和方法使得能够实现用于千兆位/秒数据传输的脉冲整形滤波器。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式