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1. 发明授权

US07830199B2 Dynamically-driven deep n-well circuit 有权
标题翻译：动态驱动深n阱电路
公开(公告)号：US07830199B2
公开(公告)日：2010-11-09
申请号：US12166559
申请日：2008-07-02
申请人： Janet M. Brunsilius , Stephen R. Kosic , Corey D. Petersen
发明人： Janet M. Brunsilius , Stephen R. Kosic , Corey D. Petersen
IPC分类号： H03K3/01
CPC分类号： H03K17/162 , H01L21/823878 , H01L21/823892 , H01L27/0921 , H01L27/0928 , H03K2217/0018
摘要： A circuit includes an NMOS transistor having a drain and a source, a p-well containing the drain and the source, an n-well under the p-well, and a first well switch configured to selectively connect the n-well to a predetermined voltage in response to an enable phase of a first switching signal. The first well switch can be configured to connect the n-well to the predetermined voltage during the enable phase of the first switching signal and to electrically float the n-well during a non-enable phase of the first switching signal.
摘要翻译：电路包括具有漏极和源极的NMOS晶体管，包含漏极和源极的p阱，p阱下面的n阱以及被配置为将n阱选择性地连接到预定的响应于第一开关信号的使能相位的电压。第一阱开关可以被配置为在第一开关信号的使能阶段期间将n阱连接到预定电压，并且在第一开关信号的非使能阶段期间使n阱电浮动。

2. 发明申请

US20110025407A1 DYNAMICALLY DRIVEN DEEP N-WELL CIRCUIT 审中-公开
标题翻译：动态驱动深层N电路
公开(公告)号：US20110025407A1
公开(公告)日：2011-02-03
申请号：US12902896
申请日：2010-10-12
申请人： Janet M. BRUNSILIUS , Stephen R. KOSIC , Corey D. PETERSEN
发明人： Janet M. BRUNSILIUS , Stephen R. KOSIC , Corey D. PETERSEN
IPC分类号： H03K3/01
CPC分类号： H03K17/162 , H01L21/823878 , H01L21/823892 , H01L27/0921 , H01L27/0928 , H03K2217/0018
摘要： A circuit can include an NMOS transistor having a drain and a source, a p-well containing the drain and the source, an n-well under the p-well, a circuit node, and a connection element connecting the n-well to the circuit node. The connection element can include a diode having an anode terminal connected to the circuit node and a cathode terminal connected to the n-well, a resistor having a first terminal connected to the circuit node and a second terminal connected to the n-well, a conductor directly connecting the n-well to the circuit node, or a well switch configured to connect the n-well to the circuit node during an enable phase of a switching signal and to electrically float the n-well during a non-enable phase of the switching signal. The diode can include a diode-connected transistor. The circuit node can be configured to receive a predetermined voltage having a magnitude equal to or greater than an upper supply voltage.
摘要翻译：电路可以包括具有漏极和源极的NMOS晶体管，包含漏极和源极的p阱，p阱下面的n阱，电路节点和将n阱连接到电路节点。连接元件可以包括具有连接到电路节点的阳极端子和连接到n阱的阴极端子的二极管，具有连接到电路节点的第一端子和连接到n阱的第二端子的电阻器，直接连接n阱到电路节点的导体，或者在开关信号的使能阶段期间配置成将n阱连接到电路节点的阱开关，并且在非使能阶段期间使n阱电浮动开关信号。二极管可以包括二极管连接的晶体管。电路节点可以被配置为接收具有等于或大于上电源电压的幅度的预定电压。

3. 发明申请

US20100001787A1 DYNAMICALLY-DRIVEN DEEP N-WELL CIRCUIT 有权
标题翻译：动态深潜电路
公开(公告)号：US20100001787A1
公开(公告)日：2010-01-07
申请号：US12166559
申请日：2008-07-02
申请人： Janet M. Brunsilius , Stephen R. Kosic , Corey D. Petersen
发明人： Janet M. Brunsilius , Stephen R. Kosic , Corey D. Petersen
IPC分类号： H03K3/01 , H01L21/336
CPC分类号： H03K17/162 , H01L21/823878 , H01L21/823892 , H01L27/0921 , H01L27/0928 , H03K2217/0018
摘要： A circuit includes an NMOS transistor having a drain and a source, a p-well containing the drain and the source, an n-well under the p-well, and a first well switch configured to selectively connect the n-well to a predetermined voltage in response to an enable phase of a first switching signal. The first well switch can be configured to connect the n-well to the predetermined voltage during the enable phase of the first switching signal and to electrically float the n-well during a non-enable phase of the first switching signal.
摘要翻译：电路包括具有漏极和源极的NMOS晶体管，包含漏极和源极的p阱，p阱下面的n阱以及被配置为将n阱选择性地连接到预定的响应于第一开关信号的使能相位的电压。第一阱开关可以被配置为在第一开关信号的使能阶段期间将n阱连接到预定电压，并且在第一开关信号的非使能阶段期间使n阱电浮动。

4. 发明授权

US07692489B2 Differential two-stage miller compensated amplifier system with capacitive level shifting 有权
标题翻译：差分两级米勒补偿放大器系统，具有电容电平转换
公开(公告)号：US07692489B2
公开(公告)日：2010-04-06
申请号：US11305069
申请日：2005-12-16
申请人： Daniel F. Kelly , Lawrence Singer , Steven Decker , Stephen R. Kosic
发明人： Daniel F. Kelly , Lawrence Singer , Steven Decker , Stephen R. Kosic
IPC分类号： H03F3/45
CPC分类号： H03F3/45183 , H03F1/086 , H03F1/14 , H03F3/45475 , H03F3/45654 , H03F3/45744 , H03F3/45968 , H03F2200/54 , H03F2203/45422 , H03F2203/45424 , H03F2203/45512 , H03F2203/45652
摘要： A differential two-stage Miller compensated amplifier system with capacitive level shifting includes a first stage differential transconductance amplifier including first and second output nodes and an output common mode voltage, a second stage differential transconductance amplifier including non-inverting and inverting inputs and outputs and an input common mode voltage, and a level shifting capacitor circuit coupled between the first and second output nodes and the non-inverting and inverting inputs for level shifting between the output common mode voltage of the first stage and the input common mode voltage of the second stage.
摘要翻译：具有电容电平偏移的差分两级米勒补偿放大器系统包括包括第一和第二输出节点和输出共模电压的第一级差分跨导放大器，包括非反相和反相输入和输出的第二级差分跨导放大器和输入共模电压和耦合在第一和第二输出节点之间的电平移动电容器电路和用于在第一级的输出共模电压和第二级的输入共模电压之间的电平移位的非反相和反相输入。

5. 发明授权

US09397651B2 Dynamically driven deep n-well circuit 有权
标题翻译：动态驱动深n阱电路
公开(公告)号：US09397651B2
公开(公告)日：2016-07-19
申请号：US12902896
申请日：2010-10-12
申请人： Janet M. Brunsilius , Stephen R. Kosic , Corey D. Petersen
发明人： Janet M. Brunsilius , Stephen R. Kosic , Corey D. Petersen
IPC分类号： H03K3/01 , H03K17/16 , H01L21/8238 , H01L27/092
CPC分类号： H03K17/162 , H01L21/823878 , H01L21/823892 , H01L27/0921 , H01L27/0928 , H03K2217/0018
摘要： A circuit can include an NMOS transistor having a drain and a source, a p-well containing the drain and the source, an n-well under the p-well, a circuit node, and a connection element connecting the n-well to the circuit node. The connection element can include a diode having an anode terminal connected to the circuit node and a cathode terminal connected to the n-well, a resistor having a first terminal connected to the circuit node and a second terminal connected to the n-well, a conductor directly connecting the n-well to the circuit node, or a well switch configured to connect the n-well to the circuit node during an enable phase of a switching signal and to electrically float the n-well during a non-enable phase of the switching signal. The diode can include a diode-connected transistor. The circuit node can be configured to receive a predetermined voltage having a magnitude equal to or greater than an upper supply voltage.
摘要翻译：电路可以包括具有漏极和源极的NMOS晶体管，包含漏极和源极的p阱，p阱下面的n阱，电路节点和将n阱连接到电路节点。连接元件可以包括具有连接到电路节点的阳极端子和连接到n阱的阴极端子的二极管，具有连接到电路节点的第一端子和连接到n阱的第二端子的电阻器，直接连接n阱到电路节点的导体，或者在开关信号的使能阶段期间配置成将n阱连接到电路节点的阱开关，并且在非使能阶段期间使n阱电浮动开关信号。二极管可以包括二极管连接的晶体管。电路节点可以被配置为接收具有等于或大于上电源电压的幅度的预定电压。

6. 发明授权

US08773294B2 Background techniques for comparator calibration 有权
标题翻译：比较校准的背景技术
公开(公告)号：US08773294B2
公开(公告)日：2014-07-08
申请号：US13490673
申请日：2012-06-07
申请人： Stephen R. Kosic , Jeffrey P. Bray
发明人： Stephen R. Kosic , Jeffrey P. Bray
IPC分类号： H03M1/10
CPC分类号： H03M1/1023 , H03M1/167 , H03M1/765
摘要： A method and a corresponding device for performing a background calibration of a comparator in a circuit having a plurality of stages that are connected in a pipelined fashion to an input signal. A digital value of a residue signal, which is output from a first stage in the plurality of stages to a subsequent stage in the plurality of stages, is calculated. The value of the residue signal is compared to at least one threshold. Based on the comparison, a triggering threshold of a selected comparator in the first stage may be adjusted.
摘要翻译：一种用于在具有以流水线方式连接到输入信号的多个级的电路中执行比较器的背景校准的方法和相应装置。计算从多级中的第一级输出到多级的后级的残差信号的数字值。将残留信号的值与至少一个阈值进行比较。基于该比较，可以调整第一级中所选择的比较器的触发阈值。

7. 发明申请

US20130328609A1 BACKGROUND TECHNIQUES FOR COMPARATOR CALIBRATION 有权
标题翻译：用于比较器校准的背景技术
公开(公告)号：US20130328609A1
公开(公告)日：2013-12-12
申请号：US13490673
申请日：2012-06-07
申请人： Stephen R. Kosic , Jeffrey P. Bray
发明人： Stephen R. Kosic , Jeffrey P. Bray
IPC分类号： G05F1/46
CPC分类号： H03M1/1023 , H03M1/167 , H03M1/765
摘要： A method and a corresponding device for performing a background calibration of a comparator in a circuit having a plurality of stages that are connected in a pipelined fashion to an input signal. A digital value of a residue signal, which is output from a first stage in the plurality of stages to a subsequent stage in the plurality of stages, is calculated. The value of the residue signal is compared to at least one threshold. Based on the comparison, a triggering threshold of a selected comparator in the first stage may be adjusted.
摘要翻译：一种用于在具有以流水线方式连接到输入信号的多个级的电路中执行比较器的背景校准的方法和相应装置。计算从多级中的第一级输出到多级的后级的残差信号的数字值。将残留信号的值与至少一个阈值进行比较。基于该比较，可以调整第一级中所选择的比较器的触发阈值。

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