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1. 发明授权

US08884792B2 Variable length code decoding device and decoding method 有权
标题翻译：可变长度码解码装置及解码方法
公开(公告)号：US08884792B2
公开(公告)日：2014-11-11
申请号：US13602360
申请日：2012-09-04
申请人： Hiroaki Nakata , Fumitaka Izuhara , Kazushi Akie , Takafumi Yuasa
发明人： Hiroaki Nakata , Fumitaka Izuhara , Kazushi Akie , Takafumi Yuasa
IPC分类号： H03M7/40 , H03M7/42 , H04N19/176 , H03M7/30 , H04N19/61 , H03M7/46
CPC分类号： H03M7/425 , H03M7/30 , H03M7/40 , H03M7/46 , H04N19/115 , H04N19/12 , H04N19/176 , H04N19/61
摘要： Variable length code decoding device for decoding variable length code data, including: decoding process tables each including at least two kinds of formats consisting a first format storing identification information for designating a subsequent table to be referred to in a subsequent decoding process, and a second format that stores a decoded value obtained by repeating the decoding process and a significant bit length to be referred to with respect to variable length code data. The device utilizes first, second, third and fourth formats and relative addresses.
摘要翻译：可变长度码解码装置，用于解码可变长度码数据，包括：解码处理表，每个包括至少两种格式，包括第一格式，第一格式存储用于指定随后的解码过程中要参考的后续表的标识信息;以及第二格式，其存储通过重复解码处理而获得的解码值以及关于可变长度代码数据参考的有效位长度。该设备利用第一，第二，第三和第四格式和相对地址。

2. 发明申请

US20120326899A1 VARIABLE LENGTH CODE DECODING DEVICE AND DECODING METHOD 有权
标题翻译：可变长度代码解码器和解码方法
公开(公告)号：US20120326899A1
公开(公告)日：2012-12-27
申请号：US13602360
申请日：2012-09-04
申请人： Hiroaki NAKATA , Fumitake Izuhara , Kazushi Akie , Takafumi Yuasa
发明人： Hiroaki NAKATA , Fumitake Izuhara , Kazushi Akie , Takafumi Yuasa
IPC分类号： H03M7/40
CPC分类号： H03M7/425 , H03M7/30 , H03M7/40 , H03M7/46 , H04N19/115 , H04N19/12 , H04N19/176 , H04N19/61
摘要： Variable length code decoding device for decoding variable length code data, including: decoding process tables each including at least two kinds of formats consisting a first format storing identification information for designating a subsequent table to be referred to in a subsequent decoding process, and a second format that stores a decoded value obtained by repeating the decoding process and a significant bit length to be referred to with respect to variable length code data. The device utilizes first, second, third and fourth formats and relative addresses.
摘要翻译：可变长度码解码装置，用于解码可变长度码数据，包括：解码处理表，每个包括至少两种格式，包括第一格式，第一格式存储用于指定随后的解码过程中要参考的后续表的标识信息;以及第二格式，其存储通过重复解码处理而获得的解码值以及关于可变长度代码数据参考的有效位长度。该设备利用第一，第二，第三和第四格式和相对地址。

3. 发明授权

US08264386B2 Variable length code decoding device and decoding method 失效
标题翻译：可变长度码解码装置及解码方法
公开(公告)号：US08264386B2
公开(公告)日：2012-09-11
申请号：US12961017
申请日：2010-12-06
申请人： Hiroaki Nakata , Fumitaka Izuhara , Kazushi Akie , Takafumi Yuasa
发明人： Hiroaki Nakata , Fumitaka Izuhara , Kazushi Akie , Takafumi Yuasa
IPC分类号： H03M7/40
CPC分类号： H03M7/425 , H03M7/30 , H03M7/40 , H03M7/46 , H04N19/115 , H04N19/12 , H04N19/176 , H04N19/61
摘要： A variable length code decoding device for decoding variable length code data, including: a table memory that stores a plurality of decoding process tables having a reference relationship therein; and a decoding control unit that sequentially selects the decoding process tables according to the decoded data to control a process of decoding the variable length code data, wherein when referring to the decoding process table to perform an initial decoding of the variable length code data, the initial decoding process is conducted by a longer bit length to be clipped from the variable length code data for referring to the decoding process table than the bit length used when referring to the other portions of the decoding process table.
摘要翻译：一种用于解码可变长度码数据的可变长度码解码装置，包括：存储多个具有参考关系的解码处理表的表存储器; 以及解码控制单元，其根据解码数据依次选择解码处理表以控制对可变长度代码数据进行解码的处理，其中当参考解码处理表来执行可变长度代码数据的初始解码时，当参考解码处理表的其他部分时，使用比用于参考解码处理表的可变长度代码数据更长的比特长进行初始解码处理。

4. 发明授权

US08135164B2 Speaker 有权
标题翻译：扬声器
公开(公告)号：US08135164B2
公开(公告)日：2012-03-13
申请号：US11965248
申请日：2007-12-27
申请人： Shoji Tanaka , Hiroko Tsutsumi , Takafumi Yuasa
发明人： Shoji Tanaka , Hiroko Tsutsumi , Takafumi Yuasa
IPC分类号： H04R1/00 , H04R7/00 , H04R9/06 , H04R11/02 , H04R25/00
CPC分类号： H04R7/14 , H04R1/24 , H04R7/18
摘要： A speaker of the present invention includes the following: a diaphragm that includes an inner periphery coupled to a voice coil, and a corrugation provided at the intermediate position between the inner periphery and an outer periphery; a speaker edge for supporting the outer periphery of the diaphragm; and a damping member attached to an outer peripheral part of the diaphragm outside the vicinity of an outer periphery of the corrugation. The effective vibration area of an inner peripheral part of the diaphragm inside an inner periphery of the corrugation is substantially half or less of the total effective vibration area. The damping member is configured as a damping portion by extending an overlap portion of the speaker edge overlapping with the diaphragm to the vicinity of the outer periphery of the corrugation. This configuration can suppress the vibration transmission at high frequencies to the outer peripheral part of the diaphragm outside the corrugation, allows only the inner peripheral part of the diaphragm inside the corrugation to mainly vibrate at high frequencies, and also can suppress a resonance in the outer peripheral part of the diaphragm outside the corrugation. Thus, the speaker can have both an excellent high frequency response and an excellent mid-high frequency response.
摘要翻译：本发明的扬声器包括：隔膜，其包括耦合到音圈的内周和设置在内周与外周之间的中间位置处的波纹; 扬声器边缘，用于支撑隔膜的外周; 以及阻尼构件，其附接到所述隔膜的外周部分在所述波纹的外周附近。波纹内周内的振动膜的内周部的有效振动面积大致为总有效振动面积的一半以下。阻尼构件通过将扬声器边缘与隔膜重叠的重叠部分延伸到波纹的外周附近而被构造为阻尼部分。这种结构可以抑制波纹外部的隔膜的外周部的高频振动传播，仅允许波纹内的隔膜的内周部分以高频率主要振动，并且还可以抑制外部的共振隔膜的外围部分在波纹外面。因此，扬声器可以具有优异的高频响应和优异的中高频响应。

5. 发明申请

US20100135381A1 ENCODING/DECODING DEVICE AND VIDEO TRANSMISSION SYSTEM 审中-公开
标题翻译：编码/解码设备和视频传输系统
公开(公告)号：US20100135381A1
公开(公告)日：2010-06-03
申请号：US12621592
申请日：2009-11-19
申请人： Masaki HAMAMOTO , Masatoshi KONDO , Masatoshi TAKADA , Muneaki YAMAGUCHI , Takanobu TSUNODA , Takafumi YUASA
发明人： Masaki HAMAMOTO , Masatoshi KONDO , Masatoshi TAKADA , Muneaki YAMAGUCHI , Takanobu TSUNODA , Takafumi YUASA
IPC分类号： H04N7/12 , H04N5/225
CPC分类号： H04N21/6582 , H04N21/23406 , H04N21/2343 , H04N21/2401 , H04N21/4307 , H04N21/44004 , H04N21/6377 , H04N21/658 , H04N21/6587
摘要： The present invention relates to a video transmission system that uses an encoding/decoding technique. An object of the present invention is to refrain from using a memory for storing decoded image data, avoid a decoder input buffer problem (buffer overflow or underflow) with ease, achieve cost reduction, and provide enhanced image quality. In the video transmission system with an encoding/decoding device, a reference signal for adjusting a synchronization schedule of the entire system is generated and supplied to various sections. In addition, a timing adjustment amount for adjusting the synchronization schedule for the reference signal is generated by a decoder and supplied to a camera.
摘要翻译：本发明涉及使用编码/解码技术的视频传输系统。本发明的目的是避免使用用于存储解码图像数据的存储器，容易地避免解码器输入缓冲器问题（缓冲器溢出或下溢），实现成本降低并提供增强的图像质量。在具有编码/解码装置的视频传输系统中，生成用于调整整个系统的同步调度的参考信号并将其提供给各个部分。此外，用于调整参考信号的同步调度的定时调整量由解码器产生并提供给相机。

6. 发明授权

US07535386B2 Variable length code decoding device and decoding method 有权
标题翻译：可变长度码解码装置及解码方法
公开(公告)号：US07535386B2
公开(公告)日：2009-05-19
申请号：US11845850
申请日：2007-08-28
申请人： Hiroaki Nakata , Fumitaka Izuhara , Kazushi Akie , Takafumi Yuasa
发明人： Hiroaki Nakata , Fumitaka Izuhara , Kazushi Akie , Takafumi Yuasa
IPC分类号： H03M7/40
CPC分类号： H03M7/425 , H03M7/30 , H03M7/40 , H03M7/46 , H04N19/115 , H04N19/12 , H04N19/176 , H04N19/61
摘要： A flag indicating whether a decoding process is completed or continued is disposed in each of entries of a decoding process table. A decoded value and a significant bit length are recorded in the entry of a decoding process completion. Information for identifying the decoding process table which is used in a subsequent process, and a bit length that is clipped from a code word which is used when referring to a subsequent table are recorded in the entry of the decoding process continuation. When the decoding process starts, the information for identifying the table to be used and the bit length that is referred to from the code word when referring to the table are designated together with the code word. The decoding process table reference is repeated as the occasion demands. With the above configuration, there is provided a variable length code decoding device.
摘要翻译：指示解码处理是否完成或继续的标志被布置在解码处理表的每个条目中。在解码处理完成的条目中记录解码值和有效位长度。用于识别在后续处理中使用的解码处理表的信息和从参考后续表时使用的代码字剪切的位长度被记录在解码处理继续的条目中。当解码处理开始时，与代码字一起指定用于识别要使用的表的信息和当参考表时从代码字引用的位长度。根据需要重复解码过程表参考。通过上述结构，提供了可变长度码解码装置。

7. 发明申请

US20080294878A1 PROCESSOR SYSTEM AND EXCEPTION PROCESSING METHOD 审中-公开
标题翻译：处理器系统和异常处理方法
公开(公告)号：US20080294878A1
公开(公告)日：2008-11-27
申请号：US12101437
申请日：2008-04-11
申请人： Takafumi YUASA , Hiroaki Nakata , Koji Hosogi , Masakazu Ehama , Fumitaka Izuhara , Kazushi Akie
发明人： Takafumi YUASA , Hiroaki Nakata , Koji Hosogi , Masakazu Ehama , Fumitaka Izuhara , Kazushi Akie
IPC分类号： G06F9/38 , G06F9/302 , G06F9/312
CPC分类号： G06F11/0793 , G06F9/30054 , G06F9/3861 , G06F9/3885 , G06F9/4812 , G06F11/0721 , G06F2209/481
摘要： When an error is detected in an error detecting unit in a processor system, the error detecting unit outputs an error signal to an interrupt control unit, and the interrupt control unit outputs a value of an error address register and a control signal to a program counter control unit and rewrites a value of a program counter to a value of an error address register. By this means, the branching process by an error interrupt is realized. In this case, when the error is detected, the process of saving the value of the program counter at the time of error occurrence is not performed, and a specific save register and a control circuit for the recovery to the address at the time of the error occurrence after the end of the error processing are not provided.
摘要翻译：当在处理器系统中的错误检测单元中检测到错误时，错误检测单元向中断控制单元输出错误信号，并且中断控制单元向程序计数器输出错误地址寄存器和控制信号的值控制单元，并将程序计数器的值重写为错误地址寄存器的值。通过这种方式，实现了通过错误中断的分支过程。在这种情况下，当检测到错误时，不执行在发生错误时保存程序计数器的值的处理，以及特定的存储寄存器和控制电路，用于恢复到发生错误时的地址未提供错误处理结束后的错误发生。

8. 发明授权

US08223838B2 Parallel processing circuit for intra-frame prediction 失效
标题翻译：用于帧内预测的并行处理电路
公开(公告)号：US08223838B2
公开(公告)日：2012-07-17
申请号：US11834449
申请日：2007-08-06
申请人： Kenichi Iwata , Seiji Mochizuki , Tetsuya Shibayama , Fumitaka Izuhara , Hiroshi Ueda , Yukifumi Kobayashi , Hiroaki Nakata , Koji Hosogi , Masakazu Ehama , Takafumi Yuasa
发明人： Kenichi Iwata , Seiji Mochizuki , Tetsuya Shibayama , Fumitaka Izuhara , Hiroshi Ueda , Yukifumi Kobayashi , Hiroaki Nakata , Koji Hosogi , Masakazu Ehama , Takafumi Yuasa
IPC分类号： H04N7/12 , H04N11/02 , H04N11/04 , H04B1/66
CPC分类号： H04N19/436 , H04N19/176 , H04N19/593
摘要： The present invention provides a functional block that executes video coding and video decoding based on H.264/AVC. The functional block includes two moving picture processing units, and a memory unit that stores therein data related to the results of processing of first plural macroblocks arranged within one row of one picture by the first moving picture processing unit. Data related to the results of processing of plural adjacent macroblocks, which are selected from the data stored in the memory unit, are transferred to the second moving picture processing unit. The second moving picture processing unit performs processing of one macroblock of second plural macroblocks arranged in the following row, using the transferred data.
摘要翻译：本发明提供一种执行基于H.264 / AVC的视频编码和视频解码的功能块。功能块包括两个运动图像处理单元，以及存储单元，其存储与第一运动图像处理单元一行布置在一行内的第一多个宏块的处理结果有关的数据。与从存储在存储单元中的数据中选择的多个相邻宏块的处理结果有关的数据被传送到第二运动图像处理单元。第二运动图像处理单元使用传送的数据来执行排列在下一行中的第二多个宏块的一个宏块的处理。

9. 发明申请

US20110080308A1 VARIABLE LENGTH CODE DECODING DEVICE AND DECODING METHOD 失效
标题翻译：可变长度代码解码器和解码方法
公开(公告)号：US20110080308A1
公开(公告)日：2011-04-07
申请号：US12961017
申请日：2010-12-06
申请人： Hiroaki NAKATA , Fumitaka Izuhara , Kazushi Akie , Takafumi Yuasa
发明人： Hiroaki NAKATA , Fumitaka Izuhara , Kazushi Akie , Takafumi Yuasa
IPC分类号： H03M7/40
CPC分类号： H03M7/425 , H03M7/30 , H03M7/40 , H03M7/46 , H04N19/115 , H04N19/12 , H04N19/176 , H04N19/61
摘要： A variable length code decoding device for decoding variable length code data, including: a table memory that stores a plurality of decoding process tables having a reference relationship therein; and a decoding control unit that sequentially selects the decoding process tables according to the decoded data to control a process of decoding the variable length code data, wherein when referring to the decoding process table to perform an initial decoding of the variable length code data, the initial decoding process is conducted by a longer bit length to be clipped from the variable length code data for referring to the decoding process table than the bit length used when referring to the other portions of the decoding process table.
摘要翻译：一种用于解码可变长度码数据的可变长度码解码装置，包括：存储多个具有参考关系的解码处理表的表存储器; 以及解码控制单元，其根据解码数据依次选择解码处理表以控制对可变长度代码数据进行解码的处理，其中当参考解码处理表来执行可变长度代码数据的初始解码时，当参考解码处理表的其他部分时，使用比用于参考解码处理表的可变长度代码数据更长的比特长进行初始解码处理。

10. 发明申请

US20110013696A1 MOVING IMAGE PROCESSOR AND PROCESSING METHOD FOR MOVING IMAGE 有权
标题翻译：移动图像处理器和移动图像的处理方法
公开(公告)号：US20110013696A1
公开(公告)日：2011-01-20
申请号：US12819394
申请日：2010-06-21
申请人： Yoshitaka HIRAMATSU , Hiroaki NAKATA , Masakazu EHAMA , Seiji MOCHIZUKI , Takafumi YUASA , Kenichi IWATA
发明人： Yoshitaka HIRAMATSU , Hiroaki NAKATA , Masakazu EHAMA , Seiji MOCHIZUKI , Takafumi YUASA , Kenichi IWATA
IPC分类号： H04N7/26 , H04N7/32 , H04N11/02
CPC分类号： H04N19/86 , H04N19/423 , H04N19/436
摘要： A moving image processor includes a first and a second moving image processing unit which are able to perform parallel operation, and a data transfer unit having a first buffer and a second buffer. The first moving image processing unit processes macroblocks MB00, - - - , of one row of one image sequentially, and the second moving image processing unit processes macroblocks MB10, - - - , of the next row sequentially. The first and the second moving image processors include a first and a second deblocking filters, respectively. Operation timing of the second filter is delayed by the processing time of two macroblocks, compared with operation timing of the first filter. The processing results of the first filter and the second filter are transferred to an external memory via the first buffer and the second buffer of the transfer unit.
摘要翻译：运动图像处理器包括能够执行并行操作的第一和第二运动图像处理单元，以及具有第一缓冲器和第二缓冲器的数据传送单元。第一运动图像处理单元顺序地处理一行一个图像的宏块MB00，...，并且第二运动图像处理单元依次处理下一行的宏块MB10， - - - 。第一和第二运动图像处理器分别包括第一和第二去块滤波器。与第一滤波器的操作定时相比，第二滤波器的操作定时被延迟两个宏块的处理时间。第一滤波器和第二滤波器的处理结果经由传送单元的第一缓冲器和第二缓冲器传送到外部存储器。

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