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1. 发明授权

US09041638B2 Liquid crystal driving circuit having a common-signal output circuit and a segment-signal output circuit and method 有权
标题翻译：具有公共信号输出电路和段信号输出电路及方法的液晶驱动电路
公开(公告)号：US09041638B2
公开(公告)日：2015-05-26
申请号：US13191075
申请日：2011-07-26
申请人： Norikazu Katagiri , Tetsuya Tokunaga , Mamoru Yamaguchi , Hiroyuki Nakamura
发明人： Norikazu Katagiri , Tetsuya Tokunaga , Mamoru Yamaguchi , Hiroyuki Nakamura
IPC分类号： G09G3/36 , G09G3/18
CPC分类号： G09G3/18 , G09G2310/0267 , G09G2310/0275
摘要： A liquid-crystal-driving circuit includes: a plurality of resistors connected in series between a first and second potentials; one or more voltage follower circuits to impedance-convert one or more intermediate potentials between the first and second potentials, to be outputted, respectively, the intermediate potentials generated at one or more connection points between the resistors, respectively; a common-signal-output circuit to supply common signals to common electrodes of a liquid-crystal panel, respectively, the common signals each being at the first and second potentials, and the intermediate potentials; and a segment-signal-output circuit to supply segment signals to segment electrodes of the panel, respectively, the segment signals each being at the first and second potentials, and the intermediate potentials according to the common signals, the segment-signal output circuit to change the potentials of the segment signals in a ramp form, at least if the potentials of the segment signals are changed with a maximum-possible-potential difference.
摘要翻译：液晶驱动电路包括：串联连接在第一和第二电位之间的多个电阻器; 一个或多个电压跟随器电路，用于阻抗转换第一和第二电位之间的一个或多个中间电位，分别输出在电阻器之间的一个或多个连接点产生的中间电位; 公共信号输出电路，分别向液晶面板的公共电极提供公共信号，每个共同信号处于第一和第二电位以及中间电位; 以及分段信号输出电路，分别将分段信号提供给面板的分段电极，每个分别处于第一和第二电位的分段信号和根据公共信号的中间电位，分段信号输出电路至少如果段信号的电位以最大可能电位差改变，则以斜坡形式改变段信号的电位。

2. 发明授权

US08941571B2 Liquid crystal driving circuit 有权
标题翻译：液晶驱动电路
公开(公告)号：US08941571B2
公开(公告)日：2015-01-27
申请号：US13584397
申请日：2012-08-13
申请人： Norikazu Katagiri , Tetsuya Tokunaga , Tomoshi Yoshida , Kensuke Goto , Mamoru Yamaguchi
发明人： Norikazu Katagiri , Tetsuya Tokunaga , Tomoshi Yoshida , Kensuke Goto , Mamoru Yamaguchi
IPC分类号： G09G3/36 , G09G3/04
CPC分类号： G09G3/3655 , G09G3/04 , G09G3/3614 , G09G3/3696 , G09G2330/025
摘要： A liquid-crystal-driving circuit includes: resistors connected in series between first and second potentials lower than the first potential; one or more voltage follower circuits to impedance-convert one or more intermediate potentials between the first and second potentials, to be outputted, respectively, the intermediate potentials generated at one or more connection points between the resistors, respectively; a common-signal-output circuit to supply common signals to common electrodes of a liquid crystal panel, respectively, the common signals being at the first, second, or one or more intermediate potentials in a predetermined order; and a segment-signal output circuit supplies segment signals to segment electrodes of the liquid crystal panel, respectively, the segment signals being at the first and second potentials, or the intermediate potentials according to the common signals, wherein the segment-signal output circuit increases impedances of the segment signals only for a first period when the of segment signals potentials are switched.
摘要翻译：液晶驱动电路包括：电阻器，其串联连接在低于第一电位的第一和第二电位之间; 一个或多个电压跟随器电路，用于阻抗转换第一和第二电位之间的一个或多个中间电位，分别输出在电阻器之间的一个或多个连接点产生的中间电位; 公共信号输出电路，分别向液晶面板的公共电极提供公共信号，共同信号处于第一，第二或一个或多个中间电位，以预定顺序; 分段信号输出电路分别将分段信号提供给液晶面板的分段电极，根据公共信号分段信号处于第一和第二电位或中间电位，其中分段信号输出电路增加段信号的阻抗仅在片段信号电位切换时的第一周期。

3. 发明授权

US08238385B2 Data processing circuit and data processing method 有权
标题翻译：数据处理电路和数据处理方法
公开(公告)号：US08238385B2
公开(公告)日：2012-08-07
申请号：US11778947
申请日：2007-07-17
申请人： Hiroyuki Arai , Tetsuya Tokunaga , Yasuo Osawa , Kensuke Goto , Yoshiyuki Yamagata , Takeshi Kimura
发明人： Hiroyuki Arai , Tetsuya Tokunaga , Yasuo Osawa , Kensuke Goto , Yoshiyuki Yamagata , Takeshi Kimura
IPC分类号： H04J3/04
CPC分类号： H04L7/02
摘要： A data processing circuit comprising: a first circuit configured to time-division-multiplex a first digital signal synchronous with a clock signal input from an external controller and a second digital signal asynchronous with the clock signal; and a second circuit configured to output a digital signal time-division-multiplexed by the first circuit to the controller.
摘要翻译：一种数据处理电路，包括：第一电路，被配置为对与从外部控制器输入的时钟信号同步的第一数字信号和与时钟信号异步的第二数字信号进行时分复用; 以及第二电路，被配置为将由第一电路进行时分复用的数字信号输出到控制器。

4. 发明申请

US20120026153A1 Liquid Crystal Driving Circuit 有权
标题翻译：液晶驱动电路
公开(公告)号：US20120026153A1
公开(公告)日：2012-02-02
申请号：US13191075
申请日：2011-07-26
申请人： Norikazu Katagiri , Tetsuya Tokunaga , Mamoru Yamaguchi , Hiroyuki Nakamura
发明人： Norikazu Katagiri , Tetsuya Tokunaga , Mamoru Yamaguchi , Hiroyuki Nakamura
IPC分类号： G09G5/00 , G09G3/36
CPC分类号： G09G3/18 , G09G2310/0267 , G09G2310/0275
摘要： A liquid-crystal-driving circuit includes: a plurality of resistors connected in series between a first and second potentials; one or more voltage follower circuits to impedance-convert one or more intermediate potentials between the first and second potentials, to be outputted, respectively, the intermediate potentials generated at one or more connection points between the resistors, respectively; a common-signal-output circuit to supply common signals to common electrodes of a liquid-crystal panel, respectively, the common signals each being at the first and second potentials, and the intermediate potentials; and a segment-signal-output circuit to supply segment signals to segment electrodes of the panel, respectively, the segment signals each being at the first and second potentials, and the intermediate potentials according to the common signals, the segment-signal output circuit to change the potentials of the segment signals in a ramp form, at least if the potentials of the segment signals are changed with a maximum-possible-potential difference.
摘要翻译：液晶驱动电路包括：串联连接在第一和第二电位之间的多个电阻器; 一个或多个电压跟随器电路，用于阻抗转换第一和第二电位之间的一个或多个中间电位，分别输出在电阻器之间的一个或多个连接点产生的中间电位; 公共信号输出电路，分别向液晶面板的公共电极提供公共信号，每个共同信号处于第一和第二电位以及中间电位; 以及分段信号输出电路，分别将分段信号提供给面板的分段电极，每个分别处于第一和第二电位的分段信号和根据公共信号的中间电位，分段信号输出电路至少如果段信号的电位以最大可能电位差改变，则以斜坡形式改变段信号的电位。

5. 发明授权

US07619547B2 Serial-to-parallel converter circuit and liquid crystal display driving circuit 有权
标题翻译：串并转换电路和液晶显示驱动电路
公开(公告)号：US07619547B2
公开(公告)日：2009-11-17
申请号：US12044867
申请日：2008-03-07
申请人： Yoshiyuki Yamagata , Tetsuya Tokunaga , Yasuo Osawa , Kensuke Goto
发明人： Yoshiyuki Yamagata , Tetsuya Tokunaga , Yasuo Osawa , Kensuke Goto
IPC分类号： H03M9/00
CPC分类号： H03M9/00 , G09G3/2096 , G09G3/3688 , G09G2310/08
摘要： A serial-to-parallel converter circuit comprising: an m-bit serial data holding unit to be input with serial data whose input bit number is set to m or n (
摘要翻译：一种串并转换器电路，包括：m位串行数据保持单元，用于输入其输入位数设置为m或传输周期内的n（

6. 发明申请

US20080019400A1 Data Processing Circuit and Data Processing Method 有权
标题翻译：数据处理电路和数据处理方法
公开(公告)号：US20080019400A1
公开(公告)日：2008-01-24
申请号：US11778947
申请日：2007-07-17
申请人： Hiroyuki Arai , Tetsuya Tokunaga , Yasuo Osawa , Kensuke Goto , Yoshiyuki Yamagata , Takeshi Kimura
发明人： Hiroyuki Arai , Tetsuya Tokunaga , Yasuo Osawa , Kensuke Goto , Yoshiyuki Yamagata , Takeshi Kimura
IPC分类号： H04J3/06 , G06F1/00
CPC分类号： H04L7/02
摘要： A data processing circuit comprising: a first circuit configured to time-division-multiplex a first digital signal synchronous with a clock signal input from an external controller and a second digital signal asynchronous with the clock signal; and a second circuit configured to output a digital signal time-division-multiplexed by the first circuit to the controller.
摘要翻译：一种数据处理电路，包括：第一电路，被配置为对与从外部控制器输入的时钟信号同步的第一数字信号和与时钟信号异步的第二数字信号进行时分复用; 以及第二电路，被配置为将由第一电路进行时分复用的数字信号输出到控制器。

7. 发明授权

US06680221B2 Bare chip mounting method and bare chip mounting system 失效
标题翻译：裸芯片安装方法和裸芯片安装系统
公开(公告)号：US06680221B2
公开(公告)日：2004-01-20
申请号：US10267668
申请日：2002-10-10
申请人： Tetsuya Tokunaga , Takahiro Yonezawa , Hiroyuki Kiyomura , Tatsuo Sasaoka , Satoshi Horie
发明人： Tetsuya Tokunaga , Takahiro Yonezawa , Hiroyuki Kiyomura , Tatsuo Sasaoka , Satoshi Horie
IPC分类号： H01L2144
CPC分类号： H01L24/81 , H01L21/6836 , H01L24/11 , H01L24/75 , H01L2221/68327 , H01L2224/1134 , H01L2224/13099 , H01L2224/13144 , H01L2224/45144 , H01L2224/75 , H01L2224/81801 , H01L2924/01004 , H01L2924/01033 , H01L2924/01039 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/00014 , H01L2924/00
摘要： A bare chip mounting method includes: a dicing step for dividing a semiconductor wafer into individual IC chips while the semiconductor wafer is being attached to a carrier; a washing step for washing the diced semiconductor wafer; a bump-bonding for carrying the washed semiconductor wafer to an assembly process while the semiconductor wafer is being attached to the carrier so as to form a bump on an electrode pad of the wafer; and a mounting step for mounting each of the IC chips, on which the bump is formed, onto a circuit formation body.
摘要翻译：裸芯片安装方法包括：切割步骤，用于在将半导体晶片附着到载体上的同时将半导体晶片分成单独的IC芯片; 用于洗涤切割的半导体晶片的洗涤步骤; 用于在将半导体晶片附着到载体上时将用于将洗涤的半导体晶片携带到组装过程的凸块接合，以在晶片的电极焊盘上形成凸块; 以及安装步骤，用于将形成有凸块的每个IC芯片安装到电路形成体上。

8. 发明授权

US06246388B1 Display driving circuit for displaying character on display panel 有权
标题翻译：显示面板显示字符显示驱动电路
公开(公告)号：US06246388B1
公开(公告)日：2001-06-12
申请号：US09309035
申请日：1999-05-10
申请人： Syuji Motegi , Hiroyuki Arai , Tetsuya Tokunaga
发明人： Syuji Motegi , Hiroyuki Arai , Tetsuya Tokunaga
IPC分类号： G09G336
CPC分类号： G09G5/222 , G09G3/04 , G09G3/20 , G09G2310/0278
摘要： For changing the content of a display RAM (38) or an accessory RAM (39), various data SDI, such as an instruction code, address data, display data, is initially transferred to a shift register (11). Then, the display data in the shift register (11) is latched by a latch circuit (62). A write operation is carried out during a period from the completion of a shift operation by the shift register (11) using various data SDI in connection with the current display to the completion of a shift operation using various data SDI in connection with the next display, i.e., a period with an operation enable signal CE remaining at an L or H level. As a result, time allowance for writing is ensured, which contributes to reduction of software processing load by an external device.
摘要翻译：为了更改显示RAM（38）或附件RAM（39）的内容，初始地将诸如指令代码，地址数据，显示数据的各种数据SDI传送到移位寄存器（11）。然后，移位寄存器（11）中的显示数据由锁存电路（62）锁存。在使用与当前显示相关联的各种数据SDI的移位寄存器（11）完成移位操作期间执行写入操作，使用与下一个显示相关联的各种数据SDI的移位操作完成，即具有操作使能信号CE保持在L或H电平的周期。结果，确保写入的时间容许，这有助于减少外部设备的软件处理负担。

9. 发明授权

US5938746A System for prioritizing slave input register to receive data transmission via bi-directional data line from master 失效
标题翻译：用于优先从属输入寄存器的系统，用于通过双向数据线从主机接收数据传输
公开(公告)号：US5938746A
公开(公告)日：1999-08-17
申请号：US805682
申请日：1997-02-25
申请人： Toshiyuki Ozawa , Shuji Motegi , Tetsuya Tokunaga
发明人： Toshiyuki Ozawa , Shuji Motegi , Tetsuya Tokunaga
IPC分类号： G06F13/38 , G06F13/42 , G06F13/18
CPC分类号： G06F13/423
摘要： A master (1) and a slave (3) are connected via a transmission line (5) for sending a clock CL; another transmission line (6) for bidirectionally sending data DT; and still another transmission line (7) for sending a control signal CE. Having turned a control signal CE into "L," the master (1) transmits an address code as data DT to the slave (3). Referring to the content of the transmitted address code, the slave (3) detects whether it is a data transmission from the master (1) to the slave (3) or vice versa. While a control signal CE remains "H," data transmission takes place. Data output from the slave (3) to the data line (6) is managed by a bus driver (22). The bus driver (22) is turned off during a period from when the clock CL became "H" to when a control signal CE becomes "L" after data transmission so that data transmission from the master (1) will not be adversely affected.
摘要翻译：主机（1）和从机（3）经由用于发送时钟CL的传输线（5）连接; 用于双向发送数据DT的另一传输线（6）; 以及用于发送控制信号CE的又一传输线（7）。将控制信号CE转换为“L”后，主机（1）将地址码作为数据DT发送到从机（3）。参照发送的地址码的内容，从机（3）检测是否是从主机（1）到从机（3）的数据传输，反之亦然。当控制信号CE保持“H”时，发生数据传输。从总线驱动器（22）管理从从机（3）到数据线（6）的数据输出。在从时钟CL变为“H”到数据传输之后的控制信号CE变为“L”的期间，总线驱动器（22）被关闭，从而不会对来自主机（1）的数据传输产生不利影响。

10. 发明授权

US4072531A Plugging compositions for blast furnace tap holes 失效
标题翻译：高炉龙头孔堵塞组合物
公开(公告)号：US4072531A
公开(公告)日：1978-02-07
申请号：US666290
申请日：1976-03-12
申请人： Kyohei Funabiki , Tetsuya Tokunaga
发明人： Kyohei Funabiki , Tetsuya Tokunaga
IPC分类号： C08G8/28 , C08K3/00 , C21B7/12 , C04B35/02 , C04B35/66 , C04B35/04
CPC分类号： C21B7/125 , C08G8/28 , C08K3/0033
摘要： Plugging compositions for blast furnace tap holes comprising a refractory filler, a wetting agent, and a binder therefor comprising a phenol-aldehyde condensate resin chemically modified by reaction with lignin have a muddy consistancy, and are characterized by enhanced compressive strength at elevated temperatures and increased plasticity at low temperatures as compared to conventional binders.
摘要翻译：包含耐火填料，润湿剂及其粘合剂的高炉煤气孔的堵塞组合物包括通过与木质素反应而化学改性的苯酚 - 醛缩合物树脂，具有浑浊的一致性，其特征在于在升高的温度下增强的抗压强度和增加的与常规粘合剂相比，低温下的可塑性。

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