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1. 发明授权

US07687844B2 Semiconductor constructions 失效
标题翻译：半导体结构
公开(公告)号：US07687844B2
公开(公告)日：2010-03-30
申请号：US12052124
申请日：2008-03-20
申请人： Cancheepuram V. Srividya , F. Daniel Gealy , Thomas M. Graettinger
发明人： Cancheepuram V. Srividya , F. Daniel Gealy , Thomas M. Graettinger
IPC分类号： H01L27/108
CPC分类号： H01L28/65 , H01L27/1085 , H01L27/10852 , H01L27/1087 , H01L28/84 , H01L29/66181
摘要： The invention includes a method of depositing a noble metal. A substrate is provided. The substrate has a first region and a second region. The first and second regions are exposed to a mixture comprising a precursor of a noble metal and an oxidant. During the exposure, a layer containing the noble metal is selectively deposited onto the first region relative to the second region. In particular applications, the first region can comprise borophosphosilicate glass, and the second region can comprise either aluminum oxide or doped non-oxidized silicon. The invention also includes capacitor constructions and methods of forming capacitor constructions.
摘要翻译：本发明包括沉积贵金属的方法。提供基板。衬底具有第一区域和第二区域。第一和第二区域暴露于包含贵金属和氧化剂的前体的混合物中。在曝光期间，包含贵金属的层相对于第二区域选择性地沉积在第一区域上。在具体应用中，第一区域可以包括硼磷硅酸盐玻璃，并且第二区域可以包括氧化铝或掺杂的非氧化硅。本发明还包括电容器结构和形成电容器结构的方法。

2. 发明申请

US20080045034A1 Methods for forming semiconductor constructions, and methods for selectively etching silicon nitride relative to conductive material 有权
标题翻译：用于形成半导体结构的方法以及相对于导电材料选择性地蚀刻氮化硅的方法
公开(公告)号：US20080045034A1
公开(公告)日：2008-02-21
申请号：US11506347
申请日：2006-08-17
申请人： Kevin R. Shea , Thomas M. Graettinger
发明人： Kevin R. Shea , Thomas M. Graettinger
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： H01L28/92 , H01L21/30625 , H01L21/31116 , H01L21/31144 , H01L21/32139 , H01L27/105 , H01L27/1052 , H01L27/108
摘要： The invention includes methods for selectively etching insulative material supports relative to conductive material. The invention can include methods for selectively etching silicon nitride relative to metal nitride. The metal nitride can be in the form of containers over a semiconductor substrate, with such containers having upwardly-extending openings with lateral widths of less than or equal to about 4000 angstroms; and the silicon nitride can be in the form of a layer extending between the containers. The selective etching can comprise exposure of at least some of the silicon nitride and the containers to Cl2 to remove the exposed silicon nitride, while not removing at least the majority of the metal nitride from the containers. In subsequent processing, the containers can be incorporated into capacitors.
摘要翻译：本发明包括相对于导电材料选择性地蚀刻绝缘材料支撑件的方法。本发明可以包括相对于金属氮化物选择性地蚀刻氮化硅的方法。金属氮化物可以是在半导体衬底上的容器的形式，其中这种容器具有向上延伸的开口，横向宽度小于或等于约4000埃; 并且氮化硅可以是在容器之间延伸的层的形式。选择性蚀刻可以包括将氮化硅和容器中的至少一些暴露于Cl 2以除去暴露的氮化硅，同时不从容器中去除至少大部分金属氮化物。在随后的处理中，容器可以并入电容器中。

3. 发明授权

US07226845B2 Semiconductor constructions, and methods of forming capacitor devices 有权
公开(公告)号：US07226845B2
公开(公告)日：2007-06-05
申请号：US11215243
申请日：2005-08-30
申请人： H. Montgomery Manning , Thomas M. Graettinger
发明人： H. Montgomery Manning , Thomas M. Graettinger
IPC分类号： H01L21/331
CPC分类号： H01L27/10894 , H01L27/10817 , H01L27/10852 , H01L28/91 , H01L29/945 , Y10S257/906
摘要： The invention includes semiconductor constructions, and also includes methods of forming pluralities of capacitor devices. An exemplary method of the invention includes forming conductive storage node material within openings in an insulative material to form conductive containers. A retaining structure lattice is formed in physical contact with at least some of the containers, and subsequently the insulative material is removed to expose outer surfaces of the containers. The retaining structure can alleviate toppling or other loss of structural integrity of the container structures. The electrically conductive containers correspond to first capacitor electrodes. After the outer sidewalls of the containers are exposed, dielectric material is formed within the containers and along the exposed outer sidewalls. Subsequently, a second capacitor electrode is formed over the dielectric material. The first and second capacitor electrodes, together with the dielectric material, form a plurality of capacitor devices.

4. 发明授权

US06881642B2 Method of forming a MIM capacitor with metal nitride electrode 失效
标题翻译：用金属氮化物电极形成MIM电容器的方法
公开(公告)号：US06881642B2
公开(公告)日：2005-04-19
申请号：US10419191
申请日：2003-04-21
申请人： Cem Basceri , Thomas M. Graettinger
发明人： Cem Basceri , Thomas M. Graettinger
IPC分类号： H01L21/02 , H01L21/285 , H01L21/316 , H01L21/20
CPC分类号： H01L28/84 , H01L21/02178 , H01L21/02181 , H01L21/02183 , H01L21/02194 , H01L21/0228 , H01L21/28568 , H01L21/3162 , H01L28/75 , H01L28/90
摘要： A method of forming an MIM capacitor with low leakage and high capacitance is disclosed. A layer of titanium nitride (TiN) or boron-doped titanium nitride (TiBN) material is formed as a lower electrode over an optional capacitance layer of hemispherical grained polysilicon (HSG). Prior to the dielectric formation, the first layer may be optionally subjected to a nitridization or oxidation process. A dielectric layer of, for example, aluminum oxide (Al2O3) formed by atomic layer deposition (ALD) is fabricated over the first layer and after the optional nitridization or oxidation process. An upper electrode of titanium nitride (TiN) or boron-doped titanium nitride (TiBN) is formed over the dielectric layer.
摘要翻译：公开了一种形成具有低泄漏和高电容的MIM电容器的方法。在半球状晶粒多晶硅（HSG）的可选电容层上形成氮化钛（TiN）或硼掺杂氮化钛（TiBN）材料层作为下电极。在电介质形成之前，第一层可以任选地进行氮化或氧化过程。通过原子层沉积（ALD）形成的例如氧化铝（Al 2 O 3 N）的电介质层在第一层上和在任选的氮化之后制造，或氧化过程。在电介质层上形成氮化钛（TiN）或硼掺杂氮化钛（TiBN）的上电极。

5. 发明授权

US06858894B2 Comprising agglomerates of one or more noble metals 失效
标题翻译：包含一种或多种贵金属的附聚物
公开(公告)号：US06858894B2
公开(公告)日：2005-02-22
申请号：US10773780
申请日：2004-02-09
申请人： Cancheepuram V. Srividya , F. Daniel Gealy , Thomas M. Graettinger
发明人： Cancheepuram V. Srividya , F. Daniel Gealy , Thomas M. Graettinger
IPC分类号： H01L21/02 , H01L21/334 , H01L21/4763 , H01L21/8242 , H01L27/108 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： H01L28/65 , H01L27/1085 , H01L27/10852 , H01L27/1087 , H01L28/84 , H01L29/66181
摘要： The invention includes a method of depositing a noble metal. A substrate is provided. The substrate has a first region and a second region. The first and second regions are exposed to a mixture comprising a precursor of a noble metal and an oxidant. During the exposure, a layer containing the noble metal is selectively deposited onto the first region relative to the second region. In particular applications, the first region can comprise borophosphosilicate glass, and the second region can comprise either aluminum oxide or doped non-oxidized silicon. The invention also includes capacitor constructions and methods of forming capacitor constructions.
摘要翻译：本发明包括沉积贵金属的方法。提供基板。衬底具有第一区域和第二区域。第一和第二区域暴露于包含贵金属和氧化剂的前体的混合物中。在曝光期间，包含贵金属的层相对于第二区域选择性地沉积在第一区域上。在具体应用中，第一区域可以包括硼磷硅酸盐玻璃，并且第二区域可以包括氧化铝或掺杂的非氧化硅。本发明还包括电容器结构和形成电容器结构的方法。

6. 发明授权

US06297124B1 Method of improving alignment signal strength by reducing refraction index at interface of materials in semiconductors 有权
$Method of improving alignment signal strength by reducing refraction index at interface of materials in semiconductors$
标题翻译：通过减少半导体材料界面处的折射率来提高取向信号强度的方法
公开(公告)号：US06297124B1
公开(公告)日：2001-10-02
申请号：US09395724
申请日：1999-09-14
申请人： Daryl C. New , Thomas M. Graettinger
发明人： Daryl C. New , Thomas M. Graettinger
IPC分类号： H01L2176
CPC分类号： G03F9/7076 , G03F9/7084 , H01L23/544 , H01L2223/54453 , H01L2924/0002 , H01L2924/00
摘要： A method and resulting structure for reducing refraction and reflection occurring at the interface between adjacent layers of different materials in a semiconductor device, assembly or laminate during an alignment step in a semiconductor device fabrication process. The method comprises forming a first layer of material, having a first index of refraction, over a substrate of the semiconductor device, assembly or laminate. A corrective layer is formed over the first layer and a second layer, having a second index of refraction, is then formed over the corrective layer. The corrective layer is composed of a material having an intermediate index of refraction between the first index of refraction and the second index of refraction. The method can also be modified to include one or more layers of materials and/or intermediate refraction layers interposed between or above any of the aforementioned adjacent layers. The aforementioned method and resulting structures can be further modified by forming an additional layer of material, having the requisite intermediate index of refraction, over an uppermost layer to further reduce reflection occurring at the interface between the uppermost layer and air. The invention is also directed to semiconductor devices, assemblies or laminates formed through the aforementioned methods and incorporating the aforementioned structures.
摘要翻译：一种用于在半导体器件制造工艺中的对准步骤期间在半导体器件，组件或层压体中的不同材料的相邻层之间的界面处发生折射和反射的方法和结果。该方法包括在半导体器件的衬底，组件或层压体上形成具有第一折射率的第一材料层。在第一层上形成校正层，然后在校正层上形成具有第二折射率的第二层。校正层由在第一折射率和第二折射率之间具有中间折射率的材料组成。该方法还可以被修改为包括插入在任何上述相邻层之间或之上的一层或多层材料和/或中间折射层。可以通过在最上层上形成具有必要的中间折射率的附加材料层来进一步改进上述方法和所得结构，以进一步减少在最上层与空气之间的界面处发生的反射。本发明还涉及通过上述方法形成并结合上述结构的半导体器件，组件或层压体。

7. 发明申请

US20130264628A1 USE OF ETCH PROCESS POST WORDLINE DEFINITION TO IMPROVE DATA RETENTION IN A FLASH MEMORY DEVICE 有权
标题翻译： ETCH过程的使用在字幕定义中改进闪存存储器件中的数据保持
公开(公告)号：US20130264628A1
公开(公告)日：2013-10-10
申请号：US13993444
申请日：2011-09-22
申请人： Randy J. Koval , Max F. Hineman , Ronald A. Weimer , Vinayak K. Shamanna , Thomas M. Graettinger , William R. Kueber , Christopher Larsen , Alex J. Schrinsky
发明人： Randy J. Koval , Max F. Hineman , Ronald A. Weimer , Vinayak K. Shamanna , Thomas M. Graettinger , William R. Kueber , Christopher Larsen , Alex J. Schrinsky
IPC分类号： H01L21/306 , H01L29/788
CPC分类号： H01L21/30604 , H01L21/76 , H01L27/11521 , H01L27/11568 , H01L29/513 , H01L29/788 , H01L29/7881 , H01L29/792
摘要： Embodiments of the present disclosure describe techniques and configurations relating to use of an etch process post wordline definition to improve data retention in a flash memory device. In one embodiment, a method includes forming a plurality of wordline structures on a substrate, wherein individual wordline structures of the plurality of wordline structures include a control gate having an electrically conductive material and a cap having an electrically insulative material formed on the control gate, depositing an electrically insulative material to form a liner on a surface of the individual wordline structures, and etching the liner to remove at least a portion of the liner. Other embodiments may be described and/or claimed.
摘要翻译：本公开的实施例描述与使用蚀刻处理后字幕定义相关的技术和配置以改善闪存设备中的数据保持。在一个实施例中，一种方法包括在衬底上形成多个字线结构，其中多个字线结构中的各个字线结构包括具有导电材料的控制栅极和在控制栅极上形成有电绝缘材料的盖，沉积电绝缘材料以在单个字线结构的表面上形成衬垫，以及蚀刻衬垫以去除衬垫的至少一部分。可以描述和/或要求保护其他实施例。

8. 发明授权

US07898850B2 Memory cells, electronic systems, methods of forming memory cells, and methods of programming memory cells 有权
标题翻译：存储单元，电子系统，形成存储单元的方法，以及编程存储单元的方法
公开(公告)号：US07898850B2
公开(公告)日：2011-03-01
申请号：US11871339
申请日：2007-10-12
申请人： Kyu S. Min , Rhett T. Brewer , Tejas Krishnamohan , Thomas M. Graettinger , D. V. Nirmal Ramaswamy , Ronald A. Weimer , Arup Bhattacharyya
发明人： Kyu S. Min , Rhett T. Brewer , Tejas Krishnamohan , Thomas M. Graettinger , D. V. Nirmal Ramaswamy , Ronald A. Weimer , Arup Bhattacharyya
IPC分类号： G11C11/34
CPC分类号： G11C16/0483 , B82Y10/00 , G11C11/5671 , G11C16/0475 , G11C2216/06 , H01L21/28273 , H01L21/28282 , H01L29/42332 , H01L29/42348 , Y10S977/943
摘要： Some embodiments include memory cells having vertically-stacked charge-trapping zones spaced from one another by dielectric material. The dielectric material may comprise high-k material. One or more of the charge-trapping zones may comprise metallic material. Such metallic material may be present as a plurality of discrete isolated islands, such as nanodots. Some embodiments include methods of forming memory cells in which two charge-trapping zones are formed over tunnel dielectric, with the zones being vertically displaced relative to one another, and with the zone closest to the tunnel dielectric having deeper traps than the other zone. Some embodiments include electronic systems comprising memory cells. Some embodiments include methods of programming memory cells having vertically-stacked charge-trapping zones.
摘要翻译：一些实施例包括具有通过介电材料彼此间隔开的垂直堆叠的电荷捕获区的存储单元。电介质材料可以包括高k材料。一个或多个电荷捕获区可以包括金属材料。这种金属材料可以作为多个离散的隔离岛存在，例如纳米点。一些实施例包括形成存储器单元的方法，其中在隧道电介质上形成两个电荷捕获区，其中区域相对于彼此垂直位移，并且最靠近隧道电介质的区域具有比另一区更深的陷阱。一些实施例包括包括存储器单元的电子系统。一些实施例包括编程具有垂直堆叠的电荷捕获区的存储器单元的方法。

9. 发明申请

US20100320566A1 Semiconductor constructions 有权
标题翻译：半导体结构
公开(公告)号：US20100320566A1
公开(公告)日：2010-12-23
申请号：US12853948
申请日：2010-08-10
申请人： H. Montgomery Manning , Thomas M. Graettinger
发明人： H. Montgomery Manning , Thomas M. Graettinger
IPC分类号： H01L29/92
CPC分类号： H01L27/10894 , H01L27/10817 , H01L27/10852 , H01L28/91 , H01L29/945 , Y10S257/906
摘要： The invention includes semiconductor constructions, and also includes methods of forming pluralities of capacitor devices. An exemplary method of the invention includes forming conductive storage node material within openings in an insulative material to form conductive containers. A retaining structure lattice is formed in physical contact with at least some of the containers, and subsequently the insulative material is removed to expose outer surfaces of the containers. The retaining structure can alleviate toppling or other loss of structural integrity of the container structures. The electrically conductive containers correspond to first capacitor electrodes. After the outer sidewalls of the containers are exposed, dielectric material is formed within the containers and along the exposed outer sidewalls. Subsequently, a second capacitor electrode is formed over the dielectric material. The first and second capacitor electrodes, together with the dielectric material, form a plurality of capacitor devices.
摘要翻译：本发明包括半导体结构，并且还包括形成多个电容器器件的方法。本发明的示例性方法包括在绝缘材料的开口内形成导电储存节点材料以形成导电容器。形成与至少一些容器物理接触的保持结构格子，随后去除绝缘材料以露出容器的外表面。保持结构可以减轻容器结构的结构完整性的倒塌或其它损失。导电容器对应于第一电容器电极。在容器的外侧壁暴露之后，电介质材料形成在容器内并沿外露的外侧壁。随后，在电介质材料上形成第二电容器电极。第一和第二电容器电极与电介质材料一起形成多个电容器器件。

10. 发明申请

US20090321809A1 GRADED OXY-NITRIDE TUNNEL BARRIER 审中-公开
标题翻译：分级氧化铁隧道障碍物
公开(公告)号：US20090321809A1
公开(公告)日：2009-12-31
申请号：US12165219
申请日：2008-06-30
申请人： Nirmal Ramaswamy , Tejas Krishnamohan , Kyu Min , Thomas M. Graettinger
发明人： Nirmal Ramaswamy , Tejas Krishnamohan , Kyu Min , Thomas M. Graettinger
IPC分类号： H01L29/788 , H01L21/469
CPC分类号： H01L21/02332 , H01L21/0214 , H01L21/02145 , H01L21/02148 , H01L21/02159 , H01L21/0217 , H01L21/02178 , H01L21/02189 , H01L21/02337 , H01L21/0234 , H01L21/3143 , H01L29/40114 , H01L29/40117 , H01L29/42324 , H01L29/4234 , H01L29/513
摘要： Briefly, a tunnel barrier for a non-volatile memory device comprising a graded oxy-nitride layer is disclosed.
摘要翻译：简而言之，公开了一种用于包括梯度氧化氮层的非易失性存储器件的隧道势垒。

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