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1. 发明授权

US08674471B2 Semiconductor device supplying charging current to element to be charged 有权
标题翻译：为要充电的元件提供充电电流的半导体器件
公开(公告)号：US08674471B2
公开(公告)日：2014-03-18
申请号：US13596209
申请日：2012-08-28
申请人： Tomohide Terashima
发明人： Tomohide Terashima
IPC分类号： H01L21/70 , H01L21/762
CPC分类号： H02J7/022 , H01L27/0629 , H01L27/0635 , H03K17/6871 , H03K17/6872 , H03K17/6874 , H03K19/017509 , Y02B40/90
摘要： A semiconductor device supplying a charging current to a charging-target element includes: a semiconductor layer of a first conductivity type; a first semiconductor region of a second conductivity type formed on a main surface of the semiconductor layer and having a first node coupled to a first electrode of the charging-target element and a second node coupled to a power supply potential node supplied with a power supply voltage; a second semiconductor region of the first conductivity type formed in a surface of the first semiconductor region at a distance from the semiconductor layer and having a third node coupled to the power supply potential node; and a charge carrier drift restriction portion restricting drift of charge carrier from the third node to the semiconductor layer.
摘要翻译：向充电目标元件提供充电电流的半导体器件包括：第一导电类型的半导体层; 第二导电类型的第一半导体区域形成在半导体层的主表面上并且具有耦合到充电目标元件的第一电极的第一节点和耦合到被提供有电源的电源电位节点的第二节点电压; 第一导电类型的第二半导体区域形成在距离半导体层一定距离的第一半导体区域的表面中，并且具有耦合到电源电位节点的第三节点; 以及电荷载流子漂移限制部分，其限制载流子从第三节点到半导体层的漂移。

2. 发明授权

US08093660B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08093660B2
公开(公告)日：2012-01-10
申请号：US12205973
申请日：2008-09-08
申请人： Tomohide Terashima
发明人： Tomohide Terashima
IPC分类号： H01L27/06
CPC分类号： H01L27/0722 , H01L27/0248 , H01L29/78 , H03K17/0406 , H03K17/567
摘要： A voltage mitigating element mitigating a voltage applied across a gate insulating film in an off state of an insulated gate bipolar transistor (IGBT) is arranged to a gate electrode node of a P-channel MOS transistor provided for suppressing flow-in of holes at the time of turn-off of the IGBT. Withstanding voltage characteristics are improved and an occupation area thereof is reduced while maintaining switching characteristics and a low on-resistance of an insulated gate bipolar transistor.
摘要翻译：在绝缘栅双极晶体管（IGBT）的截止状态下减轻施加在栅极绝缘膜上的电压的电压缓解元件被布置到P沟道MOS晶体管的栅电极节点，用于抑制在 IGBT关断时间。提高了耐电压特性，并且在保持绝缘栅双极晶体管的开关特性和低导通电阻的同时降低占用面积。

3. 发明授权

US07755168B2 Semiconductor device provided with floating electrode 有权
标题翻译：具有浮置电极的半导体器件
公开(公告)号：US07755168B2
公开(公告)日：2010-07-13
申请号：US11738039
申请日：2007-04-20
申请人： Tomohide Terashima , Shiori Uota
发明人： Tomohide Terashima , Shiori Uota
IPC分类号： H01L29/70
CPC分类号： H01L29/735 , H01L29/0692 , H01L29/0821
摘要： A semiconductor device has a first conductivity-type first semiconductor region, a second conductivity-type second semiconductor region and a second conductivity-type third semiconductor region both located on or above the first semiconductor region, a second conductivity-type fourth semiconductor region between the second semiconductor region and the third semiconductor region, and a first conductivity-type fifth semiconductor region between the third semiconductor region and the fourth semiconductor region. The fourth semiconductor region and the fifth semiconductor region are electrically connected by a conductive member. A distance between the fourth semiconductor region and the third semiconductor region is larger than a width of the fourth semiconductor region.
摘要翻译：半导体器件具有位于第一半导体区域上方或上方的第一导电型第一半导体区域，第二导电型第二半导体区域和第二导电型第三半导体区域，位于第一半导体区域之间的第二导电型第四半导体区域第二半导体区域和第三半导体区域，以及在第三半导体区域和第四半导体区域之间的第一导电类型的第五半导体区域。第四半导体区域和第五半导体区域通过导电构件电连接。第四半导体区域和第三半导体区域之间的距离大于第四半导体区域的宽度。

4. 发明申请

US20080179663A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20080179663A1
公开(公告)日：2008-07-31
申请号：US11747550
申请日：2007-05-11
申请人： Tomohide TERASHIMA
发明人： Tomohide TERASHIMA
IPC分类号： H01L29/76
CPC分类号： H01L29/0696 , H01L29/063 , H01L29/0839 , H01L29/7391 , H01L29/7393
摘要： The relationship between a distance Ls between a base layer and an n type buffer layer formed on the surface of a drift layer and the thickness t of a semiconductor substrate in contact with the drift layer is set to Ls≦t≦2×Ls. A loss upon turn-off of a high breakdown voltage semiconductor device can be reduced without deteriorating breakdown voltage characteristics.
摘要翻译：在漂移层的表面上形成的基底层和n型缓冲层之间的距离Ls与与漂移层接触的半导体衬底的厚度t之间的关系被设定为Ls <= t <= 2xLs。可以降低高击穿电压半导体器件的关断时的损耗，而不会降低击穿电压特性。

5. 发明授权

US6153915A CMOS semiconductor device 失效
标题翻译： CMOS半导体器件
公开(公告)号：US6153915A
公开(公告)日：2000-11-28
申请号：US70915
申请日：1998-05-04
申请人： Fumitoshi Yamamoto , Tomohide Terashima
发明人： Fumitoshi Yamamoto , Tomohide Terashima
IPC分类号： H01L21/8234 , H01L21/8238 , H01L21/8249 , H01L27/06 , H01L27/088 , H01L27/092 , H01L29/10 , H01L29/41 , H01L29/78 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113
CPC分类号： H01L29/1087 , H01L21/8249 , H01L27/0623 , H01L27/0921
摘要： In a semiconductor device and a method of manufacturing the same according to the invention, a p-type diffusion region for electrically connecting a back gate region and an electrode layer together is formed at a source region. Thereby, both of source region and p-type diffusion region are electrically connected to the electrode layer, so that the source region and the back gate region are maintained at the same potential. As a result, it is possible to provide the semiconductor device and the method of manufacturing the same which can suppress operation of a parasitic bipolar transistor formed in the semiconductor device even if a gate electrode has a large width.
摘要翻译：在根据本发明的半导体器件及其制造方法中，在源极区域形成用于将背栅极区域和电极层电连接的p型扩散区域。由此，源极区域和p型扩散区域都与电极层电连接，使得源极区域和背面栅极区域保持相同的电位。结果，即使栅电极具有大的宽度，也可以提供能够抑制形成在半导体器件中的寄生双极晶体管的工作的半导体器件及其制造方法。

6. 发明授权

US5894156A Semiconductor device having a high breakdown voltage isolation region 失效
标题翻译：具有高击穿电压隔离区域的半导体器件
公开(公告)号：US5894156A
公开(公告)日：1999-04-13
申请号：US739713
申请日：1996-10-29
申请人： Tomohide Terashima , Kazuhiro Shimizu
发明人： Tomohide Terashima , Kazuhiro Shimizu
IPC分类号： H01L29/78 , H01L27/06 , H01L27/08 , H01L29/06 , H01L29/08 , H01L27/092
CPC分类号： H01L29/7816 , H01L27/0629 , H01L29/063 , H01L29/0878 , Y10S257/90
摘要： A resurf structure is provided which includes an n type diffusion region surrounded by a n- diffusion region, in which a part of the joined combination of the n type diffusion region and the n- diffusion region is separated by a narrow p- substrate region in between. An aluminum lead is provided between the separated n- diffusion regions, and a signal is level shifted. A high voltage semiconductor device which includes a small area high voltage isolation region is obtained without process cost increase.
摘要翻译：提供了一种再现结构，其包括由n型扩散区域包围的n型扩散区域，其中n型扩散区域和n型扩散区域的接合组合的一部分被窄的p-衬底区域分开之间。在分离的n-扩散区域之间设置铝引线，并且信号被电平移位。获得包括小面积高电压隔离区域的高电压半导体器件，而不会增加工艺成本。

7. 发明授权

US5874767A Semiconductor device including a lateral power device 失效
标题翻译：包括侧向功率器件的半导体器件
公开(公告)号：US5874767A
公开(公告)日：1999-02-23
申请号：US954564
申请日：1997-10-20
申请人： Tomohide Terashima , Kazuhiro Shimizu
发明人： Tomohide Terashima , Kazuhiro Shimizu
IPC分类号： H01L21/673 , H01L27/06 , H01L27/088 , H01L27/092 , H01L29/06 , H01L29/10 , H01L29/739 , H01L29/78 , H01L23/58 , H01L29/00
CPC分类号： H01L29/7816 , H01L21/67326 , H01L21/67383 , H01L21/67386 , H01L27/0623 , H01L27/088 , H01L27/0922 , H01L29/7393 , H01L29/7801 , H01L29/0692 , H01L29/0878 , H01L29/1095 , H01L29/7835 , H01L2924/0002
摘要： A high breakdown voltage pch-MOSFET having a breakdown voltage of 150 V or more and a control element controlling the same are formed in a common n.sup.- epitaxial layer. Only an n-type region of n.sup.- epitaxial layer is distributed at a region located between the high breakdown voltage pch-MOSFET and the control element and extending along the substrate surface. A semiconductor device thus formed achieves a good throughput and reduces a required chip area.
摘要翻译：具有150V或更高的击穿电压的高击穿电压pch-MOSFET和控制其的控制元件形成在共同的n-外延层中。仅n型区域的n型外延层分布在位于高击穿电压pch-MOSFET与控制元件之间的区域上并且沿衬底表面延伸。这样形成的半导体器件实现了良好的吞吐量并且减少了所需的芯片面积。

8. 发明授权

US5731628A Semiconductor device having element with high breakdown voltage 失效
标题翻译：具有高击穿电压的元件的半导体器件
公开(公告)号：US5731628A
公开(公告)日：1998-03-24
申请号：US701291
申请日：1996-08-22
申请人： Tomohide Terashima
发明人： Tomohide Terashima
IPC分类号： H01L27/088 , H01L21/316 , H01L21/8234 , H01L21/8238 , H01L23/31 , H01L23/522 , H01L27/092 , H01L29/06 , H01L29/40 , H01L23/58
CPC分类号： H01L29/408 , H01L21/823871 , H01L23/3135 , H01L23/3171 , H01L23/5222 , H01L27/0922 , H01L2924/0002 , H01L2924/19041 , H01L2924/3025
摘要： A semiconductor device which contains an electrode or an interconnection subjected to a high voltage prevents current leakage due to polarization of a mold resin. In this semiconductor device, a glass coat film 13a covering a semiconductor element has an electrical conductivity in a range defined by the following formula (1) under the conditions of temperature between 17.degree. C. and 145.degree. C.: conductivity.gtoreq.1.times.10.sup.-10 /E . . . (1) (E: an electric field intensity �V/cm!, E.gtoreq.2.times.10.sup.4 �V/cm!) Owing to employment of the electrically conductive glass coat film, an electron current flowing through the conductive glass coat film suppresses an electric field caused by polarization of a mold resin.
摘要翻译：包含电极或经受高电压的互连的半导体器件防止由于模制树脂的极化引起的电流泄漏。在该半导体装置中，覆盖半导体元件的玻璃被膜13a在17℃〜145℃的温度条件下具有由下式（1）限定的范围内的导电率：导电率> 1 = -10 / E。。。（1）（E：电场强度[V / cm]，E> = 2×104 [V / cm]）由于使用导电性玻璃涂膜，流过导电性玻璃涂膜的电子电流抑制由模具树脂的极化引起的电场。

9. 发明授权

US5541430A VDMOS semiconductor device 失效
标题翻译： VDMOS半导体器件
公开(公告)号：US5541430A
公开(公告)日：1996-07-30
申请号：US54138
申请日：1993-04-30
申请人： Tomohide Terashima
发明人： Tomohide Terashima
IPC分类号： H01L21/331 , H01L21/332 , H01L21/336 , H01L29/06 , H01L29/423 , H01L29/739 , H01L29/745 , H01L29/749 , H01L29/78 , H01L29/76 , H01L29/74 , H01L29/94 , H01L31/062
CPC分类号： H01L29/4236 , H01L29/66348 , H01L29/66378 , H01L29/66787 , H01L29/7455 , H01L29/749 , H01L29/7802 , H01L29/7813 , H01L29/0696 , H01L29/4238
摘要： In a semiconductor device having a low ON resistance, an n.sup.- -type epitaxial layer (1) is formed on an upper surface of an n.sup.+ -type substrate (8) and p-type diffusion regions (2) are selectively formed on its upper surface, while n-type diffusion regions (3) are further formed on upper surfaces thereof. A gate electrode (5) wrapped up in an oxide film (4) is provided on the upper surface of the n.sup.- -type epitaxial layer (1) and above portions of the p-type diffusion regions (2) held between the n.sup.- -type epitaxial layer (1) and the n.sup.+ -type diffusion regions (3). Grooves (9) are formed in the upper surface of the n.sup.- -type epitaxial layer (1) located under a gate electrode (5) to extend perpendicularly to junction planes between the n.sup.- -type epitaxial layer (1) and the p-type diffusion regions (2). While an ON resistance includes an accumulation resistance (Ra) and a JFET resistance (Rj), these resistances can be reduced since a gate width is increased due to formation of the grooves (9) and a current readily flows downwardly along the grooves (9).
摘要翻译：在具有低导通电阻的半导体器件中，在n +型衬底（8）的上表面上形成n型外延层（1），并且在其上部选择性地形成p型扩散区域（2）而在其上表面上进一步形成n型扩散区（3）。在n型外延层（1）的上表面和保持在n型外延层（1）的上方的p型扩散区域（2）的上方设置包围氧化膜（4）的栅电极（5）型外延层（1）和n +型扩散区域（3）。在位于栅电极（5）下方的n型外延层（1）的上表面中形成沟槽（9），以垂直于n型外延层（1）和p-型外延层型扩散区域（2）。虽然导通电阻包括累积电阻（Ra）和JFET电阻（Rj），但是由于形成沟槽（9）而导致栅极宽度增加，并且电流容易沿着沟槽（9）向下流动）。

10. 发明授权

US5344789A Method of manufacturing vertical DMOS transistor with high off-breakdown-voltage and low on-resistance 失效
标题翻译：制造具有高截止击穿电压和低导通电阻的垂直DMOS晶体管的方法
公开(公告)号：US5344789A
公开(公告)日：1994-09-06
申请号：US155801
申请日：1993-11-23
申请人： Tomohide Terashima
发明人： Tomohide Terashima
IPC分类号： H01L21/18 , H01L21/336 , H01L29/06 , H01L29/423 , H01L29/78 , H01L21/44
CPC分类号： H01L29/66734 , H01L29/0657 , H01L29/66712 , H01L29/7813 , H01L21/187 , H01L29/0638 , H01L29/4236 , Y10S148/05 , Y10S438/977
摘要： A semiconductor device includes an N.sup.- type semiconductor layer (2). The N.sup.- type semiconductor layer (2) includes a triangular pole trench (10), an apex portion thereof contains a gate electrode (5). The trench (10) penetrates the semiconductor layer (2) and a P type well region (3) and projects into an N.sup.+ type source region (4). A source electrode (7) is disposed so as to be insulated from the semiconductor layer (2) by an oxide film (9) and in contact with the well region (3) and the source region (4). A drain electrode (8) is connected to the semiconductor layer (2) through an N.sup.+ type semiconductor substrate (1). With higher potential at the gate electrode (5) than at the source electrode (7), the well region (3) is partially inverted into N type near the trench (10). Thus, the semiconductor device is turned on due to a channel created associated to the conductivity type inversion. Most of current flow allowed in the semiconductor layer (2) by the channel flows near the trench (10).Hence, even when process patterns are refined, electrode-to-electrode insulation remains undegraded in the semiconductor device, attaining low on-resistance and nigh off-breakdown voltage.
摘要翻译：半导体器件包括N型半导体层（2）。 N型半导体层（2）包括三角形极沟（10），其顶部包含栅电极（5）。沟槽（10）穿透半导体层（2）和P型阱区（3）并投入到N +型源极区（4）中。源电极（7）被设置为与氧化膜（9）与半导体层（2）绝缘并与阱区（3）和源极区（4）接触。漏电极（8）通过N +型半导体衬底（1）与半导体层（2）连接。在栅电极（5）处的电位高于源电极（7）时，在沟槽（10）附近，阱区域（3）被部分地反转成N型。因此，由于与导电类型反转相关联的通道而导致半导体器件导通。通过沟槽在半导体层（2）中允许的大部分电流流过在沟槽（10）附近流动。因此，即使在精加工图形的情况下，半导体装置中的电极对电极的绝缘性仍未劣化，因此导通电阻和近击穿电压低。

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