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1. 发明授权

US06842827B2 Cache coherency arrangement to enhance inbound bandwidth 失效
标题翻译：缓存一致性排列，以增强入站带宽
公开(公告)号：US06842827B2
公开(公告)日：2005-01-11
申请号：US10038996
申请日：2002-01-02
申请人： Robert G. Blankenship , Matthew A. Lambert , Tony S. Rand
发明人： Robert G. Blankenship , Matthew A. Lambert , Tony S. Rand
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0835
摘要： A cache coherency arrangement with support for pre-fetch ownership, to enhance inbound bandwidth for single leaf and multiple leaf, input-output interfaces, with shared memory space is disclosed. Embodiments comprise ownership stealing to enhance inbound bandwidth and to prevent or attenuate starvation of transactions or of an input-output interface for transactions.
摘要翻译：公开了一种支持预取所有权的高速缓存一致性布置，以增强具有共享存储空间的单页和多页输入输出接口的入站带宽。实施例包括所有权盗取以增强入站带宽并且防止或衰减交易的饥饿或交易的输入 - 输出接口。

2. 发明授权

US08046539B2 Method and apparatus for the synchronization of distributed caches 有权
标题翻译：分布式缓存同步的方法和装置
公开(公告)号：US08046539B2
公开(公告)日：2011-10-25
申请号：US12479541
申请日：2009-06-05
申请人： Robert T. George , Mathew A. Lambert , Tony S. Rand , Robert G. Blankenship , Kenneth C. Creta
发明人： Robert T. George , Mathew A. Lambert , Tony S. Rand , Robert G. Blankenship , Kenneth C. Creta
IPC分类号： G06F12/08
CPC分类号： G06F12/0835 , G06F12/082
摘要： A method and apparatus for the synchronization of distributed caches. More particularly, the present invention to cache memory systems and more particularly to a hierarchical caching protocol suitable for use with distributed caches, including use within a caching input/output (I/O) hub.
摘要翻译：一种用于同步分布式缓存的方法和装置。更具体地，本发明涉及缓存存储器系统，更具体地涉及适用于分布式高速缓存的分层缓存协议，包括在高速缓存输入/输出（I / O）集线器内的使用。

3. 发明申请

US20090240894A1 METHOD AND APARATUS FOR THE SYNCHRONIZATION OF DISTRIBUTED CACHES 有权
标题翻译：分布式快照同步的方法与方法
公开(公告)号：US20090240894A1
公开(公告)日：2009-09-24
申请号：US12479541
申请日：2009-06-05
申请人： Robert T. George , Mathew A. Lambert , Tony S. Rand , Robert G. Blankenship , Kenneth C. Creta
发明人： Robert T. George , Mathew A. Lambert , Tony S. Rand , Robert G. Blankenship , Kenneth C. Creta
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0835 , G06F12/082
摘要： A method and apparatus for the synchronization of distributed caches. More particularly, the present invention to cache memory systems and more particularly to a hierarchical caching protocol suitable for use with distributed caches, including use within a caching input/output (I/O) hub.
摘要翻译：一种用于同步分布式缓存的方法和装置。更具体地，本发明涉及缓存存储器系统，更具体地涉及适用于分布式高速缓存的分层缓存协议，包括在高速缓存输入/输出（I / O）集线器内的使用。

4. 发明授权

US07546422B2 Method and apparatus for the synchronization of distributed caches 有权
标题翻译：分布式缓存同步的方法和装置
公开(公告)号：US07546422B2
公开(公告)日：2009-06-09
申请号：US10231414
申请日：2002-08-28
申请人： Robert T George , Mathew A Lambert , Tony S Rand , Robert G Blankenship , Kenneth C Creta
发明人： Robert T George , Mathew A Lambert , Tony S Rand , Robert G Blankenship , Kenneth C Creta
IPC分类号： G06F12/08
CPC分类号： G06F12/0835 , G06F12/082
摘要： A method and apparatus for the synchronization of distributed caches. More particularly, the present invention to cache memory systems and more particularly to a hierarchical caching protocol suitable for use with distributed caches, including use within a caching input/output (I/O) hub.
摘要翻译：一种用于同步分布式缓存的方法和装置。更具体地，本发明涉及缓存存储器系统，更具体地涉及适用于分布式高速缓存的分层缓存协议，包括在高速缓存输入/输出（I / O）集线器内的使用。

5. 发明授权

US07162546B2 Reordering unrelated transactions from an ordered interface 有权
标题翻译：从有序接口重新排序不相关的事务
公开(公告)号：US07162546B2
公开(公告)日：2007-01-09
申请号：US10034641
申请日：2001-12-27
申请人： Kenneth C. Creta , Robert T. George , Bradford B. Congdon , Tony S. Rand
发明人： Kenneth C. Creta , Robert T. George , Bradford B. Congdon , Tony S. Rand
IPC分类号： G06F3/00
CPC分类号： G06F13/4022 , G06F13/4059
摘要： A computer chipset having an identifier module and a router. The identifier module is configured to add sequence identifiers to each transaction in independent ordered sequences of transactions. The sequence identifiers identify which ordered sequence the transactions belong to. The identifier module combines the ordered sequences of transactions into a combined ordered sequence of transactions. The combined ordered sequence of transactions are sent over an ordered interface. A router then separates the combined ordered sequence of transactions into ordered queues based on the sequence identifiers associated with the transactions. The transactions in the ordered queues are executed in an order that reduces the time required to complete the transactions.
摘要翻译：具有标识符模块和路由器的计算机芯片组。标识符模块被配置为以独立有序的事务序列向每个事务添加序列标识符。序列标识符标识事务所属的有序序列。标识符模块将有序的事务序列组合成一个组合顺序的事务顺序。交易的组合有序序列通过有序接口发送。然后，路由器基于与事务相关联的序列标识符将事务的组合有序序列分离成有序队列。有序队列中的事务按照可以减少完成事务所需时间的顺序执行。

6. 发明授权

US06801976B2 Mechanism for preserving producer-consumer ordering across an unordered interface 失效
标题翻译：通过无序接口保留生产者 - 消费者排序的机制
公开(公告)号：US06801976B2
公开(公告)日：2004-10-05
申请号：US09940292
申请日：2001-08-27
申请人： Kenneth C. Creta , Bradford B. Congdon , Tony S Rand , Deepak Ramachandran
发明人： Kenneth C. Creta , Bradford B. Congdon , Tony S Rand , Deepak Ramachandran
IPC分类号： G06F1300
CPC分类号： G06F13/4013
摘要： An input/output hub includes an inbound ordering queue (IOQ) to receive inbound transactions. All read and write transactions have a transaction completion. Peer-to-peer transactions are not permitted to reach a destination until after all prior writes in the IOQ have been completed. A write in a peer-to-peer transaction does not permit subsequent accesses to proceed until the write is guaranteed to be in an ordered domain of the destination. An IOQ read bypass buffer is provided to receive read transactions pushed from the IOQ to permit posted writes and read/write completions to progress through the IOQ. An outbound ordering queue (OOQ) stores outbound transactions and completions of the inbound transactions. The OOQ also issues write completions for posted writes. An OOQ read bypass buffer is provided to receive read transactions pushed from the OOQ to permit posted writes and read/write completions to progress through the OOQ. An unordered domain within the input/output hub receives the inbound transactions transmitted from the IOQ and receives the outbound transactions transmitted from an unordered protocol.
摘要翻译：输入/输出集线器包括接收入站事务的入站订单队列（IOQ）。所有读写事务都有一个事务完成。在IOQ的所有事先写入完成之后，对等交易都不允许到达目的地。在对等交易中的写入不允许后续访问继续进行，直到写保证在目的地的有序域中。提供IOQ读取旁路缓冲区以接收从IOQ推送的读取事务，以允许发布的写入和读取/写入完成以通过IOQ进行。出站订单队列（OOQ）存储入站事务的出站事务和完成。 OOQ还发布写入完成。提供OOQ读取旁路缓冲区以接收从OOQ推送的读取事务，以允许发布的写入和读取/写入完成以通过OOQ进行。输入/输出集线器内的无序域接收从IOQ发送的入站事务，并接收从无序协议发送的出站事务。

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