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1. 发明申请

US20100244879A1 APPARATUS FOR MASS DIE TESTING 有权
标题翻译：大型测试仪器
公开(公告)号：US20100244879A1
公开(公告)日：2010-09-30
申请号：US12772928
申请日：2010-05-03
申请人： Tsung-Yang Hung
发明人： Tsung-Yang Hung
IPC分类号： G01R31/02
CPC分类号： G01R31/318511 , G01R31/2822 , G01R31/2884 , G01R31/3187 , H03H7/38
摘要： A test system for testing a large number of dice on a semiconductor wafer without repositioning test probes is disclosed. The test system includes a set of dice under test (DUT) connected together by a plurality of signal buses formed on a semiconductor wafer, at least one test die designed for carrying out tests of the dice under test, the test die having a set of pads to be connected to one or more probes of an external test apparatus, and a probe card with at least one multiplexer implemented in the probe card, such that the test die is capable of receiving signals from the external test apparatus to select any die under test within the set via the multiplexer and the signal buses without repositioning the probes.
摘要翻译：公开了一种用于在半导体晶片上测试大量骰子而不重新定位测试探针的测试系统。测试系统包括通过形成在半导体晶片上的多条信号总线连接在一起的测试用芯片（DUT），至少一个被设计用于进行被测试芯片测试的测试模具，该测试模具具有一组连接到外部测试装置的一个或多个探针的焊盘和在探针卡中实现的具有至少一个多路复用器的探针卡，使得测试管芯能够接收来自外部测试装置的信号，以选择任何模具通过复用器和信号总线在组内进行测试，而无需重新定位探头。

2. 发明申请

US20100067154A1 Enhancing Bandwidth of ESD Network Using Transformers 有权
标题翻译：使用变压器增强ESD网络的带宽
公开(公告)号：US20100067154A1
公开(公告)日：2010-03-18
申请号：US12211576
申请日：2008-09-16
申请人： Kuo-Liang Deng , Tsung-Yang Hung
发明人： Kuo-Liang Deng , Tsung-Yang Hung
IPC分类号： H02H9/00
CPC分类号： H01L27/0248 , H01F2017/0046 , H01L23/60 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： An integrated circuit device includes a first pad and a second pad; electrostatic discharging (ESD) devices coupling the first pad and the second pad to a discharging path; a transformer including a first end, a second end, a third end and a fourth end, wherein the first end and the second end are coupled to the first pad and the second pad, respectively; and a transceiver circuit coupled to the first end and the second end of the transformer.
摘要翻译：集成电路器件包括第一焊盘和第二焊盘; 将第一焊盘和第二焊盘耦合到放电路径的静电放电（ESD）装置; 包括第一端，第二端，第三端和第四端的变压器，其中所述第一端和所述第二端分别耦合到所述第一焊盘和所述第二焊盘; 以及耦合到变压器的第一端和第二端的收发器电路。

3. 发明授权

US6054952A Broad-band microstrip antenna 有权
标题翻译：宽带微带天线
公开(公告)号：US6054952A
公开(公告)日：2000-04-25
申请号：US191932
申请日：1998-11-13
申请人： Min-Hung Shen , Sheng-Ming Deng , Tsung-Yang Hung
发明人： Min-Hung Shen , Sheng-Ming Deng , Tsung-Yang Hung
IPC分类号： H01Q1/38 , H01Q1/52 , H01Q5/00 , H01Q5/371 , H01Q9/04
CPC分类号： H01Q9/0407 , H01Q1/38 , H01Q1/526 , H01Q5/371
摘要： A broad-band microstrip antenna implemented using a dielectric base as its main body is disclosed. The base has two sides where the dual-mode resonator is located on the first side, while the grounded plane is located on the second side of the dielectric base. The dual-mode resonator has a high-frequency resonator and a low-frequency resonator, which are partially positioned in parallel. Due to the electric-magnetic effects, these two resonators are mutually coupled to significantly increase the operating bandwidth. In addition, there is a feed line on the first side of the dielectric base, which connects to the dual-mode resonator to provide signal transmission. In addition, there is a grounded mask in the antenna, which is located on the first side of the dielectric base, to provide sheltering for the feed line, and connect to the grounded plane to form a closed area to provide a more complete radiation field pattern.
摘要翻译：公开了使用电介质基底作为其主体实现的宽带微带天线。基座具有两侧，双模共振器位于第一侧，而接地平面位于电介质基座的第二侧。双模谐振器具有高频谐振器和低频谐振器，它们被部分地并联放置。由于电磁效应，这两个谐振器相互耦合以显着增加工作带宽。此外，在电介质基底的第一侧上有馈电线，该馈电线连接到双模谐振器以提供信号传输。另外，在天线中有一个接地的掩模，它位于电介质基底的第一面上，为馈电线提供防护，并连接到接地平面，形成一个闭合的区域，以提供更完整的辐射场模式。

4. 发明申请

US20110037494A1 Method for Wafer-Level Testing of Integrated Circuits 有权
标题翻译：集成电路晶圆级测试方法
公开(公告)号：US20110037494A1
公开(公告)日：2011-02-17
申请号：US12539328
申请日：2009-08-11
申请人： Tsung-Yang Hung , Aaron Wang
发明人： Tsung-Yang Hung , Aaron Wang
IPC分类号： G01R31/26
CPC分类号： G01R31/3004 , G01R31/2831
摘要： A method for wafer level testing is provided which includes providing a wafer having an integrated circuit formed thereon, applying a signal to energize the integrated circuit, the signal including increasing steps or decreasing steps that range between a first level and a second level, and determining whether the integrated circuit complies with a test criteria after applying the signal.
摘要翻译：提供了一种用于晶片级测试的方法，其包括提供其上形成有集成电路的晶片，施加信号以激励集成电路，所述信号包括在第一电平和第二电平之间范围内的增加步骤或降低步骤，以及确定应用信号后，集成电路是否符合测试标准。

5. 发明申请

US20090295439A1 Phase Lock Loop (PLL) with Gain Control 有权
标题翻译：锁相环（PLL），具有增益控制
公开(公告)号：US20090295439A1
公开(公告)日：2009-12-03
申请号：US12127651
申请日：2008-05-27
申请人： Tsung-Hsien Tsai , Tsung-Yang Hung , Chien-Hung Chen , Min-Shueh Yuan
发明人： Tsung-Hsien Tsai , Tsung-Yang Hung , Chien-Hung Chen , Min-Shueh Yuan
IPC分类号： H03L7/093
CPC分类号： H03L7/093 , H03L7/0995 , H03L7/10 , H03L2207/06
摘要： A Phase Lock Loop (PLL) with gain control is provided. The PLL has a dual-path configuration, where a first and a second VCO control voltage are generated in response to a phase or frequency difference between a PLL input signal and an output signal. The PLL comprises a dynamic voltage gain control (DVGC) unit and a voltage-to-current (V2I) unit, where the DVGC creates a baseline reference current in response to the first VCO control voltage and the V2I provides a substantially linear current in response to the second VCO control voltage. The currents from the DVGC and V2I are combined and fed into a current-controlled oscillator, which generates a PLL output frequency signal. Frequency gain of the VCO is substantially reduced, thus providing a PLL with improved tuning precision.
摘要翻译：提供了具有增益控制的锁相环（PLL）。 PLL具有双路配置，其中响应于PLL输入信号和输出信号之间的相位或频率差产生第一和第二VCO控制电压。 PLL包括动态电压增益控制（DVGC）单元和电压 - 电流（V2I）单元，其中DVGC响应于第一VCO控制电压创建基准参考电流，并且V2I提供基本上线性的电流响应到第二个VCO控制电压。来自DVGC和V2I的电流被组合并馈送到电流控制的振荡器中，其产生PLL输出频率信号。 VCO的频率增益显着降低，从而提供具有改进的调谐精度的PLL。

6. 发明申请

US20060172719A1 Method and apparatus for inter-chip wireless communication 有权
标题翻译：芯片间无线通信的方法和装置
公开(公告)号：US20060172719A1
公开(公告)日：2006-08-03
申请号：US11045050
申请日：2005-01-31
申请人： Ker-Min Chen , Tsung-Yang Hung
发明人： Ker-Min Chen , Tsung-Yang Hung
IPC分类号： H04B1/28
CPC分类号： H04B1/38
摘要： In one embodiment, the disclosure relates to a method and apparatus for inter-chip wireless communication system. The system includes a first microprocessor having a plurality of non-contact ports and a first RF communication circuit integrated with the first microprocessor; a second microprocessor also having a plurality of non-contact ports and a second RF communication circuit integrated therein. An RF communication protocol can be configured to receive data from each of the non-contact ports in parallel, multiplex and translate the data to a serial RF signal. Data communication can be accomplished using the wireless communication circuit on each chip. The RF communication between the first and the second integrated circuits using the communication protocol defines a non capacitive-coupling of the first and the second die.
摘要翻译：在一个实施例中，本发明涉及一种用于芯片间无线通信系统的方法和装置。该系统包括具有多个非接触端口的第一微处理器和与第一微处理器集成的第一RF通信电路; 第二微处理器还具有集成在其中的多个非接触端口和第二RF通信电路。 RF通信协议可以被配置为并行地从每个非接触端口接收数据，将数据复用并转换为串行RF信号。可以使用每个芯片上的无线通信电路来实现数据通信。使用通信协议的第一和第二集成电路之间的RF通信定义了第一和第二管芯的非电容耦合。

7. 发明授权

US08237462B2 Method for wafer-level testing of integrated circuits 有权
标题翻译：集成电路晶圆级测试方法
公开(公告)号：US08237462B2
公开(公告)日：2012-08-07
申请号：US12539328
申请日：2009-08-11
申请人： Tsung-Yang Hung , Aaron Wang
发明人： Tsung-Yang Hung , Aaron Wang
IPC分类号： G01R31/02 , G01R31/26
CPC分类号： G01R31/3004 , G01R31/2831
摘要： A method for wafer level testing is provided which includes providing a wafer having an integrated circuit formed thereon, applying a signal to energize the integrated circuit, the signal including increasing steps or decreasing steps that range between a first level and a second level, and determining whether the integrated circuit complies with a test criteria after applying the signal.
摘要翻译：提供了一种用于晶片级测试的方法，其包括提供其上形成有集成电路的晶片，施加信号以激励集成电路，所述信号包括在第一电平和第二电平之间范围内的增加步骤或降低步骤，以及确定应用信号后，集成电路是否符合测试标准。

8. 发明授权

US08125235B2 Apparatus for mass die testing 有权
标题翻译：大容量模具测试装置
公开(公告)号：US08125235B2
公开(公告)日：2012-02-28
申请号：US12772928
申请日：2010-05-03
申请人： Tsung-Yang Hung
发明人： Tsung-Yang Hung
IPC分类号： G01R31/20
CPC分类号： G01R31/318511 , G01R31/2822 , G01R31/2884 , G01R31/3187 , H03H7/38
摘要： A test system for testing a large number of dice on a semiconductor wafer without repositioning test probes is disclosed. The test system includes a set of dice under test (DUT) connected together by a plurality of signal buses formed on a semiconductor wafer, at least one test die designed for carrying out tests of the dice under test, the test die having a set of pads to be connected to one or more probes of an external test apparatus, and a probe card with at least one multiplexer implemented in the probe card, such that the test die is capable of receiving signals from the external test apparatus to select any die under test within the set via the multiplexer and the signal buses without repositioning the probes.
摘要翻译：公开了一种用于在半导体晶片上测试大量骰子而不重新定位测试探针的测试系统。测试系统包括通过形成在半导体晶片上的多条信号总线连接在一起的测试用芯片（DUT），至少一个被设计用于进行被测试芯片测试的测试模具，该测试模具具有一组连接到外部测试装置的一个或多个探针的焊盘和在探针卡中实现的具有至少一个多路复用器的探针卡，使得测试管芯能够接收来自外部测试装置的信号以选择任何模具通过复用器和信号总线在组内进行测试，而无需重新定位探头。

9. 发明申请

US20080116910A1 Apparatus for mass die testing 审中-公开
标题翻译：大容量模具测试装置
公开(公告)号：US20080116910A1
公开(公告)日：2008-05-22
申请号：US11600973
申请日：2006-11-17
申请人： Tsung-Yang Hung
发明人： Tsung-Yang Hung
IPC分类号： G01R31/26
CPC分类号： G01R31/318511 , G01R31/2822 , G01R31/2884 , G01R31/3187 , H03H7/38
摘要： A semiconductor wafer includes a set of dice under test connected together by a plurality of signal buses; and at least one test die designed for carrying out tests of the dice under test, having a set of pads to be connected to one or more probes of an external test apparatus, and at least one multiplexer connected with the set of dice under test via the signal buses, such that the test die is capable of receiving signals from the external test apparatus to select any die under test within the set via the multiplexer and the signal buses without repositioning the probes.
摘要翻译：半导体晶片包括通过多个信号总线连接在一起的被测试的一组骰子; 以及至少一个测试模具，被设计用于进行被测试模具的测试，具有要连接到外部测试装置的一个或多个探头的一组焊盘，以及至少一个多路复用器，与被测试的所述一组模具连接，信号总线，使得测试管芯能够从外部测试装置接收信号，以经由多路复用器和信号总线在组内选择任何待测试的管芯，而不重新定位探针。

10. 发明授权

US07894173B2 Enhancing bandwidth of ESD network using transformers 有权
标题翻译：使用变压器增强ESD网络的带宽
公开(公告)号：US07894173B2
公开(公告)日：2011-02-22
申请号：US12211576
申请日：2008-09-16
申请人： Kuo-Liang Deng , Tsung-Yang Hung
发明人： Kuo-Liang Deng , Tsung-Yang Hung
IPC分类号： H02H3/22
CPC分类号： H01L27/0248 , H01F2017/0046 , H01L23/60 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： An integrated circuit device includes a first pad and a second pad; electrostatic discharging (ESD) devices coupling the first pad and the second pad to a discharging path; a transformer including a first end, a second end, a third end and a fourth end, wherein the first end and the second end are coupled to the first pad and the second pad, respectively; and a transceiver circuit coupled to the first end and the second end of the transformer.
摘要翻译：集成电路器件包括第一焊盘和第二焊盘; 将第一焊盘和第二焊盘耦合到放电路径的静电放电（ESD）装置; 包括第一端，第二端，第三端和第四端的变压器，其中所述第一端和所述第二端分别耦合到所述第一焊盘和所述第二焊盘; 以及耦合到变压器的第一端和第二端的收发器电路。

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