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1. 发明授权

US07786771B2 Phase lock loop (PLL) with gain control 有权
标题翻译：具有增益控制的锁相环（PLL）
公开(公告)号：US07786771B2
公开(公告)日：2010-08-31
申请号：US12127651
申请日：2008-05-27
申请人： Tsung-Hsien Tsai , Tsung-Yang Hung , Chien-Hung Chen , Min-Shueh Yuan
发明人： Tsung-Hsien Tsai , Tsung-Yang Hung , Chien-Hung Chen , Min-Shueh Yuan
IPC分类号： H03L7/06
CPC分类号： H03L7/093 , H03L7/0995 , H03L7/10 , H03L2207/06
摘要： A Phase Lock Loop (PLL) with gain control is provided. The PLL has a dual-path configuration, where a first and a second VCO control voltage are generated in response to a phase or frequency difference between a PLL input signal and an output signal. The PLL comprises a dynamic voltage gain control (DVGC) unit and a voltage-to-current (V2I) unit, where the DVGC creates a baseline reference current in response to the first VCO control voltage and the V2I provides a substantially linear current in response to the second VCO control voltage. The currents from the DVGC and V2I are combined and fed into a current-controlled oscillator, which generates a PLL output frequency signal. Frequency gain of the VCO is substantially reduced, thus providing a PLL with improved tuning precision.
摘要翻译：提供了具有增益控制的锁相环（PLL）。 PLL具有双路配置，其中响应于PLL输入信号和输出信号之间的相位或频率差产生第一和第二VCO控制电压。 PLL包括动态电压增益控制（DVGC）单元和电压 - 电流（V2I）单元，其中DVGC响应于第一VCO控制电压创建基准参考电流，并且V2I提供基本上线性的电流响应到第二个VCO控制电压。来自DVGC和V2I的电流被组合并馈送到电流控制的振荡器中，其产生PLL输出频率信号。 VCO的频率增益显着降低，从而提供具有改进的调谐精度的PLL。

2. 发明申请

US20090295439A1 Phase Lock Loop (PLL) with Gain Control 有权
标题翻译：锁相环（PLL），具有增益控制
公开(公告)号：US20090295439A1
公开(公告)日：2009-12-03
申请号：US12127651
申请日：2008-05-27
申请人： Tsung-Hsien Tsai , Tsung-Yang Hung , Chien-Hung Chen , Min-Shueh Yuan
发明人： Tsung-Hsien Tsai , Tsung-Yang Hung , Chien-Hung Chen , Min-Shueh Yuan
IPC分类号： H03L7/093
CPC分类号： H03L7/093 , H03L7/0995 , H03L7/10 , H03L2207/06
摘要： A Phase Lock Loop (PLL) with gain control is provided. The PLL has a dual-path configuration, where a first and a second VCO control voltage are generated in response to a phase or frequency difference between a PLL input signal and an output signal. The PLL comprises a dynamic voltage gain control (DVGC) unit and a voltage-to-current (V2I) unit, where the DVGC creates a baseline reference current in response to the first VCO control voltage and the V2I provides a substantially linear current in response to the second VCO control voltage. The currents from the DVGC and V2I are combined and fed into a current-controlled oscillator, which generates a PLL output frequency signal. Frequency gain of the VCO is substantially reduced, thus providing a PLL with improved tuning precision.
摘要翻译：提供了具有增益控制的锁相环（PLL）。 PLL具有双路配置，其中响应于PLL输入信号和输出信号之间的相位或频率差产生第一和第二VCO控制电压。 PLL包括动态电压增益控制（DVGC）单元和电压 - 电流（V2I）单元，其中DVGC响应于第一VCO控制电压创建基准参考电流，并且V2I提供基本上线性的电流响应到第二个VCO控制电压。来自DVGC和V2I的电流被组合并馈送到电流控制的振荡器中，其产生PLL输出频率信号。 VCO的频率增益显着降低，从而提供具有改进的调谐精度的PLL。

3. 发明申请

US20110080220A1 TEMPERATURE COMPENSATED INTEGRATOR 有权
标题翻译：温度补偿积分器
公开(公告)号：US20110080220A1
公开(公告)日：2011-04-07
申请号：US12575222
申请日：2009-10-07
申请人： Tsung-Hsien Tsai , Min-Shueh Yuan , Chien-Hung Chen
发明人： Tsung-Hsien Tsai , Min-Shueh Yuan , Chien-Hung Chen
IPC分类号： H03F1/30
CPC分类号： H03F3/45475 , G06G7/18 , H03F2200/264 , H03F2200/447 , H03F2203/45512 , H03F2203/45524
摘要： A representative integrator includes an amplifier having an input and an output; a feedback loop coupled between the input and the output of the amplifier, the feedback loop comprising a compensated resistor circuit having a resistance value selected for reducing a loss factor of the integrator; and a control circuit coupled to an input of the compensated resistor circuit, the control circuit producing a control signal for controlling the compensated resistor circuit to substantially maintain the resistance value selected for reducing the loss factor of the integrator across a range of integrator temperatures.
摘要翻译：代表积分器包括具有输入和输出的放大器; 耦合在所述放大器的输入和输出之间的反馈回路，所述反馈回路包括具有选择用于减小所述积分器的损耗因子的电阻值的补偿电阻器电路; 以及耦合到所述经补偿的电阻器电路的输入端的控制电路，所述控制电路产生用于控制所述经补偿的电阻器电路的控制信号，以基本上维持所选择的用于降低积分器温度范围内的积分器的损耗因子的电阻值。

4. 发明授权

US08013657B2 Temperature compensated integrator 有权
标题翻译：温度补偿积分器
公开(公告)号：US08013657B2
公开(公告)日：2011-09-06
申请号：US12575222
申请日：2009-10-07
申请人： Tsung-Hsien Tsai , Min-Shueh Yuan , Chien-Hung Chen
发明人： Tsung-Hsien Tsai , Min-Shueh Yuan , Chien-Hung Chen
IPC分类号： H03K5/00
CPC分类号： H03F3/45475 , G06G7/18 , H03F2200/264 , H03F2200/447 , H03F2203/45512 , H03F2203/45524
摘要： A representative integrator includes an amplifier having an input and an output; a feedback loop coupled between the input and the output of the amplifier, the feedback loop comprising a compensated resistor circuit having a resistance value selected for reducing a loss factor of the integrator; and a control circuit coupled to an input of the compensated resistor circuit, the control circuit producing a control signal for controlling the compensated resistor circuit to substantially maintain the resistance value selected for reducing the loss factor of the integrator across a range of integrator temperatures.
摘要翻译：代表积分器包括具有输入和输出的放大器; 耦合在所述放大器的输入和输出之间的反馈回路，所述反馈回路包括具有选择用于减小所述积分器的损耗因子的电阻值的补偿电阻器电路; 以及耦合到所述经补偿的电阻器电路的输入端的控制电路，所述控制电路产生用于控制所述经补偿的电阻器电路的控制信号，以基本上维持所选择的用于降低积分器温度范围内的积分器的损耗因子的电阻值。

5. 发明授权

US07791420B2 Phase-locked loop with start-up circuit 有权
标题翻译：带启动电路的锁相环
公开(公告)号：US07791420B2
公开(公告)日：2010-09-07
申请号：US12330952
申请日：2008-12-09
申请人： Chien-Hung Chen , Mao-Hsuan Chou , Tsung-Hsien Tsai , Min-Shueh Yuan
发明人： Chien-Hung Chen , Mao-Hsuan Chou , Tsung-Hsien Tsai , Min-Shueh Yuan
IPC分类号： H03K3/03 , H03L7/099
CPC分类号： H03L7/10 , H03L7/0995
摘要： A circuit includes a voltage-controlled oscillator (VCO), which includes a voltage input node having an input voltage; and a start-up circuit. The start-up circuit includes a first current path and a second current path. The first current path has a first current and is configured so that the first current increases in response to a decrease in the input voltage and decreases in response to an increase in the input voltage. The second current path has a second current and is configured so that the second current decreases in response to the decrease in the input voltage and decreases in response to the increase in the input voltage. The VCO further includes a third current path combining a first proportion of the first current and a second proportion of the second current into a combined current; and a current-controlled oscillator (CCO) including an input receiving the combined current and outputting an AC signal.
摘要翻译：电路包括压控振荡器（VCO），其包括具有输入电压的电压输入节点; 和启动电路。启动电路包括第一电流路径和第二电流路径。第一电流路径具有第一电流并且被配置为使得第一电流响应于输入电压的降低而增加，并且响应于输入电压的增加而减小。第二电流路径具有第二电流并且被配置为使得第二电流响应于输入电压的降低而减小，并且响应于输入电压的增加而减小。 VCO还包括将第一电流的第一比例和第二电流的第二比例组合成组合电流的第三电流通路; 以及电流控制振荡器（CCO），其包括接收组合电流的输入并输出AC信号。

6. 发明授权

US08183914B2 Constant Gm circuit and methods 有权
标题翻译：恒定电路和方法
公开(公告)号：US08183914B2
公开(公告)日：2012-05-22
申请号：US12617583
申请日：2009-11-12
申请人： Tsung-Hsien Tsai , Chien-Hung Chen , Min-Shueh Yuan
发明人： Tsung-Hsien Tsai , Chien-Hung Chen , Min-Shueh Yuan
IPC分类号： G05F1/575 , G05F1/567
CPC分类号： G05F3/242
摘要： Structures and methods for providing a temperature independent constant current reference are provided. A constant Gm circuit is disclosed with embodiments including a voltage controlled resistor providing a current into a current mirror, the current mirror sinking a reference current at its output. By providing a feedback loop that controls the voltage controlled resistor, a temperature compensated circuit may be obtained. The temperature dependence of the voltage controlled resistor is positive and the feedback circuitry maintains this resistor at a value that compensates for the negative temperature dependence of the current mirror circuit. The reference current is thus obtained at a predetermined level independent of temperature. A method for providing a reference current is disclosed wherein a voltage dependent resistor is provided supply current to a current mirror, the voltage dependent resistor receiving a feedback voltage from the current mirror and the feedback controlling the resistor so that a temperature independent reference current is obtained.
摘要翻译：提供了提供独立于温度的恒流基准的结构和方法。公开了一种恒定的Gm电路，其实施例包括向电流镜提供电流的电压控制电阻器，电流镜在其输出端吸收参考电流。通过提供控制压控电阻器的反馈回路，可以获得温度补偿电路。电压控制电阻的温度依赖性为正，并且反馈电路将该电阻保持在补偿电流镜电路的负温度依赖性的值。因此，在与温度无关的预定水平上获得参考电流。公开了一种用于提供参考电流的方法，其中提供电压依赖电阻器供应电流到电流镜，电压相关电阻器接收来自电流镜的反馈电压和控制电阻器的反馈，使得获得与温度无关的参考电流。

7. 发明申请

US20100176777A1 Constant Gm Circuit and Methods 有权
标题翻译：恒定电路和方法
公开(公告)号：US20100176777A1
公开(公告)日：2010-07-15
申请号：US12617583
申请日：2009-11-12
申请人： Tsung-Hsien Tsai , Chien-Hung Chen , Min-Shueh Yuan
发明人： Tsung-Hsien Tsai , Chien-Hung Chen , Min-Shueh Yuan
IPC分类号： G05F1/10
CPC分类号： G05F3/242
摘要： Structures and methods for providing a temperature independent constant current reference are provided. A constant Gm circuit is disclosed with embodiments including a voltage controlled resistor providing a current into a current mirror, the current mirror sinking a reference current at its output. By providing a feedback loop that controls the voltage controlled resistor, a temperature compensated circuit may be obtained. The temperature dependence of the voltage controlled resistor is positive and the feedback circuitry maintains this resistor at a value that compensates for the negative temperature dependence of the current mirror circuit. The reference current is thus obtained at a predetermined level independent of temperature. A method for providing a reference current is disclosed wherein a voltage dependent resistor is provided supply current to a current mirror, the voltage dependent resistor receiving a feedback voltage from the current mirror and the feedback controlling the resistor so that a temperature independent reference current is obtained.
摘要翻译：提供了提供独立于温度的恒流基准的结构和方法。公开了一种恒定的Gm电路，其实施例包括向电流镜提供电流的电压控制电阻器，电流镜在其输出端吸收参考电流。通过提供控制压控电阻器的反馈回路，可以获得温度补偿电路。电压控制电阻的温度依赖性为正，并且反馈电路将该电阻保持在补偿电流镜电路的负温度依赖性的值。因此，在与温度无关的预定水平上获得参考电流。公开了一种用于提供参考电流的方法，其中提供电压依赖电阻器供应电流到电流镜，电压相关电阻器接收来自电流镜的反馈电压和控制电阻器的反馈，使得获得与温度无关的参考电流。

8. 发明授权

US09229050B2 BIST circuit for phase measurement 有权
标题翻译：用于相位测量的BIST电路
公开(公告)号：US09229050B2
公开(公告)日：2016-01-05
申请号：US13205722
申请日：2011-08-09
申请人： Tsung-Hsien Tsai , Min-Shueh Yuan , Chih-Hsien Chang
发明人： Tsung-Hsien Tsai , Min-Shueh Yuan , Chih-Hsien Chang
IPC分类号： G01R31/3187 , G01R31/30 , G01R31/317
CPC分类号： G01R31/3016 , G01R31/31725 , G01R31/31726 , G01R31/31727 , G01R31/3187
摘要： A BIST circuit for high speed applications includes a phase difference detection circuit, a period-to-current conversion circuit having an input coupled to an output of the phase difference detection circuit and a current-to-voltage conversion circuit coupled to an output of the period-to-current conversion circuit. The phase difference detection circuit includes first NAND logic for receiving as inputs an input clock signal and a delayed version of an inverted version of the input clock signal; second NAND logic for receiving as inputs the inverted version of the input clock signal and a delayed version of the input clock signal; third NAND logic for receiving as inputs the input clock signal and the delayed version of the input clock signal; and fourth NAND logic for receiving as inputs the inverted version of the input clock signal and a delayed version of the inverted version of the input clock signal.
摘要翻译：用于高速应用的BIST电路包括相位差检测电路，具有耦合到相位差检测电路的输出的输入的周期到电流转换电路和耦合到该相位差检测电路的输出的电流 - 电压转换电路周期到电流转换电路。相位差检测电路包括用于接收输入时钟信号和输入时钟信号的反相版本的延迟版本作为输入的第一NAND逻辑; 用于接收输入时钟信号的反相版本和输入时钟信号的延迟版本的第二NAND逻辑; 用于接收输入时钟信号和输入时钟信号的延迟版本作为输入的第三NAND逻辑; 以及用于接收输入时钟信号的反相版本和输入时钟信号的反相版本的延迟版本的第四NAND逻辑。

9. 发明授权

US09148135B2 Real time automatic and background calibration at embedded duty cycle correlation 有权
标题翻译：嵌入式占空比相关的实时自动和背景校准
公开(公告)号：US09148135B2
公开(公告)日：2015-09-29
申请号：US13532881
申请日：2012-06-26
申请人： Matt Li , Tsung-Hsien Tsai , Mao-Hsuan Chou , Min-Shueh Yuan , Chih-Hsien Chang
发明人： Matt Li , Tsung-Hsien Tsai , Mao-Hsuan Chou , Min-Shueh Yuan , Chih-Hsien Chang
IPC分类号： G06F1/00 , H03K5/156 , G06F1/08
CPC分类号： H03K5/1565 , G06F1/08
摘要： The present disclosure relates to a clock generation system. The system includes a clock source, a tuning buffer, an output buffer, a duty cycle measurement circuit and an automatic calibration component. The clock source generates a clock signal. The tuning buffer is configured to generate a corrected clock signal from the clock signal according to adjustment values. The output buffer is configured to generate an output clock signal from the corrected clock signal. The duty cycle measurement circuit is configured measure a duty cycle of the output clock signal. The automatic calibration component is configured to generate the adjustment values according to the duty cycle measurement and the specification values.
摘要翻译：本公开涉及一种时钟发生系统。该系统包括时钟源，调谐缓冲器，输出缓冲器，占空比测量电路和自动校准部件。时钟源产生时钟信号。调谐缓冲器被配置为根据调整值从时钟信号产生校正的时钟信号。输出缓冲器被配置为从校正的时钟信号产生输出时钟信号。配置占空比测量电路来测量输出时钟信号的占空比。自动校准部件被配置为根据占空比测量值和规格值生成调整值。

10. 发明申请

US20130342252A1 Real Time Automatic and Background Calibration at Embedded Duty Cycle Correlation 有权
标题翻译：嵌入式占空比相关的实时自动和背景校准
公开(公告)号：US20130342252A1
公开(公告)日：2013-12-26
申请号：US13532881
申请日：2012-06-26
申请人： Matt Li , Tsung-Hsien Tsai , Mao-Hsuan Chou , Min-Shueh Yuan , Chih-Hsien Chang
发明人： Matt Li , Tsung-Hsien Tsai , Mao-Hsuan Chou , Min-Shueh Yuan , Chih-Hsien Chang
IPC分类号： H03K3/017
CPC分类号： H03K5/1565 , G06F1/08
摘要： The present disclosure relates to a clock generation system. The system includes a clock source, a tuning buffer, an output buffer, a duty cycle measurement circuit and an automatic calibration component. The clock source generates a clock signal. The tuning buffer is configured to generate a corrected clock signal from the clock signal according to adjustment values. The output buffer is configured to generate an output clock signal from the corrected clock signal. The duty cycle measurement circuit is configured measure a duty cycle of the output clock signal. The automatic calibration component is configured to generate the adjustment values according to the duty cycle measurement and the specification values.
摘要翻译：本公开涉及一种时钟发生系统。该系统包括时钟源，调谐缓冲器，输出缓冲器，占空比测量电路和自动校准部件。时钟源产生时钟信号。调谐缓冲器被配置为根据调整值从时钟信号产生校正的时钟信号。输出缓冲器被配置为从校正的时钟信号产生输出时钟信号。配置占空比测量电路来测量输出时钟信号的占空比。自动校准部件被配置为根据占空比测量值和规格值生成调整值。

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