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1. 发明申请

US20110177663A1 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件的半导体器件和制造方法
公开(公告)号：US20110177663A1
公开(公告)日：2011-07-21
申请号：US13076833
申请日：2011-03-31
申请人： TSUYOSHI KACHI
发明人： TSUYOSHI KACHI
IPC分类号： H01L21/336
CPC分类号： H01L29/7813 , H01L29/41766 , H01L29/4236 , H01L29/42372 , H01L29/4238 , H01L29/66719 , H01L29/66727 , H01L29/66734 , H01L29/7811
摘要： Generally, a power MOSFET mainly includes an active region occupying most of an internal region (a region where a gate electrode made of polysilicon or the like is integrated), and a surrounding gate contact region (where the gate electrode made of polysilicon or the like is derived outside a source metal covered region to make contact with a gate metal) (see FIG. 65 in a comparative example). Since the gate electrode made of polysilicon or the like has a stepped portion existing between both regions, a focus margin maybe reduced in a lithography step, including exposure or the like, for formation of a contact hole for a source or for a gate. The invention of the present application provides a semiconductor device having a trench gate type power MISFET with a gate electrode protruding from an upper surface of a semiconductor substrate, in which respective main upper surfaces of the gate electrode in an active region and a gate contact region are substantially at the same height.
摘要翻译：通常，功率MOSFET主要包括占据大部分内部区域（由多晶硅等形成的栅电极的区域）的有源区域和周围的栅极接触区域（其中由多晶硅等构成的栅极电极衍生在源极金属覆盖区域外部以与栅极金属接触）（参见比较例中的图65）。由于由多晶硅等制成的栅电极具有存在于两个区域之间的阶梯部分，所以在用于形成用于源极或栅极的接触孔的曝光等的光刻步骤中可能减小焦距。本申请的发明提供了一种半导体器件，其具有沟槽栅型功率MISFET，栅极电极从半导体衬底的上表面突出，其中有源区中的栅电极的主要上表面和栅极接触区域基本上处于相同的高度。

2. 发明授权

US07977739B2 Semiconductor device and manufacturing method for semiconductor device 失效
标题翻译：半导体装置及半导体装置的制造方法
公开(公告)号：US07977739B2
公开(公告)日：2011-07-12
申请号：US12491997
申请日：2009-06-25
申请人： Tsuyoshi Kachi
发明人： Tsuyoshi Kachi
IPC分类号： H01L29/72
CPC分类号： H01L29/7813 , H01L29/41766 , H01L29/4236 , H01L29/42372 , H01L29/4238 , H01L29/66719 , H01L29/66727 , H01L29/66734 , H01L29/7811
摘要： Generally, a power MOSFET mainly includes an active region occupying most of an internal region (a region where a gate electrode made of polysilicon or the like is integrated), and a surrounding gate contact region (where the gate electrode made of polysilicon or the like is derived outside a source metal covered region to make contact with a gate metal) (see FIG. 65 in a comparative example). Since the gate electrode made of polysilicon or the like has a stepped portion existing between both regions, a focus margin may be reduced in a lithography step, including exposure or the like, for formation of a contact hole for a source or for a gate. The invention of the present application provides a semiconductor device having a trench gate type power MISFET with a gate electrode protruding from an upper surface of a semiconductor substrate, in which respective main upper surfaces of the gate electrode in an active region and a gate contact region are substantially at the same height.
摘要翻译：通常，功率MOSFET主要包括占据大部分内部区域（由多晶硅等构成的栅极电极的区域）的有源区域和周围的栅极接触区域（其中由多晶硅等构成的栅极电极衍生在源极金属覆盖区域外部以与栅极金属接触）（参见比较例中的图65）。由于由多晶硅等制成的栅电极具有存在于两个区域之间的阶梯部分，所以在包括曝光等的光刻步骤中，可以减少用于形成用于源极或栅极的接触孔的焦距。本申请的发明提供了一种半导体器件，其具有沟槽栅型功率MISFET，栅极电极从半导体衬底的上表面突出，其中有源区中的栅电极的主要上表面和栅极接触区域基本上处于相同的高度。

3. 发明授权

US07968939B2 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07968939B2
公开(公告)日：2011-06-28
申请号：US12954877
申请日：2010-11-28
申请人： Hitoshi Matsuura , Yoshito Nakazawa , Tsuyoshi Kachi , Yuji Yatsuda
发明人： Hitoshi Matsuura , Yoshito Nakazawa , Tsuyoshi Kachi , Yuji Yatsuda
IPC分类号： H01L27/108 , H01L29/78
CPC分类号： H01L27/0629 , H01L21/26586 , H01L21/76897 , H01L29/0615 , H01L29/086 , H01L29/1095 , H01L29/41741 , H01L29/41766 , H01L29/42368 , H01L29/456 , H01L29/4933 , H01L29/66719 , H01L29/66727 , H01L29/66734 , H01L29/7806 , H01L29/7811 , H01L29/7813 , H01L29/7827 , H01L29/8725
摘要： A gate trench 13 is formed in a semiconductor substrate 10. The gate trench 13 is provided with a gate electrode 16 formed over a gate insulating film 14. A portion of the gate electrode 16 protrudes from the semiconductor substrate 10, and a sidewall 24 is formed over a side wall portion of the protruding portion. A body trench 25 is formed in alignment with an adjacent gate electrode 16. A cobalt silicide film 28 is formed over a surface of the gate electrode 16 and over a surface of the body trench 25. A plug 34 is formed using an SAC technique.
摘要翻译：栅极沟槽13形成在半导体衬底10中。栅极沟槽13设置有形成在栅极绝缘膜14上的栅电极16.栅电极16的一部分从半导体衬底10突出，侧壁24为形成在突出部分的侧壁部分上。形成与相邻的栅电极16对准的主体沟槽25.在栅电极16的表面上并在主体沟槽25的表面之上形成硅化钴膜28.使用SAC技术形成插塞34。

4. 发明授权

US07679136B2 Semiconductor device and manufacturing method of the same 有权
标题翻译：半导体器件及其制造方法相同
公开(公告)号：US07679136B2
公开(公告)日：2010-03-16
申请号：US11334446
申请日：2006-01-19
申请人： Tsuyoshi Kachi , Yoshinori Hoshino
发明人： Tsuyoshi Kachi , Yoshinori Hoshino
IPC分类号： H01L23/62
CPC分类号： H01L29/7811 , H01L29/0653 , H01L29/407 , H01L29/4236 , H01L29/4238 , H01L29/456 , H01L29/66727 , H01L29/66734 , H01L29/7813 , H01L2924/0002 , H01L2924/00
摘要： The on-resistance of a semiconductor device having a power transistor with a trench gate structure is reduced. A power MIS-FET with a trench gate structure is so formed that the relation expressed as 0≦b≦a holds, where a is the distance between an end of an interlayer insulating layer over the upper face of a semiconductor region for source and the end (position on the periphery of a trench) of the upper face of the semiconductor region for source farther from the gate electrode; and b is the length of the overlap between the interlayer insulating layer and the upper face of the semiconductor region for source. (b is the distance between the position of the end of the interlayer insulating layer over the upper face of the semiconductor region for source and position on the periphery of a trench). As a result, the area of contact between source pads and the semiconductor regions for source is increased, and further the distance between the source pads and a channel forming region can be shortened. Therefore, the on-resistance of the power MIS-FET with a trench gate structure can be reduced.
摘要翻译：具有沟槽栅极结构的功率晶体管的半导体器件的导通电阻减小。具有沟槽栅极结构的功率MIS-FET被形成为使得表示为0＆nlE; b＆nlE; a的关系成立，其中a是源极半导体区域的上表面上的层间绝缘层的端部与用于远离栅电极的源极的半导体区域的上表面的端部（沟槽的外围的位置）; b是层间绝缘层与源极半导体区域的上表面之间的重叠长度。（b是在源极的半导体区域的上表面上的层间绝缘层的端部的位置与沟槽的周边上的位置之间的距离）。结果，源极焊盘与源极半导体区域之间的接触面积增加，并且可以缩短源极焊盘与沟道形成区域之间的距离。因此，可以减小具有沟槽栅极结构的功率MIS-FET的导通电阻。

5. 发明授权

US07544568B2 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07544568B2
公开(公告)日：2009-06-09
申请号：US11836574
申请日：2007-08-09
申请人： Hitoshi Matsuura , Yoshito Nakazawa , Tsuyoshi Kachi , Yuji Yatsuda
发明人： Hitoshi Matsuura , Yoshito Nakazawa , Tsuyoshi Kachi , Yuji Yatsuda
IPC分类号： H01L27/108
CPC分类号： H01L27/0629 , H01L21/26586 , H01L21/76897 , H01L29/0615 , H01L29/086 , H01L29/1095 , H01L29/41741 , H01L29/41766 , H01L29/42368 , H01L29/456 , H01L29/4933 , H01L29/66719 , H01L29/66727 , H01L29/66734 , H01L29/7806 , H01L29/7811 , H01L29/7813 , H01L29/7827 , H01L29/8725
摘要： A gate trench 13 is formed in a semiconductor substrate 10. The gate trench 13 is provided with a gate electrode 16 formed over a gate insulating film 14. A portion of the gate electrode 16 protrudes from the semiconductor substrate 10, and a sidewall 24 is formed over a side wall portion of the protruding portion. A body trench 25 is formed in alignment with an adjacent gate electrode 16. A cobalt silicide film 28 is formed over a surface of the gate electrode 16 and over a surface of the body trench 25. A plug 34 is formed using an SAC technique.
摘要翻译：栅极沟槽13形成在半导体衬底10中。栅极沟槽13设置有形成在栅极绝缘膜14上的栅电极16.栅电极16的一部分从半导体衬底10突出，侧壁24为形成在突出部分的侧壁部分上。形成与相邻的栅电极16对准的主体沟槽25.在栅电极16的表面上并在主体沟槽25的表面之上形成硅化钴膜28.使用SAC技术形成插塞34。

6. 发明授权

US08741699B2 Method of manufacturing semiconductor device and semiconductor device 有权
标题翻译：制造半导体器件和半导体器件的方法
公开(公告)号：US08741699B2
公开(公告)日：2014-06-03
申请号：US13479360
申请日：2012-05-24
申请人： Daisuke Arai , Yoshito Nakazawa , Ikuo Hara , Tsuyoshi Kachi , Yoshinori Hoshino , Tsuyoshi Tabata
发明人： Daisuke Arai , Yoshito Nakazawa , Ikuo Hara , Tsuyoshi Kachi , Yoshinori Hoshino , Tsuyoshi Tabata
IPC分类号： H01L21/332
CPC分类号： H01L29/66325 , H01L29/0619 , H01L29/0696 , H01L29/404 , H01L29/66333 , H01L29/7395
摘要： Techniques capable of improving the yield of IGBTs capable of reducing steady loss, turn-off time, and turn-off loss are provided. Upon formation of openings in an interlayer insulting film formed on a main surface of a substrate, etching of a laminated insulating film of a PSG film and an SOG film and a silicon oxide film is once stopped at a silicon nitride film. Then, the silicon nitride film and the silicon oxide film are sequentially etched to form the openings. As a result, the openings are prevented from penetrating through an n-type source layer and a p+-type emitter layer having a thickness of 20 to 100 nm and reaching the substrate.
摘要翻译：提供了能够提高能够降低稳定损耗，关断时间和关断损耗的IGBT的产量的技术。在形成在基板的主表面上的层间绝缘膜中形成开口时，在氮化硅膜上一次停止对PSG膜的叠层绝缘膜，SOG膜和氧化硅膜的蚀刻。然后，依次蚀刻氮化硅膜和氧化硅膜以形成开口。结果，防止了开口穿过厚度为20至100nm的n型源极层和p +型发射极层并到达衬底。

7. 发明申请

US20110233665A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
公开(公告)号：US20110233665A1
公开(公告)日：2011-09-29
申请号：US13153348
申请日：2011-06-03
申请人： HITOSHI MATSUURA , Yoshito Nakazawa , Tsuyoshi Kachi , Yuji Yatsuda
发明人： HITOSHI MATSUURA , Yoshito Nakazawa , Tsuyoshi Kachi , Yuji Yatsuda
IPC分类号： H01L29/78
CPC分类号： H01L27/0629 , H01L21/26586 , H01L21/76897 , H01L29/0615 , H01L29/086 , H01L29/1095 , H01L29/41741 , H01L29/41766 , H01L29/42368 , H01L29/456 , H01L29/4933 , H01L29/66719 , H01L29/66727 , H01L29/66734 , H01L29/7806 , H01L29/7811 , H01L29/7813 , H01L29/7827 , H01L29/8725
摘要： A gate trench 13 is formed in a semiconductor substrate 10. The gate trench 13 is provided with a gate electrode 16 formed over a gate insulating film 14. A portion of the gate electrode 16 protrudes from the semiconductor substrate 10, and a sidewall 24 is formed over a side wall portion of the protruding portion. A body trench 25 is formed in alignment with an adjacent gate electrode 16. A cobalt silicide film 28 is formed over a surface of the gate electrode 16 and over a surface of the body trench 25. A plug 34 is formed using an SAC technique.

8. 发明申请

US20110068392A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20110068392A1
公开(公告)日：2011-03-24
申请号：US12954877
申请日：2010-11-28
申请人： HITOSHI MATSUURA , Yoshito Nakazawa , Tsuyoshi Kachi , Yuji Yatsuda
发明人： HITOSHI MATSUURA , Yoshito Nakazawa , Tsuyoshi Kachi , Yuji Yatsuda
IPC分类号： H01L29/78
CPC分类号： H01L27/0629 , H01L21/26586 , H01L21/76897 , H01L29/0615 , H01L29/086 , H01L29/1095 , H01L29/41741 , H01L29/41766 , H01L29/42368 , H01L29/456 , H01L29/4933 , H01L29/66719 , H01L29/66727 , H01L29/66734 , H01L29/7806 , H01L29/7811 , H01L29/7813 , H01L29/7827 , H01L29/8725
摘要： A gate trench 13 is formed in a semiconductor substrate 10. The gate trench 13 is provided with a gate electrode 16 formed over a gate insulating film 14. A portion of the gate electrode 16 protrudes from the semiconductor substrate 10, and a sidewall 24 is formed over a side wall portion of the protruding portion. A body trench 25 is formed in alignment with an adjacent gate electrode 16. A cobalt silicide film 28 is formed over a surface of the gate electrode 16 and over a surface of the body trench 25. A plug 34 is formed using an SAC technique.
摘要翻译：栅极沟槽13形成在半导体衬底10中。栅极沟槽13设置有形成在栅极绝缘膜14上的栅电极16.栅电极16的一部分从半导体衬底10突出，侧壁24为形成在突出部分的侧壁部分上。形成与相邻的栅电极16对准的主体沟槽25.在栅电极16的表面上并在主体沟槽25的表面之上形成硅化钴膜28.使用SAC技术形成插塞34。

9. 发明授权

US07825480B2 Power semiconductor device and manufacturing method of the same 有权
标题翻译：功率半导体器件及其制造方法相同
公开(公告)号：US07825480B2
公开(公告)日：2010-11-02
申请号：US12132610
申请日：2008-06-04
申请人： Hiroki Arai , Nobuyuki Shirai , Tsuyoshi Kachi
发明人： Hiroki Arai , Nobuyuki Shirai , Tsuyoshi Kachi
IPC分类号： H01L27/088
CPC分类号： H01L29/7811 , H01L29/0615 , H01L29/0619 , H01L29/0638 , H01L29/0696 , H01L29/402 , H01L29/41766 , H01L29/4238 , H01L29/66727 , H01L29/66734 , H01L29/7813
摘要： The characteristics of a semiconductor device including a trench-gate power MISFET are improved. The semiconductor device includes a substrate having an active region where the power MISFET is provided and an outer circumferential region which is located circumferentially outside the active region and where a breakdown resistant structure is provided, a pattern formed of a conductive film provided over the substrate in the outer circumferential region with an insulating film interposed therebetween, another pattern isolated from the pattern, and a gate electrode terminal electrically coupled to the gate electrodes of the power MISFET and provided in a layer over the conductive film. The conductive film of the pattern is electrically coupled to the gate electrode terminal, while the conductive film of another pattern is electrically decoupled from the gate electrode terminal.
摘要翻译：提高了包括沟槽栅极功率MISFET的半导体器件的特性。半导体器件包括具有设置有功率MISFET的有源区域的基板和位于有源区域的周向外侧并且设有耐击穿结构的外周区域，由设置在基板上的导电膜形成的图案具有介于其间的绝缘膜的外周区域，与图案隔离的另一图案，以及电连接到功率MISFET的栅电极并设置在导电膜上的层中的栅电极端子。图案的导电膜电耦合到栅电极端子，而另一图案的导电膜与栅电极端子电耦合。

10. 发明申请

US20100171174A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20100171174A1
公开(公告)日：2010-07-08
申请号：US12724409
申请日：2010-03-15
申请人： HITOSHI MATSUURA , Yoshito Nakazawa , Tsuyoshi Kachi , Yuji Yatsuda
发明人： HITOSHI MATSUURA , Yoshito Nakazawa , Tsuyoshi Kachi , Yuji Yatsuda
IPC分类号： H01L27/06
CPC分类号： H01L27/0629 , H01L21/26586 , H01L21/76897 , H01L29/0615 , H01L29/086 , H01L29/1095 , H01L29/41741 , H01L29/41766 , H01L29/42368 , H01L29/456 , H01L29/4933 , H01L29/66719 , H01L29/66727 , H01L29/66734 , H01L29/7806 , H01L29/7811 , H01L29/7813 , H01L29/7827 , H01L29/8725
摘要： A gate trench 13 is formed in a semiconductor substrate 10. The gate trench 13 is provided with a gate electrode 16 formed over a gate insulating film 14. A portion of the gate electrode 16 protrudes from the semiconductor substrate 10, and a sidewall 24 is formed over a side wall portion of the protruding portion. A body trench 25 is formed in alignment with an adjacent gate electrode 16. A cobalt silicide film 28 is formed over a surface of the gate electrode 16 and over a surface of the body trench 25. A plug 34 is formed using an SAC technique.
摘要翻译：栅极沟槽13形成在半导体衬底10中。栅极沟槽13设置有形成在栅极绝缘膜14上的栅电极16.栅电极16的一部分从半导体衬底10突出，侧壁24为形成在突出部分的侧壁部分上。形成与相邻的栅电极16对准的主体沟槽25.在栅电极16的表面上并在主体沟槽25的表面之上形成硅化钴膜28.使用SAC技术形成插塞34。

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