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1. 发明授权

US08813553B2 Device for peel test 有权
标题翻译：剥离试验装置
公开(公告)号：US08813553B2
公开(公告)日：2014-08-26
申请号：US13285191
申请日：2011-10-31
申请人： Yoshinori Hoshino
发明人： Yoshinori Hoshino
IPC分类号： G01N19/04 , G01N3/08
CPC分类号： G01N19/04 , G01N2203/0025 , G01N2203/0605
摘要： A device for a peel test. The device includes: a gripping member to grip an end of a test film to be peeled off a test object; a movable member linearly moving in a direction to or away from the gripping member; a holding member for the movable member capable of linearly moving in a direction along a peel surface of the test object while holding the test object; a moving mechanism configured to move the movable member linearly; a load measuring unit configured to measure a load applied to the gripping member; a first conversion mechanism to convert the linear motion of the movable member to rotational power, and output the rotational power; and a second conversion mechanism to convert the rotational power output from the first conversion mechanism to the linear motion of the holding member relative to the movable member.
摘要翻译：剥离试验装置。该装置包括：抓握构件，用于夹持待测试物体剥离的测试膜的端部; 可动构件，其在朝向或远离所述夹持构件的方向上直线移动; 用于可移动部件的保持部件，能够在保持被检体的同时沿着被检体的剥离面的方向直线移动; 移动机构，其构造成使所述可动构件线性移动; 负载测量单元，被配置为测量施加到所述夹持构件的负载; 第一转换机构，用于将可动构件的直线运动转换成旋转动力，并输出旋转动力; 以及第二转换机构，用于将从第一转换机构输出的旋转动力转换成保持构件相对于可动构件的直线运动。

2. 发明授权

US07679136B2 Semiconductor device and manufacturing method of the same 有权
标题翻译：半导体器件及其制造方法相同
公开(公告)号：US07679136B2
公开(公告)日：2010-03-16
申请号：US11334446
申请日：2006-01-19
申请人： Tsuyoshi Kachi , Yoshinori Hoshino
发明人： Tsuyoshi Kachi , Yoshinori Hoshino
IPC分类号： H01L23/62
CPC分类号： H01L29/7811 , H01L29/0653 , H01L29/407 , H01L29/4236 , H01L29/4238 , H01L29/456 , H01L29/66727 , H01L29/66734 , H01L29/7813 , H01L2924/0002 , H01L2924/00
摘要： The on-resistance of a semiconductor device having a power transistor with a trench gate structure is reduced. A power MIS-FET with a trench gate structure is so formed that the relation expressed as 0≦b≦a holds, where a is the distance between an end of an interlayer insulating layer over the upper face of a semiconductor region for source and the end (position on the periphery of a trench) of the upper face of the semiconductor region for source farther from the gate electrode; and b is the length of the overlap between the interlayer insulating layer and the upper face of the semiconductor region for source. (b is the distance between the position of the end of the interlayer insulating layer over the upper face of the semiconductor region for source and position on the periphery of a trench). As a result, the area of contact between source pads and the semiconductor regions for source is increased, and further the distance between the source pads and a channel forming region can be shortened. Therefore, the on-resistance of the power MIS-FET with a trench gate structure can be reduced.
摘要翻译：具有沟槽栅极结构的功率晶体管的半导体器件的导通电阻减小。具有沟槽栅极结构的功率MIS-FET被形成为使得表示为0＆nlE; b＆nlE; a的关系成立，其中a是源极半导体区域的上表面上的层间绝缘层的端部与用于远离栅电极的源极的半导体区域的上表面的端部（沟槽的外围的位置）; b是层间绝缘层与源极半导体区域的上表面之间的重叠长度。（b是在源极的半导体区域的上表面上的层间绝缘层的端部的位置与沟槽的周边上的位置之间的距离）。结果，源极焊盘与源极半导体区域之间的接触面积增加，并且可以缩短源极焊盘与沟道形成区域之间的距离。因此，可以减小具有沟槽栅极结构的功率MIS-FET的导通电阻。

3. 发明授权

US07084055B2 Method for manufacturing semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件的制造方法
公开(公告)号：US07084055B2
公开(公告)日：2006-08-01
申请号：US10930845
申请日：2004-09-01
申请人： Tsuyoshi Fujiwara , Katsuyuki Asaka , Yasuhiro Nariyoshi , Yoshinori Hoshino , Kazutoshi Oomori
发明人： Tsuyoshi Fujiwara , Katsuyuki Asaka , Yasuhiro Nariyoshi , Yoshinori Hoshino , Kazutoshi Oomori
IPC分类号： H01L21/4763
CPC分类号： H01L27/10885 , H01L21/02164 , H01L21/02274 , H01L21/02318 , H01L21/31604 , H01L21/31612 , H01L21/32051 , H01L21/76801 , H01L21/76828 , H01L21/76832 , H01L21/76837 , H01L27/10814 , H01L28/84 , H01L28/90
摘要： It is desirable to prevent breakage and separation of wiring of a semiconductor integrated circuit device, such as a bit-line of a DRAM. To accomplish this, disclosed is a method in which, e.g., a high density plasma silicon oxide film is deposited on wirings (e.g., a bit-line that is connected to the source and drain region of a memory cell selection MISFET of a DRAM memory cell) by means of a high density plasma CVD technique, at a first temperature, and the structure is subjected to RTA (heat treatment) at a second temperature higher than the first temperature (e.g., 750° C.). Via holes are then formed in the high density plasma silicon oxide film, and first and second conductive films are then formed, the first conductive film being formed in the via holes and at a third temperature lower than the first temperature. The first and second conductive layers are then polished to remain selectively within the via holes. In heat treating the high density plasma silicon oxide film, the temperature is raised from the first temperature to the second temperature at a maximum speed of 60° C./second or less.
摘要翻译：期望防止诸如DRAM的位线的半导体集成电路器件的布线的断裂和分离。为了实现这一点，公开了一种方法，其中例如将高密度等离子体氧化硅膜沉积在布线（例如，连接到DRAM存储器的存储器单元选择MISFET的源极和漏极区域的位线）在第一温度下，通过高密度等离子体CVD技术，在高于第一温度（例如750℃）的第二温度下对该结构进行RTA（热处理）。然后在高密度等离子体氧化硅膜中形成通孔，然后形成第一和第二导电膜，第一导电膜形成在通孔中并且在比第一温度低的第三温度下形成。然后抛光第一和第二导电层以选择性地保持在通孔内。在高密度等离子体氧化硅膜的热处理中，以60℃/秒以下的最高速度将温度从第一温度升高到第二温度。

4. 发明授权

US06803271B2 Method for manufacturing semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件的制造方法
公开(公告)号：US06803271B2
公开(公告)日：2004-10-12
申请号：US10187003
申请日：2002-07-02
申请人： Tsuyoshi Fujiwara , Katsuyuki Asaka , Yasuhiro Nariyoshi , Yoshinori Hoshino , Kazutoshi Oomori
发明人： Tsuyoshi Fujiwara , Katsuyuki Asaka , Yasuhiro Nariyoshi , Yoshinori Hoshino , Kazutoshi Oomori
IPC分类号： H01L218242
CPC分类号： H01L27/10885 , H01L21/02164 , H01L21/02274 , H01L21/02318 , H01L21/31604 , H01L21/31612 , H01L21/32051 , H01L21/76801 , H01L21/76828 , H01L21/76832 , H01L21/76837 , H01L27/10814 , H01L28/84 , H01L28/90
摘要： It is desirable to prevent breakage and separation of wiring of a semiconductor integrated circuit device, such as a bit-line of a DRAM. To accomplish this, an HDP silicone oxide film is deposited on a bit-line that is connected to the source and drain region of a memory cell selection MISFET of a DRAM memory cell by means of a high density plasma CVD technique, and the structure is subjected to RTA (heat treatment) at 750° C. The surface is polished, and then a capacitor to be connected to the other of the source and drain region of the memory cell selection MISFET is formed. As a result, even when a tantalum oxide film, that serves as a capacitance insulating film of the capacitor, is subjected to heat treatment, the film stress exerted on the bit-line is reduced, and breakage and separation of the bit-line are prevented.
摘要翻译：期望防止诸如DRAM的位线的半导体集成电路器件的布线的断裂和分离。为了实现这一点，HDP硅氧化物膜通过高密度等离子体CVD技术沉积在与DRAM存储单元的存储单元选择MISFET的源极和漏极区域连接的位线上，结构是在750℃下进行RTA（热处理）。抛光表面，然后形成要连接到存储单元选择MISFET的源极和漏极区域中的另一个的电容器。结果，即使当用作电容器的电容绝缘膜的氧化钽膜进行热处理时，施加在位线上的膜应力减小，位线的断裂和分离是防止了

5. 发明授权

US06721172B2 Mechanism for inserting and removing electronic circuit unit 有权
公开(公告)号：US06721172B2
公开(公告)日：2004-04-13
申请号：US10267370
申请日：2002-10-09
申请人： Hiroshi Katagiri , Katsuya Fujii , Tetsuya Takahashi , Yoshinori Hoshino , Satoshi Ueda , Yoshiyuki Sato
发明人： Hiroshi Katagiri , Katsuya Fujii , Tetsuya Takahashi , Yoshinori Hoshino , Satoshi Ueda , Yoshiyuki Sato
IPC分类号： H05K716
CPC分类号： H05K7/1409
摘要： In a mechanism for inserting and removing electronic circuit units against a shelf of an electrical device where the electronic circuit units are installed, the shelf includes a groove forming part, the electrical circuit unit includes a rotatable lever, a rotatable stopper, and a housing member, and the electrical circuit unit is locked with the shelf by rotating the lever.

6. 发明授权

US5227729A Fusion detecting system for relays 失效
标题翻译：用于继电器的熔断检测系统
公开(公告)号：US5227729A
公开(公告)日：1993-07-13
申请号：US674327
申请日：1991-04-15
申请人： Yoshinori Hoshino
发明人： Yoshinori Hoshino
IPC分类号： G01R31/00 , G01R31/327 , G05B19/048 , G05B19/05 , H01H47/00
CPC分类号： H01H47/004 , G01R31/3278
摘要： A fusion detecting system for relays is provided for detecting a fusion of relay contacts. Two fully-interlocked or semi-interlocked relays are connected in such a manner that they operate under identical conditions, and a fused state is detected based on the states of signals sent from series-connected make contacts and series-connected break contacts of the two relays. In the case of semi-interlocked relays (R1, R2), if a make contact (r12) is fused during a current supply to a coil, the other contact (r22) remains in an open state or at a make-contact side after the current supply to the coil is cut off, and if a break contact (r11) is fused, the other contact (r21) remains in an open state or at break-contact side after a current is supplied to the relay coil. Accordingly, by using two semi-interlocked relays under identical conditions and connecting same such that the make contacts and the break contacts are individually connected in series, a fusion of the relays can be detected based on signals sent from the contacts. A fusion of fully-interlocked relays can be detected in a like manner.

7. 发明申请

US20120080939A1 POWER TERMINAL BLOCK AND POWER SUPPLY APPARATUS 有权
标题翻译：电源端子和电源设备
公开(公告)号：US20120080939A1
公开(公告)日：2012-04-05
申请号：US13247511
申请日：2011-09-28
申请人： Keishi SHIMOWAKE , Yoshinori HOSHINO
发明人： Keishi SHIMOWAKE , Yoshinori HOSHINO
IPC分类号： H02J4/00 , H01R9/22
CPC分类号： H01R9/24 , H01R4/34 , Y10T307/25
摘要： A power terminal block includes a base made of an insulator, a plurality of power terminals electrically insulated from each other and disposed on the base, and a plurality of terminal bases, each terminal base including a base connecting part made of a conductor and electrically coupled to the power terminals, and a first conductor connecting part made of a conductor, the first conductor connecting part being physically and electrically coupled to the base connecting part, the base connecting part and the first conductor connecting part being provided at different heights, wherein adjoining terminal bases, electrically coupled to power terminals supplied with currents with different electrical potentials, are coupled with the first conductor connecting parts of adjoining terminal bases disposed in different directions.
摘要翻译：电源端子块包括由绝缘体制成的基座，彼此电绝缘并设置在基座上的多个电源端子和多个端子基座，每个端子基座包括由导体制成的基座连接部分，并且电耦合电源端子和由导体制成的第一导体连接部分，第一导体连接部分物理地和电耦合到基座连接部分，基座连接部分和第一导体连接部分设置在不同的高度处，其中邻接的电连接到提供有不同电位的电流的电源端子的端子台与设置在不同方向上的相邻端子台的第一导体连接部分耦合。

8. 发明申请

US20070242420A1 Cable connection interface for rack mount apparatus, and rack mount apparatus 有权
标题翻译：机架安装设备的电缆连接接口和机架安装设备
公开(公告)号：US20070242420A1
公开(公告)日：2007-10-18
申请号：US11808324
申请日：2007-06-08
申请人： Yoshinori Hoshino , Tomoyuki Hongoh
发明人： Yoshinori Hoshino , Tomoyuki Hongoh
IPC分类号： H02B1/00
CPC分类号： G02B6/4453 , G02B6/4452
摘要： A rack mount apparatus is provided in an optical transmission apparatus. The rack mount apparatus includes a rack, a shelf mounted in the rack and a cross-sectional L-shaped Panel installed in the rack under a device to be rotatable so as to take an opened position and a closed position. This enables not only an easy and reliable connection of an interface cable in the rack mount apparatus without imposing a stress thereon but also a flexible determination or change of a connection position of the interface cable and even considerable improvement of the working efficiency.
摘要翻译：在光传输装置中设置有机架安装装置。机架安装装置包括机架，安装在机架中的搁架和安装在机架下方的可横向旋转以便打开位置和闭合位置的横截面的L形面板。这不仅能够容易且可靠地将接口电缆连接到机架安装设备中，而不会在其上施加应力，而且可以灵活地确定或改变接口电缆的连接位置，甚至可以显着提高工作效率。

9. 发明授权

US5375652A Heat radiating apparatus for semiconductor device 失效
标题翻译：半导体装置用散热装置
公开(公告)号：US5375652A
公开(公告)日：1994-12-27
申请号：US103683
申请日：1993-08-10
申请人： Katsuki Matsunaga , Yasushi Kojima , Naoya Yamazaki , Kiyoshi Yoshida , Yoshinori Hoshino
发明人： Katsuki Matsunaga , Yasushi Kojima , Naoya Yamazaki , Kiyoshi Yoshida , Yoshinori Hoshino
IPC分类号： F28F3/02 , H01L23/40 , H05K7/20 , F28F7/00
CPC分类号： F28F3/02 , H01L23/4093 , H01L2924/0002
摘要： A heat radiating apparatus for a semiconductor device, in which said semiconductor device mounted on a circuit board is cooled by a radiator. The radiator is provided with a stepped portion, and fixing spring hardware having slit grooves is provided with a notch engaging with the stepped portion, so that the end of radiator is brought into contact with the outer surface of the semiconductor device when the stepped portion of the radiator engages with the notch portion of the fixing spring hardware. The stepped portion of the radiator is constituted of two stages, and the notch of the fixing spring hardware is provided with two notch portions engaging with the two-stage stepped portions of the radiator, respectively, so that the larger-diameter portion of the two-stage stepped portions of the radiator engages with the farthermost portion of the notch. Further, a male threaded portion is installed near the end of the radiator so that the male threaded portion of the radiator is threadedly fixed to the farthermost portion of the notch of the fixing spring hardware.
摘要翻译：一种用于半导体器件的散热装置，其中安装在电路板上的所述半导体器件由散热器冷却。散热器设置有阶梯部，具有狭缝槽的固定弹簧五金具有与台阶部接合的切口，使得散热器的端部与半导体器件的外表面接触，散热器与固定弹簧五金件的切口部接合。散热器的台阶部分由两段构成，固定弹簧五金件的槽口分别设置有与散热器的两级台阶部分相接合的两个切口部分，使得两者的较大直径部分 - 散热器的台阶部分与凹口的最远部分接合。此外，阳螺纹部分安装在散热器的端部附近，使得散热器的阳螺纹部分螺纹固定到固定弹簧五金件的凹口的最远部分。

10. 发明授权

US08469203B2 Cable connection interface for rack mount apparatus, and rack mount apparatus 有权
标题翻译：机架安装设备的电缆连接接口和机架安装设备
公开(公告)号：US08469203B2
公开(公告)日：2013-06-25
申请号：US11808324
申请日：2007-06-08
申请人： Yoshinori Hoshino , Tomoyuki Hongoh
发明人： Yoshinori Hoshino , Tomoyuki Hongoh
IPC分类号： A47F7/00
CPC分类号： G02B6/4453 , G02B6/4452
摘要： A rack mount apparatus is provided in an optical transmission apparatus. The rack mount apparatus includes a rack, a shelf mounted in the rack and a cross-sectional L-shaped Panel installed in the rack under a device to be rotatable so as to take an opened position and a closed position. This enables not only an easy and reliable connection of an interface cable in the rack mount apparatus without imposing a stress thereon but also a flexible determination or change of a connection position of the interface cable and even considerable improvement of the working efficiency.
摘要翻译：在光传输装置中设置有机架安装装置。机架安装装置包括机架，安装在机架中的搁架和安装在机架下方的可横向旋转以便打开位置和闭合位置的横截面的L形面板。这不仅能够容易且可靠地将接口电缆连接到机架安装设备中，而不会在其上施加应力，而且可以灵活地确定或改变接口电缆的连接位置，甚至可以显着提高工作效率。

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