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1. 发明授权

US08392667B2 Deadlock avoidance by marking CPU traffic as special 有权
标题翻译：通过将CPU流量标记为特殊来防止死锁
公开(公告)号：US08392667B2
公开(公告)日：2013-03-05
申请号：US12334394
申请日：2008-12-12
申请人： Samuel H. Duncan , David B. Glasco , Wei-Je Huang , Atul Kalambur , Patrick R. Marchand , Dennis K. Ma
发明人： Samuel H. Duncan , David B. Glasco , Wei-Je Huang , Atul Kalambur , Patrick R. Marchand , Dennis K. Ma
IPC分类号： G06F12/00
CPC分类号： G06F13/4221 , G06F9/3877 , G06F13/1663
摘要： Deadlocks are avoided by marking read requests issued by a parallel processor to system memory as “special.” Read completions associated with read requests marked as special are routed on virtual channel 1 of the PCIe bus. Data returning on virtual channel 1 cannot become stalled by write requests in virtual channel 0, thus avoiding a potential deadlock.
摘要翻译：通过将并行处理器向系统内存发出的读取请求作为特殊标记来避免死锁。与PCIe总线的虚拟通道1相连的读取完成与标记为特殊的读请求相关联。虚拟通道1上返回的数据不能因虚拟通道0中的写入请求而停止，从而避免潜在的死锁。

2. 发明授权

US07426597B1 Apparatus, system, and method for bus link width optimization of a graphics system 有权
标题翻译：用于图形系统的总线链路宽度优化的装置，系统和方法
公开(公告)号：US07426597B1
公开(公告)日：2008-09-16
申请号：US11229208
申请日：2005-09-16
申请人： William P. Tsu , Luc R. Bisson , Oren Rubinstein , Wei-Je Huang , Michael B. Diamond
发明人： William P. Tsu , Luc R. Bisson , Oren Rubinstein , Wei-Je Huang , Michael B. Diamond
IPC分类号： G06F13/40
CPC分类号： G06F13/4018 , Y02D10/14 , Y02D10/151
摘要： A bus permits the number of active serial data lanes of a data link to be re-negotiated in response to changes in bus bandwidth requirements. In one embodiment, one of the bus interfaces triggers a re-negotiation of link width and places a constraint on link width during the re-negotiation.
摘要翻译：总线允许响应于总线带宽要求的变化重新协商数据链路的有效串行数据通道的数量。在一个实施例中，一个总线接口触发链路宽度的重新协商，并且在重新协商期间对链路宽度设置约束。

3. 发明授权

US07136953B1 Apparatus, system, and method for bus link width optimization 有权
标题翻译：用于总线链路宽度优化的装置，系统和方法
公开(公告)号：US07136953B1
公开(公告)日：2006-11-14
申请号：US10431994
申请日：2003-05-07
申请人： Luc R. Bisson , Oren Rubinstein , Wei-Je Huang , Michael B. Diamond
发明人： Luc R. Bisson , Oren Rubinstein , Wei-Je Huang , Michael B. Diamond
IPC分类号： G06F13/40
CPC分类号： G06F13/4018 , G09G2330/021 , G09G2350/00 , Y02D10/14 , Y02D10/151
摘要： A bus permits the number of active serial data lanes of a data link to be re-negotiated in response to changes in bus bandwidth requirements. In one embodiment, one of the bus interfaces triggers a re-negotiation of link width and places a constraint on link width during the re-negotiation.
摘要翻译：总线允许响应于总线带宽要求的变化重新协商数据链路的有效串行数据通道的数量。在一个实施例中，一个总线接口触发链路宽度的重新协商，并且在重新协商期间对链路宽度设置约束。

4. 发明申请

US20050237327A1 Point-to-point bus bridging without a bridge controller 有权
标题翻译：无桥接控制器的点到点总线桥接
公开(公告)号：US20050237327A1
公开(公告)日：2005-10-27
申请号：US10831440
申请日：2004-04-23
申请人： Oren Rubinstein , Jonah Alben , Wei-Je Huang
发明人： Oren Rubinstein , Jonah Alben , Wei-Je Huang
IPC分类号： G06F3/14 , G06F13/14 , G06F15/80
CPC分类号： G06F3/14
摘要： A computer system includes an integrated graphics subsystem and a graphics connector for attaching either an auxiliary graphics subsystem or a loopback card. A first bus connection communicates data from the computer system to the integrated graphics subsystem. With a loopback card in place, data travels from the integrated graphics subsystem back to the computer system via a second bus connection. When the auxiliary graphics subsystem is attached, the integrated graphics subsystem operates in a data forwarding mode. Data is communicated to the integrated graphics subsystem via the first bus connection. The integrated graphics subsystem then forwards data to the auxiliary graphics subsystem. A portion of the second bus connection communicates data from the auxiliary graphics subsystem back to the computer system. The auxiliary graphics subsystem communicates display information back to the integrated graphics subsystem, where it is used to control a display device.
摘要翻译：计算机系统包括集成图形子系统和用于附加辅助图形子系统或回送卡的图形连接器。第一总线连接将数据从计算机系统传送到集成图形子系统。使用回送卡，数据通过第二总线连接从集成图形子系统传回计算机系统。当附加辅助图形子系统时，集成图形子系统以数据转发模式运行。数据经由第一总线连接传送到集成图形子系统。然后，集成图形子系统将数据转发到辅助图形子系统。第二总线连接的一部分将辅助图形子系统的数据传送回计算机系统。辅助图形子系统将显示信息传送回集成图形子系统，用于控制显示设备。

5. 发明申请

US20140082120A1 EFFICIENT CPU MAILBOX READ ACCESS TO GPU MEMORY 有权
标题翻译：高效的CPU邮箱读取访问GPU内存
公开(公告)号：US20140082120A1
公开(公告)日：2014-03-20
申请号：US13620232
申请日：2012-09-14
申请人： Dennis K. MA , Karan Gupta , Lei Tian , Franck R. Diard , Praveen Jain , Wei-Je Huang , Atul Kalambur
发明人： Dennis K. MA , Karan Gupta , Lei Tian , Franck R. Diard , Praveen Jain , Wei-Je Huang , Atul Kalambur
IPC分类号： G06F15/167
CPC分类号： G06F15/167 , G06F15/16 , G06F15/163 , G06F15/17 , G06F15/173
摘要： Techniques are disclosed for peer-to-peer data transfers where a source device receives a request to read data words from a target device. The source device creates a first and second read command for reading a first portion and a second portion of a plurality of data words from the target device, respectively. The source device transmits the first read command to the target device, and, before a first read operation associated with the first read command is complete, transmits the second read command to the target device. The first and second portions of the plurality of data words are stored in a first and second portion a buffer memory, respectively. Advantageously, an arbitrary number of multiple read operations may be in progress at a given time without using multiple peer-to-peer memory buffers. Performance for large data block transfers is improved without consuming peer-to-peer memory buffers needed by other peer GPUs.
摘要翻译：公开了用于对等数据传输的技术，其中源设备从目标设备接收到读取数据字的请求。源设备分别创建用于从目标设备读取多个数据字的第一部分和第二部分的第一和第二读取命令。源设备向目标设备发送第一读取命令，并且在与第一读取命令相关联的第一读取操作完成之前，将第二读取命令发送到目标设备。多个数据字的第一和第二部分分别存储在缓冲存储器的第一和第二部分中。有利地，任意数量的多个读取操作可以在给定时间进行，而不使用多个对等存储器缓冲器。改进了大数据块传输的性能，而不消耗其他对等GPU所需的对等内存缓冲区。

6. 发明申请

US20140013023A1 SYSTEM AND METHOD FOR SENDING ARBITRARY PACKET TYPES ACROSS A DATA CONNECTOR 有权
标题翻译：用于通过数据连接器发送仲裁分组类型的系统和方法
公开(公告)号：US20140013023A1
公开(公告)日：2014-01-09
申请号：US13541464
申请日：2012-07-03
申请人： Wei-Je HUANG , Dennis Ma , Hitendra Dutt
发明人： Wei-Je HUANG , Dennis Ma , Hitendra Dutt
IPC分类号： G06F13/20
CPC分类号： G06F13/385
摘要： A processing unit exchanges data with another processing unit across a data connector that supports a particular communication protocol. When the communication protocol is updated to support a new packet type, a specification of that new packet type may be stored within software registers included within the processing unit. Under circumstances that require the use of the new packet type, packet generation logic may read the packet specification of the new packet type, then generate and transmit a packet of the new type.
摘要翻译：处理单元通过支持特定通信协议的数据连接器与另一处理单元交换数据。当通信协议被更新以支持新的分组类型时，该新分组类型的规范可以被存储在包括在处理单元内的软件寄存器中。在需要使用新分组类型的情况下，分组生成逻辑可以读取新分组类型的分组规范，然后生成并发送新类型的分组。

7. 发明申请

US20140012904A1 PROVIDING BYTE ENABLES FOR PEER-TO-PEER DATA TRANSFER WITHIN A COMPUTING ENVIRONMENT 有权
标题翻译：在计算环境中提供与对等数据传输的字节使用
公开(公告)号：US20140012904A1
公开(公告)日：2014-01-09
申请号：US13541633
申请日：2012-07-03
申请人： Samuel H. DUNCAN , Dennis K. MA , Wei-Je HUANG , Gary WARD
发明人： Samuel H. DUNCAN , Dennis K. MA , Wei-Je HUANG , Gary WARD
IPC分类号： G06F15/16
CPC分类号： G06F15/167 , G06F15/16 , G06F15/163 , G06F15/17 , G06F15/173
摘要： Non-contiguous or tiled payload data are efficiently transferred between peers over a fabric. Specifically, a client transfers a byte enable message to a peer device via a mailbox mechanism, where the byte enable message specifies which bytes of the payload data being transferred via the data packet are to be written to the frame buffer on the peer device and which bytes are not to be written. The client transfers the non-contiguous or tiled payload payload data to the peer device. Upon receiving the payload data, the peer device writes bytes from the payload data into the target frame buffer for only those bytes enabled via the byte enable message. One advantage of the present invention is that non-contiguous or tiled data are transferred over a fabric with improved efficiency.
摘要翻译：非连续或平铺的有效载荷数据可以通过一个结构在对等体之间有效传输。具体来说，客户端通过邮箱机制向对等设备传送字节使能消息，其中字节使能消息指定要经由数据包传送的有效载荷数据的哪个字节将被写入对等设备上的帧缓冲器，以及哪个字节不被写入。客户端将非连续或平铺的有效载荷有效载荷数据传输到对等设备。在接收到有效载荷数据时，对等设备将字节从有效载荷数据写入目标帧缓冲器，以便仅通过字节使能消息使能的字节。本发明的一个优点在于，不连续的或平铺的数据以提高的效率在织物上传送。

8. 发明申请

US20130067127A1 METHOD AND APPARATUS FOR INTERLEAVING BURSTS OF HIGH-SPEED SERIAL INTERCONNECT LINK TRAINING WITH BUS DATA TRANSACTIONS 有权
标题翻译：高速串行互联链路训练与总线数据交换的冲突的方法和装置
公开(公告)号：US20130067127A1
公开(公告)日：2013-03-14
申请号：US13230694
申请日：2011-09-12
申请人： Michael Hopgood , Wei-Je Huang , Mark Taylor , Hitendra Dutt , David Wyatt , Vishal Mehta
发明人： Michael Hopgood , Wei-Je Huang , Mark Taylor , Hitendra Dutt , David Wyatt , Vishal Mehta
IPC分类号： G06F13/00
CPC分类号： G06F13/00 , G06F13/4282 , G06F2213/0026
摘要： In an apparatus according to one embodiment of the present disclosure, a communications link comprises a first device and a second device communicating with each other via the communications link at a plurality of different speeds. However, prior to communicating via the communications link for the first time at a second speed, the first device and second device complete a first training cycle at the second speed. Further, during this first training cycle for the second speed, the first training cycle for the second speed will pause before the first training cycle at the second speed completes, and the first device and second device communicate at a first speed for a period of time before returning to the paused first training cycle at the second speed. When the paused first training cycle for the second speed continues, the first training cycle for the second speed will continue where it had paused.
摘要翻译：在根据本公开的一个实施例的装置中，通信链路包括经由通信链路以多个不同速度彼此通信的第一设备和第二设备。然而，在以第二速度首次通过通信链路进行通信之前，第一设备和第二设备以第二速度完成第一训练周期。此外，在第二速度的第一训练周期期间，第二速度的第一训练周期将在第二速度的第一训练周期完成之前暂停，并且第一设备和第二设备以第一速度通信一段时间然后以第二速度返回到暂停的第一训练周期。当第二速度的暂停的第一训练周期继续时，第二速度的第一训练周期将继续停顿。

9. 发明授权

US08031198B1 Apparatus and method for servicing multiple graphics processing channels 有权
标题翻译：用于维护多个图形处理通道的装置和方法
公开(公告)号：US08031198B1
公开(公告)日：2011-10-04
申请号：US11555078
申请日：2006-10-31
申请人： Jeffrey M. Smith , Shail Dave , Wei-Je Huang , Lincoln G. Garlick , Paolo E. Sabella
发明人： Jeffrey M. Smith , Shail Dave , Wei-Je Huang , Lincoln G. Garlick , Paolo E. Sabella
IPC分类号： G06F15/00 , G06T1/00 , G06T15/00
CPC分类号： G06T1/20
摘要： An apparatus and method for servicing multiple graphics processing channels are described. In one embodiment, a graphics processing apparatus includes a scheduler configured to direct servicing of a graphics processing channel by issuing an index related to the graphics processing channel. The graphics processing apparatus also includes a processing core connected to the scheduler. The processing core is configured to service the graphics processing channel by: (i) correlating the index with a memory location at which an instance block for the graphics processing channel is stored; and (ii) accessing the instance block stored at the memory location.
摘要翻译：描述了一种用于维护多个图形处理通道的装置和方法。在一个实施例中，图形处理装置包括调度器，被配置为通过发布与图形处理通道相关的索引来直接对图形处理通道进行服务。图形处理装置还包括连接到调度器的处理核心。处理核心被配置为通过以下操作来服务图形处理通道：（i）将索引与存储图形处理通道的实例块的存储器位置相关联; 和（ii）访问存储在存储器位置的实例块。

10. 发明授权

US07756123B1 Apparatus, system, and method for swizzling of a PCIe link 有权
标题翻译：用于转换PCIe链路的装置，系统和方法
公开(公告)号：US07756123B1
公开(公告)日：2010-07-13
申请号：US11614901
申请日：2006-12-21
申请人： Wei-Je Huang , Nathan C. Myers
发明人： Wei-Je Huang , Nathan C. Myers
IPC分类号： H04Q3/00
CPC分类号： G06F13/4022
摘要： A peripheral component interface express (PCIe) controller include a crossbar to reorder data lanes into an order compatible with PCIe negotiation rules. A full crossbar permits an arbitrary swizzling of data lanes, permitting greater flexibility in motherboard lane routing.
摘要翻译：外围组件接口快速（PCIe）控制器包括一个交叉开关，以将数据通道重新排列成与PCIe协商规则兼容的顺序。一个完整的交叉开关允许任意旋转数据通道，允许在主板通道路由中更大的灵活性。

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