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1. 发明授权

US08637931B2 finFET with merged fins and vertical silicide 有权
标题翻译： finFET具有合并翅片和垂直硅化物
公开(公告)号：US08637931B2
公开(公告)日：2014-01-28
申请号：US13337874
申请日：2011-12-27
申请人： Veeraraghavan S. Basker , Andres Bryant , Huiming Bu , Wilfried Haensch , Effendi Leobandung , Chung-Hsun Lin , Theodorus E. Standaert , Tenko Yamashita , Chun-chen Yeh
发明人： Veeraraghavan S. Basker , Andres Bryant , Huiming Bu , Wilfried Haensch , Effendi Leobandung , Chung-Hsun Lin , Theodorus E. Standaert , Tenko Yamashita , Chun-chen Yeh
IPC分类号： H01L27/12
CPC分类号： H01L29/41791 , H01L29/66795
摘要： A finFET device is provided. The finFET device includes a BOX layer, fin structures located over the BOX layer, a gate stack located over the fin structures, gate spacers located on vertical sidewalls of the gate stack, an epi layer covering the fin structures, source and drain regions located in the semiconductor layers of the fin structures, and silicide regions abutting the source and drain regions. The fin structures each comprise a semiconductor layer and extend in a first direction, and the gate stack extends in a second direction that is perpendicular. The gate stack comprises a high-K dielectric layer and a metal gate, and the epi layer merges the fin structures together. The silicide regions each include a vertical portion located on the vertical sidewall of the source or drain region.
摘要翻译：提供了finFET器件。 finFET器件包括BOX层，位于BOX层上方的翅片结构，位于鳍结构上方的栅极堆叠，位于栅叠层的垂直侧壁上的栅极隔离物，覆盖翅片结构的外延层，位于翅片结构的半导体层和邻接源极和漏极区域的硅化物区域。翅片结构各自包括半导体层并沿第一方向延伸，并且栅极堆叠沿垂直的第二方向延伸。栅极堆叠包括高K电介质层和金属栅极，并且外延层将鳍结构融合在一起。硅化物区域各自包括位于源极或漏极区域的垂直侧壁上的垂直部分。

2. 发明授权

US08288826B2 Semiconductor-on-insulator (SOI) structures including gradient nitrided buried oxide (BOX) 有权
标题翻译：绝缘体上半导体（SOI）结构包括梯度氮化掩埋氧化物（BOX）
公开(公告)号：US08288826B2
公开(公告)日：2012-10-16
申请号：US13290634
申请日：2011-11-07
申请人： Anthony I. Chou , Toshiharu Furukawa , Wilfried Haensch , Zhibin Ren , Dinkar V. Singh , Jeffrey W. Sleight
发明人： Anthony I. Chou , Toshiharu Furukawa , Wilfried Haensch , Zhibin Ren , Dinkar V. Singh , Jeffrey W. Sleight
IPC分类号： H01L29/76 , H01L21/00
CPC分类号： H01L29/78603 , H01L27/1203 , H01L29/66772 , H01L29/78606 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor-on-insulator structure includes a buried dielectric layer interposed between a base semiconductor substrate and a surface semiconductor layer. The buried dielectric layer comprises an oxide material that includes a nitrogen gradient that peaks at the interface of the buried dielectric layer with at least one of the base semiconductor substrate and surface semiconductor layer. The interface of the buried dielectric layer with the at least one of the base semiconductor substrate and surface semiconductor layer is abrupt, providing a transition in less than about 5 atomic layer thickness, and having less than about 10 angstroms RMS interfacial roughness. A second dielectric layer comprising an oxide dielectric material absent nitrogen may be located interposed between the buried dielectric layer and the surface semiconductor layer.
摘要翻译：绝缘体上半导体结构包括插入在基底半导体衬底和表面半导体层之间的掩埋电介质层。掩埋介电层包括氧化物材料，其包括氮化物梯度，其在掩埋介电层的界面处与基底半导体衬底和表面半导体层中的至少一个相接触。掩埋介质层与基底半导体衬底和表面半导体层中的至少一个的界面是突然的，提供小于约5原子层厚度的转变，并且具有小于约10埃的RMS界面粗糙度。包含不含氮的氧化物介电材料的第二电介质层可位于掩埋介电层和表面半导体层之间。

3. 发明授权

US08053373B2 Semiconductor-on-insulator(SOI) structures including gradient nitrided buried oxide (BOX) 有权
标题翻译：绝缘体上半导体（SOI）结构包括梯度氮化掩埋氧化物（BOX）
公开(公告)号：US08053373B2
公开(公告)日：2011-11-08
申请号：US12123706
申请日：2008-05-20
申请人： Anthony I. Chou , Toshiharu Furukawa , Wilfried Haensch , Zhibin Ren , Dinkar V. Singh , Jeffrey W. Sleight
发明人： Anthony I. Chou , Toshiharu Furukawa , Wilfried Haensch , Zhibin Ren , Dinkar V. Singh , Jeffrey W. Sleight
IPC分类号： H01L21/31 , H01L29/76
CPC分类号： H01L29/78603 , H01L27/1203 , H01L29/66772 , H01L29/78606 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor-on-insulator structure includes a buried dielectric layer interposed between a base semiconductor substrate and a surface semiconductor layer. The buried dielectric layer comprises an oxide material that includes a nitrogen gradient that peaks at the interface of the buried dielectric layer with at least one of the base semiconductor substrate and surface semiconductor layer. The interface of the buried dielectric layer with the at least one of the base semiconductor substrate and surface semiconductor layer is abrupt, providing a transition in less than about 5 atomic layer thickness, and having less than about 10 angstroms RMS interfacial roughness. A second dielectric layer comprising an oxide dielectric material absent nitrogen may be located interposed between the buried dielectric layer and the surface semiconductor layer.
摘要翻译：绝缘体上半导体结构包括插入在基底半导体衬底和表面半导体层之间的掩埋电介质层。掩埋介电层包括氧化物材料，其包括氮化物梯度，其在掩埋介电层的界面处与基底半导体衬底和表面半导体层中的至少一个相接触。掩埋介质层与基底半导体衬底和表面半导体层中的至少一个的界面是突然的，提供小于约5原子层厚度的转变，并且具有小于约10埃的RMS界面粗糙度。包含不含氮的氧化物介电材料的第二电介质层可位于掩埋介电层和表面半导体层之间。

4. 发明申请

US20110170266A1 4D DEVICE PROCESS AND STRUCTURE 失效
标题翻译： 4D设备过程和结构
公开(公告)号：US20110170266A1
公开(公告)日：2011-07-14
申请号：US12684779
申请日：2010-01-08
申请人： Wilfried Haensch , Roy R. Yu
发明人： Wilfried Haensch , Roy R. Yu
IPC分类号： H05K7/20 , H01L21/78 , H01L21/306 , H01L21/66 , H05K1/14 , H05K1/11 , B32B37/02
CPC分类号： B32B37/02 , B32B37/12 , B32B38/1841 , B32B2309/105 , B32B2310/0843 , B32B2457/14 , H01L23/473 , H01L23/481 , H01L23/49827 , H01L24/09 , H01L24/32 , H01L24/81 , H01L24/83 , H01L24/92 , H01L24/94 , H01L24/96 , H01L24/97 , H01L25/0652 , H01L25/0657 , H01L25/18 , H01L25/50 , H01L29/0657 , H01L2224/0401 , H01L2224/05144 , H01L2224/05147 , H01L2224/06181 , H01L2224/08145 , H01L2224/13147 , H01L2224/16147 , H01L2224/26135 , H01L2224/291 , H01L2224/29147 , H01L2224/2919 , H01L2224/32145 , H01L2224/73253 , H01L2224/81191 , H01L2224/83005 , H01L2224/8314 , H01L2224/83141 , H01L2224/9202 , H01L2224/94 , H01L2224/96 , H01L2224/97 , H01L2225/06513 , H01L2225/06541 , H01L2225/06544 , H01L2225/06551 , H01L2225/06555 , H01L2225/06562 , H01L2225/06572 , H01L2225/06589 , H01L2225/06593 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01075 , H01L2924/01076 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/1032 , H01L2924/10329 , H01L2924/1204 , H01L2924/1431 , H01L2924/1434 , H01L2924/1461 , H01L2924/15153 , H01L2224/83 , H01L2924/00014 , H01L2224/03 , H01L2224/11 , H01L2224/81 , H01L2924/00
摘要： a 4D device comprises a 2D multi-core logic and a 3D memory stack connected through the memory stack sidewall using a fine pitch T&J connection. The 3D memory in the stack is thinned from the original wafer thickness to no remaining Si. A tounge and groove device at the memory wafer top and bottom surfaces allows an accurate stack alignment. The memory stack also has micro-channels on the backside to allow fluid cooling. The memory stack is further diced at the fixed clock-cycle distance and is flipped on its side and re-assembled on to a template into a pseudo-wafer format. The top side wall of the assembly is polished and built with BEOL to fan-out and use the T&J fine pitch connection to join to the 2D logic wafer. The other side of the memory stack is polished, fanned-out, and bumped with C4 solder. The invention also comprises a process for manufacturing the device. In another aspect, the invention comprises a 4D process and device for over 50× greter than 2D memory density per die and an ultra high density memory.
摘要翻译： 4D设备包括2D多核逻辑和通过存储器堆叠侧壁使用细间距T＆J连接连接的3D存储器堆栈。堆叠中的3D存储器从原始晶片厚度减薄到不剩余的Si。存储晶圆顶部和底部表面的凹槽和凹槽装置允许精确的堆叠对准。存储器堆栈还在背面具有微通道以允许流体冷却。存储器堆栈以固定的时钟周期距离进一步切割，并在其侧面翻转并且重新组装到模板上成为伪晶片格式。组件的顶侧壁被抛光并用BEOL构建以扇出，并且使用T＆J细间距连接来连接到2D逻辑晶片。存储器堆叠的另一面被抛光，扇形，并用C4焊料撞击。本发明还包括一种制造该装置的方法。在另一方面，本发明包括一个4D处理和装置，其超过每个芯片的2D存储密度超过50倍，而超高密度存储器。

5. 发明申请

US20090302372A1 Fin Field Effect Transistor Devices with Self-Aligned Source and Drain Regions 有权
标题翻译：具有自对准源极和漏极区域的鳍式场效应晶体管器件
公开(公告)号：US20090302372A1
公开(公告)日：2009-12-10
申请号：US12544939
申请日：2009-08-20
申请人： Josephine B. Chang , Michael A. Guillorn , Wilfried Haensch , Katherine Lynn Saenger
发明人： Josephine B. Chang , Michael A. Guillorn , Wilfried Haensch , Katherine Lynn Saenger
IPC分类号： H01L29/78
CPC分类号： H01L27/0886 , H01L29/66545 , H01L29/66553 , H01L29/66795 , H01L29/785 , H01L29/7854 , Y10S977/938
摘要： Improved fin field effect transistor (FinFET) devices and methods for the fabrication thereof are provided. In one aspect, a method for fabricating a field effect transistor device comprises the following steps. A substrate is provided having a silicon layer thereon. A fin lithography hardmask is patterned on the silicon layer. A dummy gate structure is placed over a central portion of the fin lithography hardmask. A filler layer is deposited around the dummy gate structure. The dummy gate structure is removed to reveal a trench in the filler layer, centered over the central portion of the fin lithography hardmask, that distinguishes a fin region of the device from source and drain regions of the device. The fin lithography hardmask in the fin region is used to etch a plurality of fins in the silicon layer. The trench is filled with a gate material to form a gate stack over the fins. The filler layer is removed to reveal the source and drain regions of the device, wherein the source and drain regions are intact and self-aligned with the gate stack.
摘要翻译：提供了改进的鳍状场效应晶体管（FinFET）器件及其制造方法。一方面，一种用于制造场效应晶体管器件的方法包括以下步骤。提供其上具有硅层的衬底。翅片光刻硬掩模在硅层上图案化。虚拟栅极结构放置在散热片光刻硬掩模的中心部分上。填充层沉积在伪栅极结构周围。去除伪栅极结构以在填充层中露出位于散热片光刻硬掩模的中心部分上方的沟槽，其将器件的鳍片区域与器件的源极和漏极区域区分开。翅片区域中的翅片光刻硬掩模用于蚀刻硅层中的多个翅片。沟槽填充有栅极材料，以在鳍片上形成栅极叠层。去除填充层以露出器件的源极和漏极区域，其中源极和漏极区域是完整的并且与栅极堆叠自对准。

6. 发明授权

US07601569B2 Partially depleted SOI field effect transistor having a metallized source side halo region 有权
标题翻译：部分耗尽的SOI场效应晶体管具有金属化源极侧区域
公开(公告)号：US07601569B2
公开(公告)日：2009-10-13
申请号：US11761568
申请日：2007-06-12
申请人： Jin Cai , Wilfried Haensch , Amlan Majumdar
发明人： Jin Cai , Wilfried Haensch , Amlan Majumdar
IPC分类号： H01L21/335 , H01L21/00 , H01L21/338 , H01L21/8234
CPC分类号： H01L29/78696 , H01L29/458 , H01L29/66772 , H01L29/78612 , H01L29/78624
摘要： Source and drain extension regions and source side halo region and drain side halo region are formed in a top semiconductor layer aligned with a gate stack on an SOI substrate. A deep source region and a deep drain region are formed asymmetrically in the top semiconductor layer by an angled ion implantation. The deep source region is offset away from one of the outer edges of the at least spacer to expose the source extension region on the surface of the semiconductor substrate. A source metal semiconductor alloy is formed by reacting a metal layer with portions of the deep source region, the source extension region, and the source side halo region. The source metal semiconductor alloy abuts the remaining portion of the source side halo region, providing a body contact tied to the deep source region to the partially depleted SOI MOSFET.
摘要翻译：源极和漏极延伸区域和源极侧卤素区域和漏极侧晕圈形成在与SOI衬底上的栅极堆叠对准的顶部半导体层中。通过成角度的离子注入，在顶部半导体层中不均匀地形成深源区和深漏区。深源区域远离至少间隔物的外缘之一偏离以暴露半导体衬底的表面上的源延伸区域。源金属半导体合金通过使金属层与深源区，源极延伸区和源极侧晕区的一部分反应而形成。源极金属半导体合金与源极侧光晕区域的剩余部分相邻，从而将与源极区域连接的体接触部分连接到部分耗尽的SOI MOSFET。

7. 发明申请

US20080315309A1 FIN FIELD EFFECT TRANSISTOR DEVICES WITH SELF-ALIGNED SOURCE AND DRAIN REGIONS 有权
标题翻译：具有自对准源和漏区的FIN场效应晶体管器件
公开(公告)号：US20080315309A1
公开(公告)日：2008-12-25
申请号：US11765931
申请日：2007-06-20
申请人： Josephine B. Chang , Michael A. Guillorn , Wilfried Haensch , Katherine Lynn Saenger
发明人： Josephine B. Chang , Michael A. Guillorn , Wilfried Haensch , Katherine Lynn Saenger
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L27/0886 , H01L29/66545 , H01L29/66553 , H01L29/66795 , H01L29/785 , H01L29/7854 , Y10S977/938
摘要： Improved fin field effect transistor (FinFET) devices and methods for the fabrication thereof are provided. In one aspect, a method for fabricating a field effect transistor device comprises the following steps. A substrate is provided having a silicon layer thereon. A fin lithography hardmask is patterned on the silicon layer. A dummy gate structure is placed over a central portion of the fin lithography hardmask. A tiller layer is deposited around the dummy gate structure. The dummy gate structure is removed to reveal a trench in the filler layer, centered over the central portion of the fin lithography hardmask, that distinguishes a fin region of the device from source and drain regions of the device. The fin lithography hardmask in the fin region is used to etch a plurality of fins in the silicon layer. The trench is filled with a gate material to form a gate stack over the fins. The filler layer is removed to reveal the source and drain regions of the device, wherein the source and drain regions are intact and self-aligned with the gate stack.
摘要翻译：提供了改进的鳍状场效应晶体管（FinFET）器件及其制造方法。一方面，一种用于制造场效应晶体管器件的方法包括以下步骤。提供其上具有硅层的衬底。翅片光刻硬掩模在硅层上图案化。虚拟栅极结构放置在散热片光刻硬掩模的中心部分上。捣实层沉积在虚拟栅极结构周围。去除伪栅极结构以在填充层中露出位于散热片光刻硬掩模的中心部分上方的沟槽，其将器件的鳍片区域与器件的源极和漏极区域区分开。翅片区域中的翅片光刻硬掩模用于蚀刻硅层中的多个翅片。沟槽填充有栅极材料，以在鳍片上形成栅极叠层。去除填充层以露出器件的源极和漏极区域，其中源极和漏极区域是完整的并且与栅极堆叠自对准。

8. 发明申请

US20080014740A1 Semiconductor-on-insulator (SOI) structures including gradient nitrided buried oxide (BOX) 有权
公开(公告)号：US20080014740A1
公开(公告)日：2008-01-17
申请号：US11483901
申请日：2006-07-10
申请人： Anthony I. Chou , Toshiharu Furukawa , Wilfried Haensch , Zhibin Ren , Dinkar V. Singh , Jeffrey W. Sleight
发明人： Anthony I. Chou , Toshiharu Furukawa , Wilfried Haensch , Zhibin Ren , Dinkar V. Singh , Jeffrey W. Sleight
IPC分类号： H01L21/4763
CPC分类号： H01L29/78603 , H01L27/1203 , H01L29/66772 , H01L29/78606 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor-on-insulator structure includes a buried dielectric layer interposed between a base semiconductor substrate and a surface semiconductor layer. The buried dielectric layer comprises an oxide material that includes a nitrogen gradient that peaks at the interface of the buried dielectric layer with at least one of the base semiconductor substrate and surface semiconductor layer. The interface of the buried dielectric layer with the at least one of the base semiconductor substrate and surface semiconductor layer is abrupt, providing a transition in less than about 5 atomic layer thickness, and having less than about 10 angstroms RMS interfacial roughness. A second dielectric layer comprising an oxide dielectric material absent nitrogen may be located interposed between the buried dielectric layer and the surface semiconductor layer.

9. 发明申请

US20070232020A1 HYBRID-ORIENTATION TECHNOLOGY BURIED N-WELL DESIGN 失效
标题翻译：混合技术渗透N型设计
公开(公告)号：US20070232020A1
公开(公告)日：2007-10-04
申请号：US11760836
申请日：2007-06-11
申请人： Wilfried Haensch , Edward Nowak
发明人： Wilfried Haensch , Edward Nowak
IPC分类号： H01L21/311
CPC分类号： H01L27/1203 , H01L27/1207 , H01L29/045
摘要： A semiconductor structure is provided that includes a hybrid orientated substrate having at least two coplanar surfaces of different surface crystal orientations, wherein one of the coplanar surfaces has bulk-like semiconductor properties and the other coplanar surface has semiconductor-on-insulator (SOI) properties. In accordance with the present invention, the substrate includes a new well design that provides a large capacitance from a retrograde well region of the second conductivity type to the substrate thereby providing noise decoupling with a low number of well contacts. The present invention also provides a method of fabricating such a semiconductor structure.
摘要翻译：提供一种半导体结构，其包括具有不同表面晶取向的至少两个共面表面的混合取向基板，其中共面中的一个具有块状半导体特性，而另一共面具有绝缘体上半导体（SOI）性质。根据本发明，衬底包括新的阱设计，其从第二导电类型的逆向阱区域向衬底提供大的电容，由此提供具有少量阱接触的噪声解耦。本发明还提供一种制造这种半导体结构的方法。

10. 发明申请

US20050204319A1 Threshold voltage roll-off compensation using back-gated mosfet devices for system high-performance and low standby power 有权
标题翻译：使用后门控mosfet器件进行系统高性能和低待机功耗的阈值电压滚降补偿
公开(公告)号：US20050204319A1
公开(公告)日：2005-09-15
申请号：US10796805
申请日：2004-03-09
申请人： Hussein Hanafi , Robert Dennard , Wilfried Haensch
发明人： Hussein Hanafi , Robert Dennard , Wilfried Haensch
IPC分类号： G06F17/50
CPC分类号： H03K19/0013
摘要： A method for compensating the threshold voltage roll-off using transistors containing back-gates or body nodes is provided. The method includes designing a semiconductor system or chip having a plurality of transistors with a channel length of Lnom. For the present invention, it is assumed that the channel length of these transistors at the completion of chip manufacturing is Lmax. This enables one to set the off-current to the maximum value of I-offmax which is done by setting the threshold voltage value to Vtmin. The Vtmin for these transistors is obtained during processing by using the proper implant dose. After manufacturing, the transistors are then tested to determine the off-current thereof. Some transistors within the system or chip will have an off-current value that meets a current specification. For those transistor devices, no further compensation is required. For other transistors within the system or chip, the off-current is not within the predetermined specification. For those transistors, threshold voltage roll-off has occurred since they are transistors that have a channel length that is less than nominal. For such short channel transistors, the threshold voltage is low, even lower than Vtmin, and the off-current is high, even higher than I-offmax. Compensation of the short channel transistors is achieved in the present invention by biasing the back-gate or body node to give increased threshold voltage about equal to Vtmin and hence an off-current that meets the predetermined specification, which is about equal to I-offmax.
摘要翻译：提供了使用包含背栅或体节点的晶体管补偿阈值电压滚降的方法。该方法包括设计具有通道长度为L nom的多个晶体管的半导体系统或芯片。对于本发明，假设在芯片制造完成时这些晶体管的沟道长度为L max max。这使得能够将截止电流设置为通过将阈值电压值设置为Vt分钟来完成的I-OFF 的最大值。通过使用适当的植入剂量，在处理期间获得这些晶体管的Vt 。在制造之后，然后测试晶体管以确定其截止电流。系统或芯片内的一些晶体管将具有满足当前规范的截止值。对于那些晶体管器件，不需要进一步的补偿。对于系统或芯片内的其他晶体管，截止电流不在预定的规范内。对于那些晶体管，已经发生阈值电压滚降，因为它们是具有小于额定值的沟道长度的晶体管。对于这种短沟道晶体管，阈值电压低，甚至低于Vt分钟<！ - SIPO - >，并且截止电流高，甚至高于I-off最大值。在本发明中通过偏置背栅极或体节点以提供大约等于Vt分钟的阈值电压，从而达到满足预定规格的截止电流来实现短沟道晶体管的补偿，其大约等于I-off最大。

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