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1. 发明申请

US20160320037A1 ELECTRONIC FABRIC 审中-公开
标题翻译：电子织物
公开(公告)号：US20160320037A1
公开(公告)日：2016-11-03
申请号：US15139648
申请日：2016-04-27
申请人： William S. Wong , John S. Morreale
发明人： William S. Wong , John S. Morreale
IPC分类号： F21V23/00 , F21V33/00 , F21V3/00
CPC分类号： F21V33/0008 , A41D1/005 , A41D27/085 , F21Y2107/70 , F21Y2115/10 , H05K1/038 , H05K1/114 , H05K1/189 , H05K2201/10106
摘要： An electronic fabric can include a first fabric layer, a second fabric layer, and a plurality of electronic devices. The first fabric layer can include a first set of conductive wires extending longitudinally in a first direction. The second fabric layer can define a plurality of apertures, can include a second set of conductive wires extending longitudinally in a second direction, and can be coupled to the first fabric layer such that each of the first set of conductive wires is arranged at a location of one of the plurality of apertures. Each electronic device can have a first terminal electrically coupled with one of the first set of conductive wires and a second terminal electrically coupled to one of the second set of conductive wires. The first terminal can be electrically coupled with the one of the first set of conductive wires through one of the plurality of apertures.
摘要翻译：电子织物可以包括第一织物层，第二织物层和多个电子器件。第一织物层可以包括沿第一方向纵向延伸的第一组导线。第二织物层可以限定多个孔，可以包括沿第二方向纵向延伸的第二组导线，并且可以耦合到第一织物层，使得第一组导线中的每一个布置在位置的多个孔中的一个。每个电子设备可以具有与第一组导线中的一个电耦合的第一端子和电耦合到第二组导线之一的第二端子。第一端子可以通过多个孔中的一个与第一组导线中的一个电耦合。

2. 发明授权

US09035673B2 Method of in-process intralayer yield detection, interlayer shunt detection and correction 有权
标题翻译：过程中内部产量检测，层间分流检测和校正方法
公开(公告)号：US09035673B2
公开(公告)日：2015-05-19
申请号：US12693019
申请日：2010-01-25
申请人： Michael Yu Tak Young , Scott Jong Ho Limb , William S. Wong , Robert A. Street
发明人： Michael Yu Tak Young , Scott Jong Ho Limb , William S. Wong , Robert A. Street
IPC分类号： G01R31/14 , G11C29/02 , G01R31/28 , H01L21/66 , G11C29/04
CPC分类号： G11C29/025 , G01R31/2853 , G11C2029/0403 , H01L22/14 , H01L22/20
摘要： A system and method for in-process yield evaluation and correction in an array type of device are provided. The system and method include measuring electrical resistance between individual GATE lines, DATA lines, a DATA bus I/O pad, and a GATE bus I/O pad; and analyzing the measured electrical resistance to identify at least one of the following: GATE line open defects, GATE line bridge defects, DATA line open defects, DATA line bridge defects, and interlayer shunt defects.
摘要翻译：提供了一种用于阵列型设备中的过程中产量评估和校正的系统和方法。该系统和方法包括测量各个GATE线路，DATA线路，DATA总线I / O焊盘和GATE总线I / O焊盘之间的电阻; 并分析测量的电阻以识别以下至少之一：GATE线路开路缺陷，GATE线路桥梁缺陷，DATA线路开路缺陷，DATA线路桥梁缺陷和层间分流缺陷。

3. 发明授权

US08603246B2 Growth reactor systems and methods for low-temperature synthesis of nanowires 有权
公开(公告)号：US08603246B2
公开(公告)日：2013-12-10
申请号：US12022563
申请日：2008-01-30
申请人： Pengfei Qi , William S Wong
发明人： Pengfei Qi , William S Wong
IPC分类号： C23C16/00 , C23C16/46 , C23C16/455
CPC分类号： H01L21/02603 , B01J7/00 , B01J15/005 , B01J19/2415 , B01J2219/00135 , B82Y40/00 , H01L21/0237 , H01L21/02422 , H01L21/02532 , H01L21/0262 , H01L21/02645 , Y10S118/00
摘要： A method for synthesis of silicon nanowires provides a growth reactor having a decomposition zone and a deposition zone. A precursor gas introduced into the decomposition zone is disassociated to form an activated species that reacts with catalyst materials located in the deposition zone to deposit nano-structured materials on a low melting point temperature substrate in the deposition zone. A decomposition temperature in the decomposition zone is greater than a melting point temperature of the low melting point temperature substrate. The silicon nanowire are grown directly on the low melting point temperature substrate in the deposition zone to prevent the higher temperatures in the decomposition zone from damaging the molecular structure and/or integrity of the lower melting point temperature substrate located in the deposition zone.

4. 发明授权

US08291352B2 Multivariable solver for optical proximity correction 有权
标题翻译：用于光学邻近校正的多变量求解器
公开(公告)号：US08291352B2
公开(公告)日：2012-10-16
申请号：US12721331
申请日：2010-03-10
申请人： William S. Wong , Been-Der Chen , Yenwen Lu , Jiangwei Li , Tatsuo Nishibe
发明人： William S. Wong , Been-Der Chen , Yenwen Lu , Jiangwei Li , Tatsuo Nishibe
IPC分类号： G06F17/50
CPC分类号： G03F1/144 , G03F1/36 , G03F7/70441 , G03F7/705
摘要： The method of the invention tracks how the collective movement of edge segments in a mask layout alters the resist image values at control points in the layout and simultaneously determines a correction amount for each edge segment in the layout. A multisolver matrix that represents the collective effect of movements of each edge segment in the mask layout is used to simultaneously determine the correction amount for each edge segment in the mask layout.
摘要翻译：本发明的方法跟踪掩模布局中边缘段的集体移动如何在布局中的控制点处改变抗蚀剂图像值，同时确定布局中每个边缘段的校正量。用于表示掩模布局中每个边缘段的移动的集合效果的多分离器矩阵用于同时确定掩模布局中每个边缘段的校正量。

5. 发明申请

US20120205656A1 Thin-Film Electronic Devices Including Pre-Deformed Compliant Substrate 审中-公开
标题翻译：薄膜电子器件包括符合预变形的基板
公开(公告)号：US20120205656A1
公开(公告)日：2012-08-16
申请号：US13453881
申请日：2012-04-23
申请人： Rene Lujan , William S. Wong , Julia R. Greer
发明人： Rene Lujan , William S. Wong , Julia R. Greer
IPC分类号： H01L29/786
CPC分类号： H01L27/1218
摘要： A thin-film layered electronic device, or array of devices, is formed over a layer structure comprising a flexible substrate, a buffer layer, and a metal layer. The layer structure is annealed to permanently deform the layer structure beyond its plastic deformation limit. The thin-film electronic device is formed thereover by a process according to which all steps are performed at a temperature below that at which further plastic deformation of the buffer layer occurs. In-process strain and runout are reduced, improving device yield on flexible substrates. The metal layer forms a first layer of the thin-film layered device, or array of devices.
摘要翻译：在包括柔性衬底，缓冲层和金属层的层结构上形成薄膜层状电子器件或器件阵列。层结构退火以使层结构永久变形超过其塑性变形极限。薄膜电子器件通过一种方法形成，根据该工艺，所有步骤都在低于缓冲层进一步塑性变形的温度下进行。过程中的应变和跳动减少，提高柔性基板上的器件产量。金属层形成薄膜分层器件的第一层或器件阵列。

6. 发明授权

US08239786B2 Local multivariable solver for optical proximity correction in lithographic processing method, and device manufactured thereby 有权
标题翻译：用于光刻处理方法中的光学邻近校正的局部多变量求解器，以及由此制造的器件
公开(公告)号：US08239786B2
公开(公告)日：2012-08-07
申请号：US12644790
申请日：2009-12-22
申请人： William S. Wong , Fei Liu , Been-Der Chen , Yen-Wen Lu
发明人： William S. Wong , Fei Liu , Been-Der Chen , Yen-Wen Lu
IPC分类号： G06F17/50
CPC分类号： G03F1/36
摘要： A multivariable solver for proximity correction uses a Jacobian matrix to approximate effects of perturbations of segment locations in successive iterations of a design loop. The problem is formulated as a constrained minimization problem with box, linear equality, and linear inequality constraints. To improve computational efficiency, non-local interactions are ignored, which results in a sparse Jacobian matrix.
摘要翻译：用于近程校正的多变量求解器使用雅可比矩阵近似设计循环的连续迭代中的段位置的扰动效应。该问题被形成为具有框，线性等式和线性不等式约束的约束最小化问题。为了提高计算效率，忽略非局部相互作用，这导致了稀疏的雅可比矩阵。

7. 发明申请

US20120164781A1 Disordered Nanowire Solar Cell 审中-公开
标题翻译：无序纳米线太阳能电池
公开(公告)号：US20120164781A1
公开(公告)日：2012-06-28
申请号：US13410224
申请日：2012-03-01
申请人： Robert A. Street , William S. Wong
发明人： Robert A. Street , William S. Wong
IPC分类号： H01L31/105 , H01L31/18
CPC分类号： H01L31/035227 , H01L31/075 , Y02E10/548
摘要： A disordered nanowire solar cell includes doped silicon nanowires disposed in a disordered nanowire mat, a thin (e.g., 50 nm) p-i-n coating layer formed on the surface of the silicon nanowires, and a conformal conductive layer disposed on the upper (e.g., n-doped) layer of the p-i-n coating layer. The disordered nanowire mat is grown from a seed layer using VLS processing at a high temperature (e.g., 450° C.), whereby the crystalline silicon nanowires assume a random interwoven pattern that enhances light scattering. Light scattered by the nanowires is absorbed by p-i-n layer, causing, e.g., electrons to pass along the nanowires to the first electrode layer, and holes to pass through the conformal conductive layer to an optional upper electrode layer. Fabrication of the disordered nanowire solar cell is large-area compatible.
摘要翻译：无序的纳米线太阳能电池包括设置在无序纳米线垫中的掺杂硅纳米线，形成在硅纳米线表面上的薄（例如50nm）的针涂层，以及设置在上层（例如，掺杂）层。无序纳米线垫在高温（例如450℃）下使用VLS处理从种子层生长，由此晶体硅纳米线呈现增强光散射的随机交织图案。由纳米线散射的光被p-i-n层吸收，导致例如电子沿着纳米线传递到第一电极层，并且空穴通过共形导电层到可选的上电极层。无序纳米线太阳能电池的制造是大面积兼容的。

8. 发明授权

US08198127B2 Charge mapping memory array formed of materials with mutable electrical characteristics 有权
标题翻译：电荷映射存储器阵列由具有可变电特性的材料形成
公开(公告)号：US08198127B2
公开(公告)日：2012-06-12
申请号：US12622210
申请日：2009-11-19
申请人： William S. Wong , Sanjiv Sambandan , Tse Nga Ng , Robert A. Street
发明人： William S. Wong , Sanjiv Sambandan , Tse Nga Ng , Robert A. Street
IPC分类号： H01L51/40
CPC分类号： G11C13/003 , B82Y10/00 , G11C11/22 , G11C13/0014 , G11C13/0016 , G11C2213/53 , G11C2213/74 , G11C2213/79 , G11C2213/80
摘要： A memory cell array including a data line; a capacitor; and a transistor coupled between the data line and the capacitor. At least one of the capacitor and the transistor includes a material with a mutable electrical characteristic. A memory cell array including a first transistor coupled between a first node, a second node, and a third node; and a second transistor coupled between the second node and a fourth node. The first transistor includes a material with a mutable electrical characteristic.
摘要翻译：包括数据线的存储单元阵列; 电容器以及耦合在数据线和电容器之间的晶体管。电容器和晶体管中的至少一个包括具有可变电特性的材料。一种存储单元阵列，包括耦合在第一节点，第二节点和第三节点之间的第一晶体管; 以及耦合在所述第二节点和第四节点之间的第二晶体管。第一晶体管包括具有可变电特性的材料。

9. 发明授权

US08193601B2 Structure and method for flexible sensor array 有权
标题翻译：柔性传感器阵列的结构和方法
公开(公告)号：US08193601B2
公开(公告)日：2012-06-05
申请号：US12692379
申请日：2010-01-22
申请人： Sanjiv Sambandan , William S. Wong , Rene A. Lujan , Scott J. Limb
发明人： Sanjiv Sambandan , William S. Wong , Rene A. Lujan , Scott J. Limb
IPC分类号： H01L31/102
CPC分类号： H01L27/14658 , H01L27/14692
摘要： A method of forming a sensor array. The method includes depositing a source/drain contact layer; depositing a semiconductor layer on the source/drain contact layer; and patterning the source/drain contact layer and the semiconductor layer substantially simultaneously, wherein the patterned semiconductor layer forms part of a sensor of the sensor array.
摘要翻译：一种形成传感器阵列的方法。该方法包括沉积源/漏接触层; 在源极/漏极接触层上沉积半导体层; 并且基本上同时构图源极/漏极接触层和半导体层，其中图案化的半导体层形成传感器阵列的传感器的一部分。

10. 发明授权

US08104863B2 Method for the printing of homogeneous electronic material with a multi-ejector print head 有权
标题翻译：使用多重喷射打印头打印均质电子材料的方法
公开(公告)号：US08104863B2
公开(公告)日：2012-01-31
申请号：US12787362
申请日：2010-05-25
申请人： Steven E. Ready , William S. Wong
发明人： Steven E. Ready , William S. Wong
IPC分类号： B41J29/393
CPC分类号： H05K3/125 , H01L21/288 , H01L21/76838 , H01L23/544 , H01L2924/0002 , H01L2924/00
摘要： Printing systems are disclosed that produce homogenous, smooth edged printed patterns (such as integrated circuit (IC) patterns) by separating pattern layouts into discrete design layers having only parallel layout features, and by printing each design layer using individual print solution droplets deposited onto the substrate. A first alignment operation is performed to achieve a specified orientation between the printhead and a first set of alignment marks on the substrate using first image data generated by the imaging sensor of the camera before performing a first print operation, and a second alignment operation to orient the printhead relative to a second set of alignment marks is performed before a second print operation. A first pattern layout portion includes first layout elements aligned parallel to a first reference axis, and the first print operation is performed by making multiple printing passes in a print direction aligned with the first reference axis.
摘要翻译：公开了印刷系统，其通过将图案布局分离成仅具有平行布局特征的离散设计层，并且通过使用沉积到所述图案上的各个印刷液滴印刷每个设计层来产生均匀的平滑边缘印刷图案（例如集成电路（IC）图案）基质。执行第一对准操作，以在执行第一打印操作之前使用由相机的成像传感器产生的第一图像数据在第二组对准操作之前在打印头和基板上的第一组对准标记之间实现指定的取向，在第二打印操作之前执行打印头相对于第二组对准标记。第一图案布局部分包括平行于第一参考轴线排列的第一布局元件，并且通过在与第一参考轴线对齐的打印方向上进行多次打印遍历来执行第一打印操作。

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