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1. 发明授权

US10066829B2 Electronic fabric 有权
公开(公告)号：US10066829B2
公开(公告)日：2018-09-04
申请号：US15139648
申请日：2016-04-27
申请人： William S. Wong , John S. Morreale
发明人： William S. Wong , John S. Morreale
IPC分类号： F21V33/00 , H05K1/03 , H05K1/18 , F21Y115/10 , F21Y107/70 , H05K1/11 , A41D27/08 , A41D1/00
摘要： An electronic fabric can include a first fabric layer, a second fabric layer, and a plurality of electronic devices. The first fabric layer can include a first set of conductive wires extending longitudinally in a first direction. The second fabric layer can define a plurality of apertures, can include a second set of conductive wires extending longitudinally in a second direction, and can be coupled to the first fabric layer such that each of the first set of conductive wires is arranged at a location of one of the plurality of apertures. Each electronic device can have a first terminal electrically coupled with one of the first set of conductive wires and a second terminal electrically coupled to one of the second set of conductive wires. The first terminal can be electrically coupled with the one of the first set of conductive wires through one of the plurality of apertures.

2. 发明申请

US20160320037A1 ELECTRONIC FABRIC 审中-公开
标题翻译：电子织物
公开(公告)号：US20160320037A1
公开(公告)日：2016-11-03
申请号：US15139648
申请日：2016-04-27
申请人： William S. Wong , John S. Morreale
发明人： William S. Wong , John S. Morreale
IPC分类号： F21V23/00 , F21V33/00 , F21V3/00
CPC分类号： F21V33/0008 , A41D1/005 , A41D27/085 , F21Y2107/70 , F21Y2115/10 , H05K1/038 , H05K1/114 , H05K1/189 , H05K2201/10106
摘要： An electronic fabric can include a first fabric layer, a second fabric layer, and a plurality of electronic devices. The first fabric layer can include a first set of conductive wires extending longitudinally in a first direction. The second fabric layer can define a plurality of apertures, can include a second set of conductive wires extending longitudinally in a second direction, and can be coupled to the first fabric layer such that each of the first set of conductive wires is arranged at a location of one of the plurality of apertures. Each electronic device can have a first terminal electrically coupled with one of the first set of conductive wires and a second terminal electrically coupled to one of the second set of conductive wires. The first terminal can be electrically coupled with the one of the first set of conductive wires through one of the plurality of apertures.
摘要翻译：电子织物可以包括第一织物层，第二织物层和多个电子器件。第一织物层可以包括沿第一方向纵向延伸的第一组导线。第二织物层可以限定多个孔，可以包括沿第二方向纵向延伸的第二组导线，并且可以耦合到第一织物层，使得第一组导线中的每一个布置在位置的多个孔中的一个。每个电子设备可以具有与第一组导线中的一个电耦合的第一端子和电耦合到第二组导线之一的第二端子。第一端子可以通过多个孔中的一个与第一组导线中的一个电耦合。

3. 发明授权

US08492876B2 Geometry and design for conformal electronics 有权
标题翻译：适形电子学的几何和设计
公开(公告)号：US08492876B2
公开(公告)日：2013-07-23
申请号：US12253390
申请日：2008-10-17
申请人： William S. Wong , Brent S. Krusor , Robert A. Street
发明人： William S. Wong , Brent S. Krusor , Robert A. Street
IPC分类号： H01L29/06
CPC分类号： H05K3/0044 , G02F2201/56 , H01L27/14603 , H01L27/14692 , H01L27/14812 , H01L29/78603
摘要： A method of forming a three-dimensional electronic device includes forming at least one electronic device on a two-dimensional, flexible substrate, the electronic device being formed according to a three-dimensional structure, cutting the two-dimensional, flexible substrate, the cuts being located to allow the two-dimensional substrate to be shaped, the cuts having at least one stress relief feature, and shaping the two-dimensional, flexible substrate to form the three-dimensional structure, the stress relief features arranged to alleviate stress in the three-dimensional structure. A method of forming a three-dimensional electronic device includes forming at least one electronic device on a two-dimensional, flexible substrate, the electronic device being formed according to a three-dimensional structure, cutting the two-dimensional, flexible substrate, the cuts being arranged to as to increase a radius of curvature to meet a stress relief parameter when the substrate is shaped, and shaping the two-dimensional, flexible substrate to form the three-dimensional structure. A three-dimensional electronic device having an electronic device formed on a flexible substrate, the flexible substrate formed into a three-dimensional structure, wedged-shaped portions removed from the substrate to allow the substrate to be formed into the three-dimensional structure, and a stress relief feature arranged adjacent to the wedge-shaped portions.
摘要翻译：形成三维电子器件的方法包括在二维柔性基板上形成至少一个电子器件，该电子器件根据三维结构形成，切割二维柔性基片，切割被设置成允许二维基底成形，切口具有至少一个应力消除特征，并且成形二维柔性基底以形成三维结构，应力消除特征被设置为减轻二维基底中的应力三维结构。形成三维电子器件的方法包括在二维柔性基板上形成至少一个电子器件，该电子器件根据三维结构形成，切割二维柔性基片，切割被布置成当基底成形时增加曲率半径以满足应力消除参数，并且将二维柔性基底成形以形成三维结构。一种具有形成在柔性基板上的电子器件的三维电子器件，形成为三维结构的柔性衬底，从衬底移除楔形部分以使衬底形成三维结构;以及紧邻楔形部分布置的应力消除特征。

4. 发明授权

US08411075B2 Large area electronic sheet and pixel circuits with disordered semiconductors for sensor actuator interface 有权
标题翻译：用于传感器执行器接口的大面积电子薄片和具有无序半导体的像素电路
公开(公告)号：US08411075B2
公开(公告)日：2013-04-02
申请号：US12206690
申请日：2008-09-08
申请人： Sanjiv Sambandan , William S. Wong , Robert A. Street
发明人： Sanjiv Sambandan , William S. Wong , Robert A. Street
IPC分类号： G06F3/038 , G06G5/00
CPC分类号： G06F3/038
摘要： A pixel circuit including a first transistor; a second transistor, the first transistor and the second transistor serially coupled between a first power supply terminal and a second power supply terminal; and a first capacitor coupled between a gate of the first transistor and a gate of the second transistor, and an electronic sheet including the same.
摘要翻译：一种像素电路，包括第一晶体管; 第二晶体管，第一晶体管和第二晶体管，串联耦合在第一电源端子和第二电源端子之间; 以及耦合在所述第一晶体管的栅极和所述第二晶体管的栅极之间的第一电容器以及包括所述第一晶体管的电子薄片。

5. 发明申请

US20120272196A1 Local Multivariable Solver for Optical Proximity Correction in Lithographic Processing Method, and Device Manufactured Thereby 有权
标题翻译：用于光刻接近校正的局部多变量求解器，以及由此制造的器件
公开(公告)号：US20120272196A1
公开(公告)日：2012-10-25
申请号：US13541638
申请日：2012-07-03
申请人： William S. Wong , Fei Liu , Been-Der Chen , Yen-Wen Lu
发明人： William S. Wong , Fei Liu , Been-Der Chen , Yen-Wen Lu
IPC分类号： G06F17/50
CPC分类号： G03F1/36
摘要： A multivariable solver for proximity correction uses a Jacobian matrix to approximate effects of perturbations of segment locations in successive iterations of a design loop. The problem is formulated as a constrained minimization problem with box, linear equality, and linear inequality constraints. To improve computational efficiency, non-local interactions are ignored, which results in a sparse Jacobian matrix.
摘要翻译：用于近程校正的多变量求解器使用雅可比矩阵近似设计循环的连续迭代中的段位置的扰动效应。该问题被形成为具有框，线性等式和线性不等式约束的约束最小化问题。为了提高计算效率，忽略非局部相互作用，这导致了稀疏的雅可比矩阵。

6. 发明授权

US08154009B1 Light emitting structure including high-al content MQWH 有权
标题翻译：发光结构包括高含量的MQWH
公开(公告)号：US08154009B1
公开(公告)日：2012-04-10
申请号：US12435342
申请日：2009-05-04
申请人： William S. Wong , Michael A. Kneissl , Zhihong Yang , Mark Teepe , Cliff Knollenberg
发明人： William S. Wong , Michael A. Kneissl , Zhihong Yang , Mark Teepe , Cliff Knollenberg
IPC分类号： H01L31/00
CPC分类号： H01L29/205 , B82Y20/00 , H01L29/155 , H01L29/2003 , H01L33/04 , H01L33/32 , H01S5/0213 , H01S5/0216 , H01S5/0217 , H01S5/0224 , H01S5/34333
摘要： A GaN/AlN superlattice is formed over a GaN/sapphire template structure, serving in part as a strain relief layer for growth of subsequent layers (e.g., deep UV light emitting diodes). The GaN/AlN superlattice mitigates the strain between a GaN/sapphire template and a multiple quantum well heterostructure active region, allowing the use of high Al mole fraction in the active region, and therefore emission in the deep UV wavelengths.
摘要翻译：在GaN /蓝宝石模板结构上形成GaN / AlN超晶格，其部分作为用于后续层（例如深UV发光二极管）生长的应变消除层。 GaN / AlN超晶格减轻GaN /蓝宝石模板和多量子阱异质结构有源区之间的应变，允许在有源区中使用高Al摩尔分数，从而在深紫外波长中发射。

7. 发明授权

US07964440B2 Phase-separated composite films and methods of preparing the same 有权
标题翻译：相分离复合膜及其制备方法
公开(公告)号：US07964440B2
公开(公告)日：2011-06-21
申请号：US11015795
申请日：2004-12-20
申请人： Alberto Salleo , Ana Claudia Arias , William S. Wong
发明人： Alberto Salleo , Ana Claudia Arias , William S. Wong
IPC分类号： H01L51/40
CPC分类号： B82Y30/00 , H01L27/28 , H01L51/0004 , H01L51/0015
摘要： Composite films formed from blends of semiconducting and insulating materials that phase separate on patterned substrates are provided. Phase separation provides isolated and encapsulated areas of semiconductor on the substrate. Processes for preparing and using such composite films are also provided, along with devices including such composite films.
摘要翻译：提供由在图案化衬底上相分离的半导体和绝缘材料的共混物形成的复合膜。相分离在衬底上提供隔离和封装的半导体区域。还提供了制备和使用这种复合膜的方法以及包括这种复合膜的装置。

8. 发明申请

US20110027947A1 PRINTING METHOD FOR HIGH PERFORMANCE ELECTRONIC DEVICES 有权
标题翻译：高性能电子设备的打印方法
公开(公告)号：US20110027947A1
公开(公告)日：2011-02-03
申请号：US12901365
申请日：2010-10-08
申请人： Michael L. Chabinyc , William S. Wong
发明人： Michael L. Chabinyc , William S. Wong
IPC分类号： H01L21/782
CPC分类号： H01L51/0005 , B82Y10/00 , H01L51/0012 , H01L51/0048 , H01L51/0545 , Y10S977/723 , Y10S977/786
摘要： A method of depositing elongated nanostructures that allows accurate positioning and orientation is described. The method involves printing or otherwise depositing elongated nanostructures in a carrier solution. The deposited droplets are also elongated, usually by patterning the surface upon which the droplets are deposited. As the droplet evaporates, the fluid flow within the droplets is controlled such that the nanostructures are deposited either at the edge of the elongated droplet or the center of the elongated droplet. The described deposition technique has particular application in forming the active region of a transistor.
摘要翻译：描述了允许精确定位和取向的细长纳米结构的沉积方法。该方法涉及在载体溶液中印刷或以其它方式沉积细长的纳米结构。沉积的液滴也是细长的，通常通过图案化沉积有液滴的表面。当液滴蒸发时，控制液滴内的流体流动，使得纳米结构沉积在细长液滴的边缘或细长液滴的中心。所描述的沉积技术特别适用于形成晶体管的有源区。

9. 发明授权

US07838933B2 Printing method for high performance electronic devices 有权
标题翻译：高性能电子设备的打印方法
公开(公告)号：US07838933B2
公开(公告)日：2010-11-23
申请号：US11644055
申请日：2006-12-22
申请人： Michael L. Chabinyc , William S. Wong
发明人： Michael L. Chabinyc , William S. Wong
IPC分类号： H01L27/12
CPC分类号： H01L51/0005 , B82Y10/00 , H01L51/0012 , H01L51/0048 , H01L51/0545 , Y10S977/723 , Y10S977/786
摘要： A method of depositing elongated nanostructures that allows accurate positioning and orientation is described. The method involves printing or otherwise depositing elongated nanostructures in a carrier solution. The deposited droplets are also elongated, usually by patterning the surface upon which the droplets are deposited. As the droplet evaporates, the fluid flow within the droplets is controlled such that the nanostructures are deposited either at the edge of the elongated droplet or the center of the elongated droplet. The described deposition technique has particular application in forming the active region of a transistor.
摘要翻译：描述了允许精确定位和取向的细长纳米结构的沉积方法。该方法涉及在载体溶液中印刷或以其它方式沉积细长的纳米结构。沉积的液滴也是细长的，通常通过图案化沉积有液滴的表面。当液滴蒸发时，控制液滴内的流体流动，使得纳米结构沉积在细长液滴的边缘或细长液滴的中心。所描述的沉积技术特别适用于形成晶体管的有源区。

10. 发明授权

US07824949B2 Structure and method for flexible sensor array 有权
标题翻译：柔性传感器阵列的结构和方法
公开(公告)号：US07824949B2
公开(公告)日：2010-11-02
申请号：US11963008
申请日：2007-12-21
申请人： Sanjiv Sambandan , William S. Wong , Rene A. Lujan , Scott J. Limb
发明人： Sanjiv Sambandan , William S. Wong , Rene A. Lujan , Scott J. Limb
IPC分类号： H01L21/00
CPC分类号： H01L27/14658 , H01L27/14692
摘要： A method of forming a sensor array. The method includes depositing a source/drain contact layer; depositing a semiconductor layer on the source/drain contact layer; and patterning the source/drain contact layer and the semiconductor layer substantially simultaneously, wherein the patterned semiconductor layer forms part of a sensor of the sensor array.
摘要翻译：一种形成传感器阵列的方法。该方法包括沉积源极/漏极接触层; 在源极/漏极接触层上沉积半导体层; 并且基本上同时构图源极/漏极接触层和半导体层，其中图案化的半导体层形成传感器阵列的传感器的一部分。

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