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1. 发明授权

US08533250B1 Multiplier with built-in accumulator 有权
标题翻译：带内置蓄能器的乘数
公开(公告)号：US08533250B1
公开(公告)日：2013-09-10
申请号：US12486231
申请日：2009-06-17
申请人： Kok Yoong Foo , Yan Jiong Boo , Geok Sun Chong , Boon Jin Ang , Kar Keng Chua
发明人： Kok Yoong Foo , Yan Jiong Boo , Geok Sun Chong , Boon Jin Ang , Kar Keng Chua
IPC分类号： G06F7/38 , G06F7/00
CPC分类号： G06F7/5443
摘要： Circuits for a multiplier with a built-in accumulator and a method of performing multiplication with accumulation are disclosed. An embodiment of the disclosed circuits includes a logic circuit coupled to receive two inputs. The logic circuit is capable of generating a plurality of value bits from the inputs received. In one embodiment, the logic circuit includes a Booth recoder circuit that generates a plurality of partial products. A block of adders is coupled to logic circuit to receive and sum up the value bits. An adder adds the summation result from the block of adders to a previous accumulated value to generate intermediate sum and carry values. An accumulator, coupled to the adder, receives and stores the intermediate values.
摘要翻译：公开了具有内置累加器的乘法器的电路和执行与累加相乘的方法。所公开的电路的实施例包括耦合以接收两个输入的逻辑电路。逻辑电路能够从接收到的输入产生多个值比特。在一个实施例中，逻辑电路包括生成多个部分乘积的布斯重新编码器电路。一组加法器耦合到逻辑电路以接收和总结值位。加法器将来自加法器块的求和结果相加到先前的累积值，以产生中间和和携带值。耦合到加法器的累加器接收并存储中间值。

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