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1. 发明授权

US08533250B1 Multiplier with built-in accumulator 有权
标题翻译：带内置蓄能器的乘数
公开(公告)号：US08533250B1
公开(公告)日：2013-09-10
申请号：US12486231
申请日：2009-06-17
申请人： Kok Yoong Foo , Yan Jiong Boo , Geok Sun Chong , Boon Jin Ang , Kar Keng Chua
发明人： Kok Yoong Foo , Yan Jiong Boo , Geok Sun Chong , Boon Jin Ang , Kar Keng Chua
IPC分类号： G06F7/38 , G06F7/00
CPC分类号： G06F7/5443
摘要： Circuits for a multiplier with a built-in accumulator and a method of performing multiplication with accumulation are disclosed. An embodiment of the disclosed circuits includes a logic circuit coupled to receive two inputs. The logic circuit is capable of generating a plurality of value bits from the inputs received. In one embodiment, the logic circuit includes a Booth recoder circuit that generates a plurality of partial products. A block of adders is coupled to logic circuit to receive and sum up the value bits. An adder adds the summation result from the block of adders to a previous accumulated value to generate intermediate sum and carry values. An accumulator, coupled to the adder, receives and stores the intermediate values.
摘要翻译：公开了具有内置累加器的乘法器的电路和执行与累加相乘的方法。所公开的电路的实施例包括耦合以接收两个输入的逻辑电路。逻辑电路能够从接收到的输入产生多个值比特。在一个实施例中，逻辑电路包括生成多个部分乘积的布斯重新编码器电路。一组加法器耦合到逻辑电路以接收和总结值位。加法器将来自加法器块的求和结果相加到先前的累积值，以产生中间和和携带值。耦合到加法器的累加器接收并存储中间值。

2. 发明授权

US08151224B1 Method of designing integrated circuits including providing an option to select a mask layer set 有权
标题翻译：设计集成电路的方法，包括提供选择掩模层集合的选项
公开(公告)号：US08151224B1
公开(公告)日：2012-04-03
申请号：US12345187
申请日：2008-12-29
申请人： Boon Jin Ang , Kar Keng Chua , Choong Kit Wong , Kok Yoong Foo , Thow Pang Chong
发明人： Boon Jin Ang , Kar Keng Chua , Choong Kit Wong , Kok Yoong Foo , Thow Pang Chong
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F2217/64
摘要： A method of designing at IC is described. In one embodiment, the method includes providing an option to select a mask layer set from a plurality of mask layer sets, the plurality of mask layer sets including a first mask layer set and a second mask layer set, where the second mask layer set is an alternative mask layer option to the first mask layer set. In one embodiment, the method further includes receiving a selection from a user choosing a mask layer set from the plurality of mask layer sets. In one embodiment, the receiving occurs after design of the IC and prior to fabrication of the IC. Also, in one embodiment, the plurality of mask layer sets are predetermined mask layer sets. In one embodiment, the first mask layer set is a standard threshold voltage (SVT) mask layer set and the second mask layer set is a high threshold voltage (HVT) mask layer set. In one embodiment, core devices of the SVT mask layer set are SVT devices and some periphery devices of the SVT mask layer set are HVT devices. In one embodiment, hybrid cell (H-cell) devices of the HVT mask layer set are HVT devices and some periphery devices of the HVT mask layer set are HVT devices.
摘要翻译：描述了一种IC设计方法。在一个实施例中，该方法包括提供从多个掩模层集合中选择掩模层集合的选项，所述多个掩模层集合包括第一掩模层集合和第二掩模层集合，其中第二掩模层集合是第一掩模层集合的替代掩模层选项。在一个实施例中，该方法还包括从用户接收从多个掩模层集合中选择掩模层集合的选择。在一个实施例中，接收发生在IC的设计之后并且在IC的制造之前。而且，在一个实施例中，多个掩模层组是预定的掩模层集合。在一个实施例中，第一掩模层集合是标准阈值电压（SVT）掩模层集合，第二掩模层集合是高阈值电压（HVT）掩模层集合。在一个实施例中，SVT掩模层集合的核心设备是SVT设备，SVT掩模层集合的一些外围设备是HVT设备。在一个实施例中，HVT掩模层集合的混合小区（H cell）设备是HVT设备，并且HVT掩模层集合的一些外围设备是HVT设备。

3. 发明授权

US07675336B1 Clock duty cycle recovery circuit 有权
标题翻译：时钟占空比恢复电路
公开(公告)号：US07675336B1
公开(公告)日：2010-03-09
申请号：US11016394
申请日：2004-12-17
申请人： Kok Yoong Foo , Tze Haw Liew , Joo Ming Too
发明人： Kok Yoong Foo , Tze Haw Liew , Joo Ming Too
IPC分类号： H03K3/017 , H03K5/04 , H03K7/08
CPC分类号： H03K5/1565
摘要： Circuits, methods, and apparatus that provide the improvement or recovery of a duty cycle of a clock signal. One embodiment of the present invention receives a clock signal that may have a degraded duty cycle. The frequency of the clock signal is divided by two. The frequency-divided signal is delayed in order to generate two signals that are phase shifted from one another by 90 degrees. These signals are then exclusive-ORed together to generate a recovered clock. A control loop is provided to adjust the phase shift between the signals to be approximately 90 degrees.
摘要翻译：提供时钟信号的占空比的改进或恢复的电路，方法和装置。本发明的一个实施例接收可能具有降低的占空比的时钟信号。时钟信号的频率除以2。分频信号被延迟以产生彼此相移90度的两个信号。这些信号然后被异或在一起以产生恢复的时钟。提供控制回路以将信号之间的相移调整为大约90度。

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