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1. 发明授权

US09099389B2 Method and apparatus for reducing stripe patterns 有权
标题翻译：减少条纹图案的方法和装置
公开(公告)号：US09099389B2
公开(公告)日：2015-08-04
申请号：US13371303
申请日：2012-02-10
申请人： Chung Chien Wang , Yeur-Luen Tu , Cheng-Ta Wu , Chia-Shiung Tsai
发明人： Chung Chien Wang , Yeur-Luen Tu , Cheng-Ta Wu , Chia-Shiung Tsai
IPC分类号： H01L21/268 , H01L27/146
CPC分类号： H01L21/268 , G01B11/14 , H01L27/1464 , H01L27/14643 , H01L27/14689
摘要： A method for reducing stripe patterns comprising receiving scattered light signals from a backside surface of a laser annealed backside illuminated image sensor wafer, generating a backside surface image based upon the scattered light signals, determining a distance between an edge of a sensor array of the laser anneal backside illuminated image sensor wafer and an adjacent boundary of a laser beam and re-calibrating the laser beam if the distance is less than a predetermined value.
摘要翻译：一种用于减少条纹图案的方法，包括从激光退火背面照射图像传感器晶片的背面接收散射光信号，基于散射光信号产生背面图像，确定激光器的传感器阵列的边缘之间的距离退火背面照射的图像传感器晶片和激光束的相邻边界，并且如果距离小于预定值则重新校准激光束。

2. 发明授权

US09059057B2 Image sensor having compressive layers 有权
标题翻译：具有压缩层的图像传感器
公开(公告)号：US09059057B2
公开(公告)日：2015-06-16
申请号：US13492258
申请日：2012-06-08
申请人： Chun-Han Tsao , Chih-Yu Lai , Chih-Hui Huang , Cheng-Ta Wu , Yeur-Luen Tu , Ching-Chun Wang , Shyh-Fann Ting , Chia-Shiung Tsai
发明人： Chun-Han Tsao , Chih-Yu Lai , Chih-Hui Huang , Cheng-Ta Wu , Yeur-Luen Tu , Ching-Chun Wang , Shyh-Fann Ting , Chia-Shiung Tsai
IPC分类号： H01L31/102 , H01L21/00 , H01L27/146 , H01L27/148
CPC分类号： H01L31/02164 , H01L27/14623 , H01L27/14632 , H01L27/1464 , H01L27/14643 , H01L27/14687 , H01L27/148 , H01L51/4273
摘要： An image sensor device including a semiconductor substrate that includes an array region and a black level correction region. The array region contains a plurality of radiation-sensitive pixels. The black level correction region contains one or more reference pixels. The substrate has a front side and a back side. The image sensor device includes a first compressively-stressed layer formed on the back side of the substrate. The first compressively-stressed layer contains silicon oxide, and is negatively charged. The second compressively-stressed layer contains silicon nitride, and is negatively charged. A metal shield is formed over at least a portion of the black level correction region. The image sensor device includes a third compressively-stressed layer formed on the metal shield and the second compressively-stressed layer. The third compressively-stressed layer contains silicon oxide. A sidewall of the metal shield is protected by the third compressively-stressed layer.
摘要翻译：一种包括具有阵列区域和黑色电平校正区域的半导体衬底的图像传感器装置。阵列区域包含多个辐射敏感像素。黑色电平校正区域包含一个或多个参考像素。基板具有前侧和后侧。图像传感器装置包括形成在基板的背面上的第一压缩应力层。第一压应力层含有氧化硅，带负电荷。第二压应力层含有氮化硅，带负电荷。在黑色电平校正区域的至少一部分上形成金属屏蔽。图像传感器装置包括形成在金属屏蔽和第二压缩应力层上的第三压缩应力层。第三压缩应力层含有氧化硅。金属屏蔽层的侧壁由第三压应力层保护。

3. 发明授权

US08802457B2 Backside surface treatment of semiconductor chips 有权
标题翻译：半导体芯片的背面表面处理
公开(公告)号：US08802457B2
公开(公告)日：2014-08-12
申请号：US13205179
申请日：2011-08-08
申请人： Chih-Yu Lai , Cheng-Ta Wu , Kai-Chun Hsu , Yeur-Luen Tu , Ching-Chun Wang , Chia-Shiung Tsai
发明人： Chih-Yu Lai , Cheng-Ta Wu , Kai-Chun Hsu , Yeur-Luen Tu , Ching-Chun Wang , Chia-Shiung Tsai
IPC分类号： H01L21/00 , H01L21/46 , H01L21/322
CPC分类号： H01L27/14687 , H01L27/1464
摘要： A method includes performing a grinding to a backside of a semiconductor substrate, wherein a remaining portion of the semiconductor substrate has a back surface. A treatment is then performed on the back surface using a method selected from the group consisting essentially of a dry treatment and a plasma treatment. Process gases that are used in the treatment include oxygen (O2). The plasma treatment is performed without vertical bias in a direction perpendicular to the back surface.
摘要翻译：一种方法包括对半导体衬底的背面进行研磨，其中半导体衬底的剩余部分具有背面。然后使用基本上由干法处理和等离子体处理组成的组中的方法在背面进行处理。用于处理的工艺气体包括氧（O 2）。在垂直于后表面的方向上进行等离子体处理而没有垂直偏压。

4. 发明授权

US08610229B2 Sidewall for backside illuminated image sensor metal grid and method of manufacturing same 有权
标题翻译：背面照明图像传感器金属网格的侧壁及其制造方法
公开(公告)号：US08610229B2
公开(公告)日：2013-12-17
申请号：US13087192
申请日：2011-04-14
申请人： Hung-Wen Hsu , Shih-Chang Liu , Yeur-Luen Tu
发明人： Hung-Wen Hsu , Shih-Chang Liu , Yeur-Luen Tu
IPC分类号： H01L27/146
CPC分类号： H01L27/14685 , H01L27/14623 , H01L27/14627 , H01L27/1464
摘要： The present disclosure provides an image sensor device and a method for manufacturing the image sensor device. An exemplary image sensor device includes a substrate having a front surface and a back surface; a plurality of sensor elements disposed at the front surface of the substrate, each of the plurality of sensor elements being operable to sense radiation projected towards the back surface of the substrate; a radiation-shielding feature disposed over the back surface of the substrate and horizontally disposed between each of the plurality of sensor elements; a dielectric feature disposed between the back surface of the substrate and the radiation-shielding feature; and a metal layer disposed along sidewalls of the dielectric feature.
摘要翻译：本公开提供了一种图像传感器装置和用于制造图像传感器装置的方法。示例性的图像传感器装置包括具有前表面和后表面的基板; 设置在所述基板的前表面处的多个传感器元件，所述多个传感器元件中的每一个可操作以感测朝向所述基板的后表面投射的辐射; 辐射屏蔽特征设置在所述基板的所述背表面上并且水平地设置在所述多个传感器元件中的每一个之间; 设置在基板的背面和辐射屏蔽特征之间的电介质特征; 以及沿着电介质特征的侧壁设置的金属层。

5. 发明授权

US07824998B2 Method of forming a semiconductor capacitor using amorphous carbon 有权
标题翻译：使用无定形碳形成半导体电容器的方法
公开(公告)号：US07824998B2
公开(公告)日：2010-11-02
申请号：US12357661
申请日：2009-01-22
申请人： Yuan-Hung Liu , Ming Chyi Liu , Yeur-Luen Tu , Chi-Hsin Lo , Chia-Shiung Tsai
发明人： Yuan-Hung Liu , Ming Chyi Liu , Yeur-Luen Tu , Chi-Hsin Lo , Chia-Shiung Tsai
IPC分类号： H01L21/20
CPC分类号： H01L21/02274 , H01L21/02115 , H01L21/28273 , H01L21/3086 , H01L21/31116 , H01L21/31144 , H01L21/3146 , H01L21/76816 , H01L21/7682 , H01L21/76885 , H01L21/76897 , H01L27/115 , H01L27/11521 , H01L27/14632 , H01L27/14687 , H01L28/91 , H01L29/42328 , H01L29/7881
摘要： A method includes forming an amorphous carbon layer over a first dielectric layer formed over a substrate, forming a second dielectric layer over the amorphous carbon layer; and forming an opening within the amorphous carbon layer and second dielectric layer by a first etch process to partially expose a top surface of the first dielectric layer. A substantially conformal metal-containing layer is formed over the second dielectric layer and within the opening. The second dielectric layer and a portion of the metal-containing layer are removed. The amorphous carbon layer is removed by an oxygen-containing plasma process to expose a top surface of the first dielectric layer. An insulating layer is formed over the metal-containing layer, and a second metal-containing layer is formed over the insulating layer to form a capacitor.
摘要翻译：一种方法包括在形成在衬底上的第一电介质层上形成无定形碳层，在非晶碳层上形成第二电介质层; 以及通过第一蚀刻工艺在所述非晶碳层和所述第二介电层内形成开口，以部分地暴露所述第一介电层的顶表面。在第二电介质层上并在开口内形成基本上共形的含金属层。去除第二电介质层和一部分含金属层。通过含氧等离子体工艺除去无定形碳层以暴露第一介电层的顶表面。在含金属层的上方形成有绝缘层，在绝缘层上形成第二含金属层，形成电容器。

6. 发明申请

US20090130814A1 SEMICONDUCTOR METHODS 有权
标题翻译：半导体方法
公开(公告)号：US20090130814A1
公开(公告)日：2009-05-21
申请号：US12357661
申请日：2009-01-22
申请人： Yuan-Hung LIU , Ming Chyi Liu , Yeur-Luen Tu , Chi-Hsin Lo , Chai-Shiung Tsai
发明人： Yuan-Hung LIU , Ming Chyi Liu , Yeur-Luen Tu , Chi-Hsin Lo , Chai-Shiung Tsai
IPC分类号： H01L21/20
CPC分类号： H01L21/02274 , H01L21/02115 , H01L21/28273 , H01L21/3086 , H01L21/31116 , H01L21/31144 , H01L21/3146 , H01L21/76816 , H01L21/7682 , H01L21/76885 , H01L21/76897 , H01L27/115 , H01L27/11521 , H01L27/14632 , H01L27/14687 , H01L28/91 , H01L29/42328 , H01L29/7881
摘要： A method includes forming an amorphous carbon layer over a first dielectric layer formed over a substrate, forming a second dielectric layer over the amorphous carbon layer; and forming an opening within the amorphous carbon layer and second dielectric layer by a first etch process to partially expose a top surface of the first dielectric layer. A substantially conformal metal-containing layer is formed over the second dielectric layer and within the opening. The second dielectric layer and a portion of the metal-containing layer are removed. The amorphous carbon layer is removed by an oxygen-containing plasma process to expose a top surface of the first dielectric layer. An insulating layer is formed over the metal-containing layer, and a second metal-containing layer is formed over the insulating layer to form a capacitor.
摘要翻译：一种方法包括在形成在衬底上的第一电介质层上形成无定形碳层，在非晶碳层上形成第二电介质层; 以及通过第一蚀刻工艺在所述非晶碳层和所述第二介电层内形成开口，以部分地暴露所述第一介电层的顶表面。在第二电介质层上并在开口内形成基本上共形的含金属层。去除第二电介质层和一部分含金属层。通过含氧等离子体工艺除去无定形碳层以暴露第一介电层的顶表面。在含金属层的上方形成有绝缘层，在绝缘层上形成第二含金属层，形成电容器。

7. 发明授权

US06653203B1 Thin sidewall multi-step HDP deposition method to achieve completely filled high aspect ratio trenches 有权
标题翻译：薄侧壁多步骤HDP沉积方法实现完全填充的高纵横比沟槽
公开(公告)号：US06653203B1
公开(公告)日：2003-11-25
申请号：US10154285
申请日：2002-05-23
申请人： Tsung-Hsun Huang , Yeur-Luen Tu , Chung Yi Yu
发明人： Tsung-Hsun Huang , Yeur-Luen Tu , Chung Yi Yu
IPC分类号： H01L2176
CPC分类号： H01L21/76224 , H01L21/76232
摘要： A multi-step HDP deposition and sputtering process for void-free filling of high aspect ratio trenches and for trenches having stepped cross-sectional profiles. The method is particularly applicable to filling trenches formed in triply layered substrates comprising a silicon layer, an oxide layer and a nitride layer, wherein the nitride layer has been pulled back from the edge of the trench opening and forms a step. The method allows the void-free filling of such a trench without damaging the nitride layer in the process. Briefly, the essence of the method is the formation of deposited layers on the sidewalls of the trench wherein the first layer is deposited with a high deposition to sputtering ratio (D/S>10) and low bias power to form a thin layer, with no overhang, that is capable of protecting the nitride layer during subsequent deposition and sputtering steps. A subsequent in-situ sputtering step at a lower D/S ratio using oxygen as the sputtering gas maintains a wide trench opening which then allows the complete filling to proceed using argon as the sputtering gas for increased throughput.
摘要翻译：用于无高度填充高纵横比沟槽和具有阶梯形截面轮廓的沟槽的多步HDP沉积和溅射工艺。该方法特别适用于填充形成在包括硅层，氧化物层和氮化物层的三层分层衬底中的沟槽，其中氮化物层已从沟槽开口的边缘拉回并形成一个步骤。该方法允许这种沟槽的无空隙填充而不损害该过程中的氮化物层。简而言之，该方法的本质是在沟槽的侧壁上形成沉积层，其中第一层以高沉积至溅射比（D / S> 10）沉积并具有低偏压功率以形成薄层，其中没有悬垂，在后续沉积和溅射步骤中能够保护氮化物层。使用氧作为溅射气体的较低D / S比率的随后的原位溅射步骤保持宽的沟槽开口，然后允许使用氩气作为溅射气体进行完全填充以提高生产量。

8. 发明授权

US06528366B1 Fabrication methods of vertical metal-insulator-metal (MIM) capacitor for advanced embedded DRAM applications 有权
标题翻译：用于高级嵌入式DRAM应用的垂直金属 - 绝缘体金属（MIM）电容器的制造方法
公开(公告)号：US06528366B1
公开(公告)日：2003-03-04
申请号：US09839964
申请日：2001-04-23
申请人： Yeur-Luen Tu , Dah Lin , Min-Hwa Chi
发明人： Yeur-Luen Tu , Dah Lin , Min-Hwa Chi
IPC分类号： H01L218242
CPC分类号： H01L28/87 , H01L27/10817 , H01L27/10852 , H01L27/10894 , H01L27/10897 , H01L28/91
摘要： Methods for fabricating a vertical metal-insulator-metal (MIM) capacitor are described. The capacitor can be fabricated at any level of metal interconnect, depending upon the desired depth of the capacitor. No global topology variations occur at any interconnect level in these methods. The entire process temperature is limited to be low enough, less than about 450° C., so that the back-end metal interconnect is not degraded or damaged. In one method, the deep capacitor cavity can be formed by etching back-end oxide (i.e. intermetal dielectric) from near the top level of metal interconnect until reaching the via-plug at several lower metal interconnect levels. In another method, metal lines and tungsten plugs are formed in both the logic and memory areas. Then, a selective wet metal etching is performed to remove the stacked tungsten plugs and metal lines for the formation of the capacitor cavity. After the capacitor cavity is formed by either method, the sidewall of the deep cavity is coated sequentially with a conformal conducting film as the bottom electrode and a high-k dielectric, and then filled with a conducting material to form the top electrode.
摘要翻译：描述了用于制造垂直金属 - 绝缘体 - 金属（MIM）电容器的方法。根据电容器的期望深度，可以在任何金属互连级别制造电容器。在这些方法中，任何互连级别都不会发生全局拓扑变化。整个工艺温度被限制为足够低，小于约450℃，使得后端金属互连不会降解或损坏。在一种方法中，深电容器腔可以通过从靠近金属互连顶层的后端蚀刻后端氧化物（即金属间电介质）形成，直到在几个较低的金属互连级别到达通孔。在另一种方法中，在逻辑区和存储区都形成金属线和钨插塞。然后，进行选择性湿式金属蚀刻以去除用于形成电容器腔的堆叠的钨插塞和金属线。在通过任一种方法形成电容器腔之后，依次用适形导电膜作为底部电极和高k电介质涂覆深腔的侧壁，然后填充导电材料以形成顶部电极。

9. 发明授权

US06187486B1 Method of multi-exposure for improving photolithography resolution 有权
标题翻译：用于提高光刻分辨率的多曝光方法
公开(公告)号：US06187486B1
公开(公告)日：2001-02-13
申请号：US09250766
申请日：1999-02-16
申请人： Jun-Cheng Lai , Yeur-Luen Tu , Chine-Gie Lou
发明人： Jun-Cheng Lai , Yeur-Luen Tu , Chine-Gie Lou
IPC分类号： G03F900
CPC分类号： G03F7/70466 , G03F7/2022 , G03F7/203
摘要： A multi-exposure process. By performing the multi-exposure process, the size of the line width can be enlarged or shrunk by the precondition of the fixed pitch. Moreover, the line width can be shrunk to a level even smaller than the resolving power of the stepper or the scanner. Additionally, by using the invention, the exposure energy, the exposure time and the exposure DOF can be fixed while the exposure process is performed. Therefore, the process window is increased and the yield is enhanced. Furthermore, the processing sequence according to the invention is simpler than the conventional photolithography processing sequence, so that the throughput can be increased.
摘要翻译：多曝光过程。通过进行多次曝光处理，可以通过固定间距的前提来扩大或缩小线宽的尺寸。此外，线宽可以缩小到甚至小于步进器或扫描仪的分辨率的水平。此外，通过使用本发明，可以在执行曝光处理时固定曝光能量，曝光时间和曝光DOF。因此，处理窗口增加，产量提高。此外，根据本发明的处理顺序比常规的光刻处理顺序更简单，从而可以提高吞吐量。

10. 发明授权

US6165867A Method to reduce aspect ratio of DRAM peripheral contact 有权
标题翻译：降低DRAM周边接触宽高比的方法
公开(公告)号：US6165867A
公开(公告)日：2000-12-26
申请号：US246919
申请日：1999-02-09
申请人： Yeur-Luen Tu , Cheng-Yuan Hsu , Cheng-Yuan Chang
发明人： Yeur-Luen Tu , Cheng-Yuan Hsu , Cheng-Yuan Chang
IPC分类号： H01L21/768 , H01L21/8242 , H01L21/20
CPC分类号： H01L27/10894 , H01L21/76802 , H01L21/76829
摘要： The present invention provides a method for reducing aspect ratio of DRAM peripheral contact so as to achieving a good contact etching and metal deposition by utilizing conventional equipment. Besides, the present invention provides a stop layer formed by a nitride layer to reduce the volcano effect resulted from the misalignment between stacked contacts. Furthermore, the present invention is capable of etching poly layer and oxide layer in a single step, whereby the height of the peripheral contact is substantially the same as, or lower than, the contact of the storage node of a capacitor. Therefore, the aspect ratio of DRAM peripheral contact can be reduced.
摘要翻译：本发明提供一种降低DRAM周边接触的纵横比的方法，以便通过利用常规设备实现良好的接触蚀刻和金属沉积。此外，本发明提供了由氮化物层形成的停止层，以减少由于堆叠的触点之间的未对准而导致的火山效应。此外，本发明能够在一个步骤中蚀刻多层和氧化物层，由此周边接触的高度与电容器的存储节点的接触基本相同或低于接触。因此，可以减小DRAM周边接触的纵横比。

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