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1. 发明授权

US08890242B2 Closed cell trenched power semiconductor structure 有权
标题翻译：闭孔沟槽功率半导体结构
公开(公告)号：US08890242B2
公开(公告)日：2014-11-18
申请号：US13402945
申请日：2012-02-23
申请人： Yuan-Shun Chang , Kao-Way Tu , Yi-Yun Tsai
发明人： Yuan-Shun Chang , Kao-Way Tu , Yi-Yun Tsai
IPC分类号： H01L29/78
CPC分类号： H01L29/7813 , H01L29/0696 , H01L29/41766 , H01L29/4238 , H01L29/66719 , H01L29/66727 , H01L29/66734
摘要： A closed cell trenched power semiconductor structure is provided. The closed cell trenched power semiconductor structure has a substrate and cells. The cells are arranged on the substrate in an array. Every cell has a body and a trenched gate. The trenched gate surrounds the body. A side wall of the trenched gate facing body has a concave.
摘要翻译：提供了一种闭孔沟槽功率半导体结构。闭孔沟槽功率半导体结构具有基板和单元。电池以阵列布置在基板上。每个细胞都有一个身体和一个沟槽的门。壕沟围绕着身体。沟槽门面对体的侧壁具有凹面。

2. 发明申请

US20110318895A1 FABRICATION METHOD OF TRENCHED POWER MOSFET 有权
标题翻译：激光功率MOSFET的制造方法
公开(公告)号：US20110318895A1
公开(公告)日：2011-12-29
申请号：US13225555
申请日：2011-09-06
申请人： Kou-Way Tu , Hsiu-Wen Hsu , Yi-Yun Tsai , Yuan-Shun Chang
发明人： Kou-Way Tu , Hsiu-Wen Hsu , Yi-Yun Tsai , Yuan-Shun Chang
IPC分类号： H01L21/336
CPC分类号： H01L29/7813 , H01L21/26586 , H01L29/0878 , H01L29/41766 , H01L29/4236 , H01L29/42368 , H01L29/66719 , H01L29/66727 , H01L29/66734
摘要： A fabrication method of a trenched power MOSFET is provided. A pattern layer having a first opening is formed on a substrate. A portion of the substrate is removed, using the pattern layer as a mask, to form a trench in the substrate. A width of the trench is expanded. A gate oxide layer is formed on a surface of the trench. A portion of the gate oxide layer on a bottom of the trench is removed, using the pattern layer as a mask, to form a second opening in the gate oxide layer. The width of the expanded trench is greater than that of the second opening. A thick oxide layer is formed in the second opening. Heavily doped regions are formed beside the thick oxide layer. A gate is formed in the trench. A body layer surrounding the trench is formed. Sources are formed beside the trench.
摘要翻译：提供了一种沟槽功率MOSFET的制造方法。在基板上形成具有第一开口的图案层。使用图案层作为掩模去除衬底的一部分，以在衬底中形成沟槽。沟槽的宽度扩大。栅极氧化层形成在沟槽的表面上。使用图案层作为掩模，去除沟槽底部上的栅极氧化物层的一部分，以在栅极氧化物层中形成第二个开口。扩展沟槽的宽度大于第二开口的宽度。在第二开口中形成厚的氧化物层。在厚氧化物层旁边形成重掺杂区域。在沟槽中形成栅极。形成围绕沟槽的主体层。源头在沟槽旁边形成。

3. 发明申请

US20080224139A1 THIN FILM TRANSISTOR 审中-公开
标题翻译：薄膜晶体管
公开(公告)号：US20080224139A1
公开(公告)日：2008-09-18
申请号：US11775874
申请日：2007-07-11
申请人： Chin-Chuan Lai , Chuan-Yi Wu , Yi-Yun Tsai
发明人： Chin-Chuan Lai , Chuan-Yi Wu , Yi-Yun Tsai
IPC分类号： H01L29/06
CPC分类号： H01L29/78678 , H01L29/66765 , H01L29/78669
摘要： A thin film transistor including a substrate, a gate, a gate insulator layer, a semiconductor layer, an ohmic contact layer, a source and a drain is provided. The gate is disposed on the substrate while the gate insulator layer is disposed on the substrate and covers the gate. The semiconductor layer is disposed on the gate insulator layer above the gate. The semiconductor layer includes an undoped amorphous silicon layer and a first undoped microcrystalline silicon (μc-Si) layer, wherein the first undoped μc-Si layer is disposed on the undoped amorphous silicon layer. The ohmic contact layer is disposed on part of the semiconductor layer and the source and the drain are disposed on the ohmic contact layer. Therefore, the thin film transistor has better quality control and electrical characteristics.
摘要翻译：提供了包括基板，栅极，栅极绝缘体层，半导体层，欧姆接触层，源极和漏极的薄膜晶体管。栅极设置在基板上，同时栅极绝缘体层设置在基板上并覆盖栅极。半导体层设置在栅极上方的栅极绝缘体层上。半导体层包括未掺杂的非晶硅层和第一未掺杂微晶硅（muc-Si）层，其中第一未掺杂的粘硅层设置在未掺杂的非晶硅层上。欧姆接触层设置在半导体层的一部分上，源极和漏极设置在欧姆接触层上。因此，薄膜晶体管具有更好的质量控制和电气特性。

4. 发明授权

US08916930B2 Trenched power semiconductor device and fabrication method thereof 有权
标题翻译：沟槽功率半导体器件及其制造方法
公开(公告)号：US08916930B2
公开(公告)日：2014-12-23
申请号：US13223603
申请日：2011-09-01
申请人： Yuan-Shun Chang , Yi-Yun Tsai , Kao-Way Tu
发明人： Yuan-Shun Chang , Yi-Yun Tsai , Kao-Way Tu
IPC分类号： H01L29/78 , H01L21/336 , H01L29/66 , H01L29/417 , H01L29/40 , H01L29/06 , H01L21/74 , H01L29/423 , H01L29/08
CPC分类号： H01L29/7809 , H01L21/74 , H01L29/0623 , H01L29/0653 , H01L29/0878 , H01L29/0882 , H01L29/407 , H01L29/41766 , H01L29/42368 , H01L29/66719 , H01L29/66727 , H01L29/66734 , H01L29/7811 , H01L29/7812 , H01L29/7813
摘要： A trenched power semiconductor device on a lightly doped substrate is provided. The device has a base, a plurality of trenches including at least a gate trench, a plurality of first heavily doping regions, a body region, a source doped region, a contact window, a second heavily doped region, and a metal layer. The trenches are formed in the base. The first heavily doped regions are beneath the trenches respectively and spaced from the bottom of the respective trench with a lightly doped region. The body region encircles the trenches and is away from the first heavily doped region with a predetermined distance. The source doped region is in an upper portion of the body region. The contact window is adjacent to the edge of the base. The second heavily doped region is below the contact window filled by the metal layer for electrically connecting the second heavily doped region.
摘要翻译：提供了一种在轻掺杂衬底上的沟槽功率半导体器件。该器件具有基极，至少包括栅极沟槽，多个第一重掺杂区域，体区域，源极掺杂区域，接触窗口，第二重掺杂区域和金属层的多个沟槽。沟槽形成在基部。第一重掺杂区域分别在沟槽下方并且与具有轻掺杂区域的相应沟槽的底部间隔开。体区域包围沟槽并且以预定距离远离第一重掺杂区域。源极掺杂区域位于体区的上部。接触窗口与基座的边缘相邻。第二重掺杂区域在由用于电连接第二重掺杂区域的金属层填充的接触窗口的下方。

5. 发明授权

US08735249B2 Trenched power semiconductor device and fabrication method thereof 有权
标题翻译：沟槽功率半导体器件及其制造方法
公开(公告)号：US08735249B2
公开(公告)日：2014-05-27
申请号：US13115951
申请日：2011-05-25
申请人： Yi-Yun Tsai , Yuan-Shun Chang , Kao-Way Tu
发明人： Yi-Yun Tsai , Yuan-Shun Chang , Kao-Way Tu
IPC分类号： H01L21/326
CPC分类号： H01L29/7809 , H01L21/2253 , H01L21/2257 , H01L29/0623 , H01L29/0634 , H01L29/0878 , H01L29/0882 , H01L29/0886 , H01L29/407 , H01L29/41766 , H01L29/4236 , H01L29/42368 , H01L29/66727 , H01L29/66734 , H01L29/7397 , H01L29/7811 , H01L29/7813
摘要： A trenched power semiconductor device on a lightly doped substrate is provided. Firstly, a plurality of trenches including at least a gate trench and a contact window are formed on the lightly doped substrate. Then, at least two trench-bottom heavily doped regions are formed at the bottoms of the trenches. These trench-bottom heavily doped regions are then expanded to connect with each other by using thermal diffusion process so as to form a conductive path. Afterward, the gate structure and the well are formed above the trench-bottom heavily doped regions, and then a conductive structure is formed in the contact window to electrically connect the trench-bottom heavily doped regions to an electrode.
摘要翻译：提供了一种在轻掺杂衬底上的沟槽功率半导体器件。首先，在轻掺杂衬底上形成至少包括栅极沟槽和接触窗口的多个沟槽。然后，在沟槽的底部形成至少两个沟底重掺杂区域。然后通过使用热扩散工艺将这些沟底重掺杂区域扩展以彼此连接，从而形成导电路径。之后，栅极结构和阱形成在沟槽底部重掺杂区域上方，然后在接触窗口中形成导电结构，以将沟槽底部重掺杂区域电连接到电极。

6. 发明授权

US08426275B2 Fabrication method of trenched power MOSFET 有权
标题翻译：沟槽功率MOSFET的制造方法
公开(公告)号：US08426275B2
公开(公告)日：2013-04-23
申请号：US13225555
申请日：2011-09-06
申请人： Kou-Way Tu , Hsiu-Wen Hsu , Yi-Yun Tsai , Yuan-Shun Chang
发明人： Kou-Way Tu , Hsiu-Wen Hsu , Yi-Yun Tsai , Yuan-Shun Chang
IPC分类号： H01L21/336
CPC分类号： H01L29/7813 , H01L21/26586 , H01L29/0878 , H01L29/41766 , H01L29/4236 , H01L29/42368 , H01L29/66719 , H01L29/66727 , H01L29/66734
摘要： A fabrication method of a trenched power MOSFET is provided. A pattern layer having a first opening is formed on a substrate. A portion of the substrate is removed, using the pattern layer as a mask, to form a trench in the substrate. A width of the trench is expanded. A gate oxide layer is formed on a surface of the trench. A portion of the gate oxide layer on a bottom of the trench is removed, using the pattern layer as a mask, to form a second opening in the gate oxide layer. The width of the expanded trench is greater than that of the second opening. A thick oxide layer is formed in the second opening. Heavily doped regions are formed beside the thick oxide layer. A gate is formed in the trench. A body layer surrounding the trench is formed. Sources are formed beside the trench.
摘要翻译：提供了一种沟槽功率MOSFET的制造方法。在基板上形成具有第一开口的图案层。使用图案层作为掩模去除衬底的一部分，以在衬底中形成沟槽。沟槽的宽度扩大。栅极氧化层形成在沟槽的表面上。使用图案层作为掩模，去除沟槽底部上的栅极氧化物层的一部分，以在栅极氧化物层中形成第二个开口。扩展沟槽的宽度大于第二开口的宽度。在第二开口中形成厚的氧化物层。在厚氧化物层旁边形成重掺杂区域。在沟槽中形成栅极。形成围绕沟槽的主体层。源头在沟槽旁边形成。

7. 发明申请

US20130221435A1 CLOSED CELL TRENCHED POWER SEMICONDUCTOR STRUCTURE 有权
标题翻译：封闭式电解槽功率半导体结构
公开(公告)号：US20130221435A1
公开(公告)日：2013-08-29
申请号：US13402945
申请日：2012-02-23
申请人： YUAN-SHUN CHANG , KAO-WAY TU , YI-YUN TSAI
发明人： YUAN-SHUN CHANG , KAO-WAY TU , YI-YUN TSAI
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7813 , H01L29/0696 , H01L29/41766 , H01L29/4238 , H01L29/66719 , H01L29/66727 , H01L29/66734
摘要： A closed cell trenched power semiconductor structure is provided. The closed cell trenched power semiconductor structure has a substrate and cells. The cells are arranged on the substrate in an array. Every cell has a body and a trenched gate. The trenched gate surrounds the body. A side wall of the trenched gate facing body has a concave.
摘要翻译：提供了一种闭孔沟槽功率半导体结构。闭孔沟槽功率半导体结构具有基板和单元。电池以阵列布置在基板上。每个细胞都有一个身体和一个沟槽的门。壕沟围绕着身体。沟槽门面对体的侧壁具有凹面。

8. 发明申请

US20120299091A1 TRENCHED POWER SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF 有权
标题翻译：电力半导体器件及其制造方法
公开(公告)号：US20120299091A1
公开(公告)日：2012-11-29
申请号：US13115951
申请日：2011-05-25
申请人： YI-YUN TSAI , YUAN-SHUN CHANG , KAO-WAY TU
发明人： YI-YUN TSAI , YUAN-SHUN CHANG , KAO-WAY TU
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7809 , H01L21/2253 , H01L21/2257 , H01L29/0623 , H01L29/0634 , H01L29/0878 , H01L29/0882 , H01L29/0886 , H01L29/407 , H01L29/41766 , H01L29/4236 , H01L29/42368 , H01L29/66727 , H01L29/66734 , H01L29/7397 , H01L29/7811 , H01L29/7813
摘要： A trenched power semiconductor device on a lightly doped substrate is provided. Firstly, a plurality of trenches including at least a gate trench and a contact window are formed on the lightly doped substrate. Then, at least two trench-bottom heavily doped regions are formed at the bottoms of the trenches. These trench-bottom heavily doped regions are then expanded to connect with each other by using thermal diffusion process so as to form a conductive path. Afterward, the gate structure and the well are formed above the trench-bottom heavily doped regions, and then a conductive structure is formed in the contact window to electrically connect the trench-bottom heavily doped regions to an electrode.
摘要翻译：提供了一种在轻掺杂衬底上的沟槽功率半导体器件。首先，在轻掺杂衬底上形成至少包括栅极沟槽和接触窗口的多个沟槽。然后，在沟槽的底部形成至少两个沟底重掺杂区域。然后通过使用热扩散工艺将这些沟底重掺杂区域扩展以彼此连接，从而形成导电路径。之后，栅极结构和阱形成在沟槽底部重掺杂区域上方，然后在接触窗口中形成导电结构，以将沟槽底部重掺杂区域电连接到电极。

9. 发明授权

US07858969B2 Organic thin film transistor and method for manufacturing the same 有权
标题翻译：有机薄膜晶体管及其制造方法
公开(公告)号：US07858969B2
公开(公告)日：2010-12-28
申请号：US11737769
申请日：2007-04-20
申请人： Yi-Yun Tsai , Chuan-Yi Wu , Chin-Chuan Lai
发明人： Yi-Yun Tsai , Chuan-Yi Wu , Chin-Chuan Lai
IPC分类号： H01L51/10 , H01L51/40
CPC分类号： H01L51/102 , H01L51/0022 , H01L51/0529 , H01L51/0545
摘要： An organic thin film transistor including a substrate, a gate, a gate insulator, an adhesive layer, a metal nano-particle layer and an organic semiconductor layer is provided. The gate is disposed on the substrate. The gate insulator is disposed on the gate and the substrate. The adhesive layer is disposed on the gate insulator. Besides, the adhesive layer has a hydrophobic surface above the gate and a first hydrophilic surface and a second hydrophilic surface on two sides of the hydrophobic surface. A surface of the metal nano-particle layer is modified by a hydrophilic group, and the metal nano-particle layer is disposed on the first and the second hydrophilic surfaces of the adhesive layer as a source and a drain, respectively. The organic semiconductor layer is disposed on the hydrophobic surface of the adhesive layer and on the metal nano-particle layer.
摘要翻译：提供了包括基板，栅极，栅极绝缘体，粘合层，金属纳米颗粒层和有机半导体层的有机薄膜晶体管。栅极设置在基板上。栅极绝缘体设置在栅极和基板上。粘合剂层设置在栅极绝缘体上。此外，粘合剂层在浇口上方具有疏水表面，在疏水表面的两侧具有第一亲水表面和第二亲水表面。金属纳米粒子层的表面被亲水基团改性，金属纳米粒子层分别作为源极和漏极设置在粘合剂层的第一和第二亲水表面上。有机半导体层设置在粘合层的疏水性表面和金属纳米粒子层上。

10. 发明申请

US20130056821A1 TRENCHED POWER SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF 有权
标题翻译：电力半导体器件及其制造方法
公开(公告)号：US20130056821A1
公开(公告)日：2013-03-07
申请号：US13223603
申请日：2011-09-01
申请人： YUAN-SHUN CHANG , YI-YUN TSAI , KAO-WAY TU
发明人： YUAN-SHUN CHANG , YI-YUN TSAI , KAO-WAY TU
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7809 , H01L21/74 , H01L29/0623 , H01L29/0653 , H01L29/0878 , H01L29/0882 , H01L29/407 , H01L29/41766 , H01L29/42368 , H01L29/66719 , H01L29/66727 , H01L29/66734 , H01L29/7811 , H01L29/7812 , H01L29/7813
摘要： A trenched power semiconductor device on a lightly doped substrate is provided. The device has a base, a plurality of trenches including at least a gate trench, a plurality of first heavily doping regions, a body region, a source doped region, a contact window, a second heavily doped region, and a metal layer. The trenches are formed in the base. The first heavily doped regions are beneath the trenches respectively and spaced from the bottom of the respective trench with a lightly doped region. The body region encircles the trenches and is away from the first heavily doped region with a predetermined distance. The source doped region is in an upper portion of the body region. The contact window is adjacent to the edge of the base. The second heavily doped region is below the contact window filled by the metal layer for electrically connecting the second heavily doped region.
摘要翻译：提供了一种在轻掺杂衬底上的沟槽功率半导体器件。该器件具有基极，至少包括栅极沟槽，多个第一重掺杂区域，体区域，源极掺杂区域，接触窗口，第二重掺杂区域和金属层的多个沟槽。沟槽形成在基部。第一重掺杂区域分别在沟槽下方并且与具有轻掺杂区域的相应沟槽的底部间隔开。体区域包围沟槽并且以预定距离远离第一重掺杂区域。源极掺杂区域位于体区的上部。接触窗口与基座的边缘相邻。第二重掺杂区域在由用于电连接第二重掺杂区域的金属层填充的接触窗口的下方。

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