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1. 发明授权

US08426275B2 Fabrication method of trenched power MOSFET 有权
标题翻译：沟槽功率MOSFET的制造方法
公开(公告)号：US08426275B2
公开(公告)日：2013-04-23
申请号：US13225555
申请日：2011-09-06
申请人： Kou-Way Tu , Hsiu-Wen Hsu , Yi-Yun Tsai , Yuan-Shun Chang
发明人： Kou-Way Tu , Hsiu-Wen Hsu , Yi-Yun Tsai , Yuan-Shun Chang
IPC分类号： H01L21/336
CPC分类号： H01L29/7813 , H01L21/26586 , H01L29/0878 , H01L29/41766 , H01L29/4236 , H01L29/42368 , H01L29/66719 , H01L29/66727 , H01L29/66734
摘要： A fabrication method of a trenched power MOSFET is provided. A pattern layer having a first opening is formed on a substrate. A portion of the substrate is removed, using the pattern layer as a mask, to form a trench in the substrate. A width of the trench is expanded. A gate oxide layer is formed on a surface of the trench. A portion of the gate oxide layer on a bottom of the trench is removed, using the pattern layer as a mask, to form a second opening in the gate oxide layer. The width of the expanded trench is greater than that of the second opening. A thick oxide layer is formed in the second opening. Heavily doped regions are formed beside the thick oxide layer. A gate is formed in the trench. A body layer surrounding the trench is formed. Sources are formed beside the trench.
摘要翻译：提供了一种沟槽功率MOSFET的制造方法。在基板上形成具有第一开口的图案层。使用图案层作为掩模去除衬底的一部分，以在衬底中形成沟槽。沟槽的宽度扩大。栅极氧化层形成在沟槽的表面上。使用图案层作为掩模，去除沟槽底部上的栅极氧化物层的一部分，以在栅极氧化物层中形成第二个开口。扩展沟槽的宽度大于第二开口的宽度。在第二开口中形成厚的氧化物层。在厚氧化物层旁边形成重掺杂区域。在沟槽中形成栅极。形成围绕沟槽的主体层。源头在沟槽旁边形成。

2. 发明申请

US20110318895A1 FABRICATION METHOD OF TRENCHED POWER MOSFET 有权
标题翻译：激光功率MOSFET的制造方法
公开(公告)号：US20110318895A1
公开(公告)日：2011-12-29
申请号：US13225555
申请日：2011-09-06
申请人： Kou-Way Tu , Hsiu-Wen Hsu , Yi-Yun Tsai , Yuan-Shun Chang
发明人： Kou-Way Tu , Hsiu-Wen Hsu , Yi-Yun Tsai , Yuan-Shun Chang
IPC分类号： H01L21/336
CPC分类号： H01L29/7813 , H01L21/26586 , H01L29/0878 , H01L29/41766 , H01L29/4236 , H01L29/42368 , H01L29/66719 , H01L29/66727 , H01L29/66734
摘要： A fabrication method of a trenched power MOSFET is provided. A pattern layer having a first opening is formed on a substrate. A portion of the substrate is removed, using the pattern layer as a mask, to form a trench in the substrate. A width of the trench is expanded. A gate oxide layer is formed on a surface of the trench. A portion of the gate oxide layer on a bottom of the trench is removed, using the pattern layer as a mask, to form a second opening in the gate oxide layer. The width of the expanded trench is greater than that of the second opening. A thick oxide layer is formed in the second opening. Heavily doped regions are formed beside the thick oxide layer. A gate is formed in the trench. A body layer surrounding the trench is formed. Sources are formed beside the trench.
摘要翻译：提供了一种沟槽功率MOSFET的制造方法。在基板上形成具有第一开口的图案层。使用图案层作为掩模去除衬底的一部分，以在衬底中形成沟槽。沟槽的宽度扩大。栅极氧化层形成在沟槽的表面上。使用图案层作为掩模，去除沟槽底部上的栅极氧化物层的一部分，以在栅极氧化物层中形成第二个开口。扩展沟槽的宽度大于第二开口的宽度。在第二开口中形成厚的氧化物层。在厚氧化物层旁边形成重掺杂区域。在沟槽中形成栅极。形成围绕沟槽的主体层。源头在沟槽旁边形成。

3. 发明申请

US20100176444A1 POWER MOSFET AND METHOD OF FABRICATING THE SAME 审中-公开
标题翻译：功率MOSFET及其制造方法
公开(公告)号：US20100176444A1
公开(公告)日：2010-07-15
申请号：US12389360
申请日：2009-02-19
申请人： Kou-Way Tu , Hsiu-Wen Hsu
发明人： Kou-Way Tu , Hsiu-Wen Hsu
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7813 , H01L29/0878 , H01L29/41766 , H01L29/4236 , H01L29/42368 , H01L29/66727 , H01L29/66734
摘要： A power MOSFET including a substrate of first conductivity type, an epitaxial layer of first conductivity type on the substrate, a body layer of second conductivity type in the epitaxial layer, a first insulating layer, a second insulating layer, a first conductive layer and two source regions of first conductivity type is provided. The body layer has a first trench therein. The epitaxial layer has a second trench therein. The second trench is below the first trench, and the width of the second trench is much smaller than that of the first trench. The first insulating layer is at least in the second trench. The first conductive layer is in the first trench. The second insulating layer is at least between the sidewall of the first trench and the first conductive layer. The source regions are disposed in the body layer beside the first trench respectively.
摘要翻译：一种功率MOSFET，包括第一导电类型的衬底，衬底上的第一导电类型的外延层，外延层中的第二导电类型的主体层，第一绝缘层，第二绝缘层，第一导电层和第二导电层提供了第一导电类型的源区。体层在其中具有第一沟槽。外延层中具有第二沟槽。第二沟槽在第一沟槽的下方，第二沟槽的宽度比第一沟槽的宽度小得多。第一绝缘层至少在第二沟槽中。第一导电层在第一沟槽中。第二绝缘层至少在第一沟槽的侧壁和第一导电层之间。源区域分别设置在第一沟槽旁边的体层中。

4. 发明申请

US20150262843A1 PACKAGE STRUCTURE AND PACKAGING METHOD OF WAFER LEVEL CHIP SCALE PACKAGE 有权
标题翻译：滤波器芯片尺寸封装的封装结构和封装方法
公开(公告)号：US20150262843A1
公开(公告)日：2015-09-17
申请号：US14574405
申请日：2014-12-18
申请人： Chih-Cheng Hsieh , Hsiu-Wen Hsu , Chun-Ying Yeh , Chung-Ming Leng
发明人： Chih-Cheng Hsieh , Hsiu-Wen Hsu , Chun-Ying Yeh , Chung-Ming Leng
IPC分类号： H01L21/56 , H01L23/31 , H01L25/18 , H01L23/00 , H01L25/07 , H01L25/00 , H01L21/683 , H01L23/492
CPC分类号： H01L21/56 , H01L21/561 , H01L21/568 , H01L21/6835 , H01L23/3114 , H01L23/4924 , H01L23/49816 , H01L23/5389 , H01L24/19 , H01L24/20 , H01L24/27 , H01L24/32 , H01L24/83 , H01L24/97 , H01L2221/68363 , H01L2221/68372 , H01L2221/68381 , H01L2224/0401 , H01L2224/04105 , H01L2224/12105 , H01L2224/131 , H01L2224/2732 , H01L2224/27332 , H01L2224/29023 , H01L2224/29111 , H01L2224/29139 , H01L2224/29147 , H01L2224/32245 , H01L2224/73267 , H01L2224/83005 , H01L2224/83191 , H01L2224/83851 , H01L2224/92244 , H01L2224/97 , H01L2924/1203 , H01L2924/1305 , H01L2924/13055 , H01L2924/13091 , H01L2924/15153 , H01L2224/83 , H01L2924/014 , H01L2924/00014 , H01L2224/19
摘要： A package structure and a packaging method of wafer level chip scale package are provided. The packaging method includes: providing a carrier, and disposing a plurality of chips on the carrier; forming a plurality of adhesive layers on a surface of the corresponding chips; covering a conductive cover plate, bonding the conductive cover plate with the chips through the adhesive layers, and dividing out a plurality of packaging spaces by the conductive cover plate for disposing the chips respectively; and providing an insulation material to fill the packaging spaces through via holes on the conductive cover plate to form a first insulation structure; finally, removing the carrier.
摘要翻译：提供晶片级芯片级封装的封装结构和封装方法。包装方法包括：提供载体，并在载体上布置多个芯片; 在相应芯片的表面上形成多个粘合剂层; 覆盖导电盖板，通过粘合剂层将导电盖板与芯片接合，并且分别由用于设置芯片的导电盖板分割多个封装空间; 以及提供绝缘材料以通过所述导电盖板上的通孔填充所述包装空间以形成第一绝缘结构; 最后，删除载体。

5. 发明申请

US20060197148A1 TRENCH POWER MOSET AND METHOD FOR FABRICATING THE SAME 审中-公开
标题翻译： TRENCH POWER MOSET AND METHOD FOR FABRISTING THE SAME
公开(公告)号：US20060197148A1
公开(公告)日：2006-09-07
申请号：US11164820
申请日：2005-12-07
申请人： Hsiu-Wen Hsu
发明人： Hsiu-Wen Hsu
IPC分类号： H01L29/76 , H01L29/94
CPC分类号： H01L29/7813 , H01L21/28052 , H01L29/456 , H01L29/4933 , H01L29/66719 , H01L29/66727 , H01L29/66734
摘要： A method for fabricating a trench power MOSFET, comprising an epitaxial layer and a mask layer formed over a substrate, a trench formed in the epitaxial layer and the mask layer, a gate oxide layer formed on the trench, then the mask layer removed, a body well region formed in the epitaxial layer beside the trench, a source region formed in and adjacent to the body well region, and a spacer formed on the sidewalls of the exposed gate layer exposing the source region partially. Masking by spacer, an opening exposing the body well is formed by partially removing the source region and the gate layer. A body region is formed in the body well region under the opening. A silicide layer is formed on the surfaces of the gate layer and the opening.
摘要翻译：一种制造沟槽功率MOSFET的方法，包括在衬底上形成的外延层和掩模层，在外延层中形成的沟槽和掩模层，形成在沟槽上的栅氧化层，然后去除掩模层，形成在沟槽旁边的外延层中的主体区域，形成在主体阱区域中并与身体阱区域相邻的源区域，以及形成在暴露的栅极层的侧壁上的部分地暴露源极区域的间隔物。通过间隔件掩蔽，通过部分去除源极区域和栅极层来形成良好的暴露体的开口。身体区域形成在开口下方的身体区域中。在栅极层和开口的表面上形成硅化物层。

6. 发明授权

US09299592B2 Package structure and packaging method of wafer level chip scale package 有权
标题翻译：晶圆级芯片尺寸封装的封装结构和封装方法
公开(公告)号：US09299592B2
公开(公告)日：2016-03-29
申请号：US14574405
申请日：2014-12-18
申请人： Chih-Cheng Hsieh , Hsiu-Wen Hsu , Chun-Ying Yeh , Chung-Ming Leng
发明人： Chih-Cheng Hsieh , Hsiu-Wen Hsu , Chun-Ying Yeh , Chung-Ming Leng
IPC分类号： H01L23/495 , H01L21/56 , H01L21/683 , H01L23/31 , H01L23/492 , H01L23/00 , H01L23/538
CPC分类号： H01L21/56 , H01L21/561 , H01L21/568 , H01L21/6835 , H01L23/3114 , H01L23/4924 , H01L23/49816 , H01L23/5389 , H01L24/19 , H01L24/20 , H01L24/27 , H01L24/32 , H01L24/83 , H01L24/97 , H01L2221/68363 , H01L2221/68372 , H01L2221/68381 , H01L2224/0401 , H01L2224/04105 , H01L2224/12105 , H01L2224/131 , H01L2224/2732 , H01L2224/27332 , H01L2224/29023 , H01L2224/29111 , H01L2224/29139 , H01L2224/29147 , H01L2224/32245 , H01L2224/73267 , H01L2224/83005 , H01L2224/83191 , H01L2224/83851 , H01L2224/92244 , H01L2224/97 , H01L2924/1203 , H01L2924/1305 , H01L2924/13055 , H01L2924/13091 , H01L2924/15153 , H01L2224/83 , H01L2924/014 , H01L2924/00014 , H01L2224/19
摘要： A package structure and a packaging method of wafer level chip scale package are provided. The packaging method includes: providing a carrier, and disposing a plurality of chips on the carrier; forming a plurality of adhesive layers on a surface of the corresponding chips; covering a conductive cover plate, bonding the conductive cover plate with the chips through the adhesive layers, and dividing out a plurality of packaging spaces by the conductive cover plate for disposing the chips respectively; and providing an insulation material to fill the packaging spaces through via holes on the conductive cover plate to form a first insulation structure; finally, removing the carrier.
摘要翻译：提供晶片级芯片级封装的封装结构和封装方法。包装方法包括：提供载体，并在载体上布置多个芯片; 在相应芯片的表面上形成多个粘合剂层; 覆盖导电盖板，通过粘合剂层将导电盖板与芯片接合，并且分别由用于设置芯片的导电盖板分割多个封装空间; 以及提供绝缘材料以通过所述导电盖板上的通孔填充所述包装空间以形成第一绝缘结构; 最后，删除载体。

7. 发明授权

US08114762B2 Method for manufacturing trench MOSFET device with low gate charge 有权
标题翻译：具有低栅极电荷的沟槽MOSFET器件的制造方法
公开(公告)号：US08114762B2
公开(公告)日：2012-02-14
申请号：US12453281
申请日：2009-05-06
申请人： Hsiu-Wen Hsu , Chun Wei Ni , Kao-Way Tu
发明人： Hsiu-Wen Hsu , Chun Wei Ni , Kao-Way Tu
IPC分类号： H01L21/3205 , H01L21/44
CPC分类号： H01L29/7813 , H01L21/2815 , H01L29/407 , H01L29/42376 , H01L29/4933 , H01L29/66734
摘要： A method for manufacturing trench MOSFET device with low gate charge includes the steps of providing a substrate of first conductivity type; forming an epitaxial layer of first conductivity type on the substrate; forming a body region of second conductivity type in the epitaxial layer, the body region extends downwards from the surface of the epitaxial layer; forming a plurality of trenches in the epitaxial layer, the body region having the trenches formed therethrough; forming a first insulating layer on the body region and on an inner surface of each trench; forming a ploy-silicon spacer on the first insulating layer on an inner side-wall of each trench; filling a dielectric structure in the lower portion of each trench; and filling a ploy-silicon structure on top of the dielectric structure in each trench. Through the trench MOSFET device, the gate capacitance and resistance thereof are reduced so the performance is increased.
摘要翻译：具有低栅极电荷的沟槽MOSFET器件的制造方法包括提供第一导电类型的衬底的步骤; 在衬底上形成第一导电类型的外延层; 在所述外延层中形成第二导电类型的体区，所述体区从所述外延层的表面向下延伸; 在所述外延层中形成多个沟槽，所述主体区域具有穿过其形成的沟槽; 在所述主体区域和每个沟槽的内表面上形成第一绝缘层; 在每个沟槽的内侧壁上的第一绝缘层上形成合金硅衬垫; 在每个沟槽的下部填充电介质结构; 并在每个沟槽中的电介质结构的顶部上填充硅 - 硅结构。通过沟槽MOSFET器件，栅极电容和电阻降低，从而性能提高。

8. 发明申请

US20090236636A1 Closed Cell Array Structure Capable of Decreasing Area of non-well Junction Regions 审中-公开
标题翻译：闭孔单元阵列结构能够减少非井结区的面积
公开(公告)号：US20090236636A1
公开(公告)日：2009-09-24
申请号：US12127805
申请日：2008-05-27
申请人： Hsiu-Wen Hsu
发明人： Hsiu-Wen Hsu
IPC分类号： H01L29/76
CPC分类号： H01L29/7802 , H01L29/0696 , H01L29/1095 , H01L29/4238
摘要： A closed cell array structure capable of decreasing area of non-well junction regions includes a plurality of closed cell units, arranged in a plane, each shaped as a polygon, and a plurality of gate windows, each formed in a corner of a closed cell unit in a gate layer without doped source ion material.
摘要翻译：能够减小非阱结区域面积的闭孔阵列结构包括布置在平面中的多个闭孔单元，每个形成为多边形，以及多个门窗，每个形成在闭孔的角部单元在没有掺杂源离子材料的栅极层。

9. 发明授权

US07592658B2 Method of forming a semiconductor device having a capacitor and a resistor 失效
标题翻译：形成具有电容器和电阻器的半导体器件的方法
公开(公告)号：US07592658B2
公开(公告)日：2009-09-22
申请号：US12011074
申请日：2008-01-24
申请人： Hsiu-Wen Hsu
发明人： Hsiu-Wen Hsu
IPC分类号： H01L27/108 , H01L29/76
CPC分类号： H01L27/0682 , H01L27/0629 , H01L28/20 , H01L28/40 , H01L29/94
摘要： A semiconductor device comprising the following. A structure having: a capacitor; a first resistor; and a second resistor each within at least a portion of an oxide structure and a metal-oxide semiconductor electrode not within at least a portion of the oxide structure. The capacitor comprising: a lower capacitor first doped polysilicon portion; a capacitor interpoly oxide film portion thereover; and an upper capacitor second doped polysilicon portion over at least a portion of the capacitor interpoly oxide film portion. The first resistor comprising a lower first resistor first doped polysilicon portion and an upper first resistor second doped polysilicon portion thereover. The second resistor comprising a lower second resistor first doped polysilicon portion and an upper interpoly oxide film portion thereover. The metal-oxide semiconductor electrode comprising a lower metal-oxide semiconductor first doped polysilicon portion and an upper metal-oxide semiconductor second doped polysilicon portion thereover.
摘要翻译：一种半导体器件，包括以下部件。一种结构，具有：电容器; 第一个电阻; 以及每个在至少一部分氧化物结构内的第二电阻和金属氧化物半导体电极，不在氧化物结构的至少一部分内。所述电容器包括：下电容器第一掺杂多晶硅部分; 其上的电容器叠层氧化物膜部分; 以及在电容器叠层氧化物膜部分的至少一部分上方的上电容器第二掺杂多晶硅部分。第一电阻器包括下部第一电阻器第一掺杂多晶硅部分和其上部第一电阻器第二掺杂多晶硅部分。第二电阻器包括下部第二电阻器第一掺杂多晶硅部分和其上部上部叠层氧化物膜部分。该金属氧化物半导体电极包括下部金属氧化物半导体第一掺杂多晶硅部分和上部金属氧化物半导体第二掺杂多晶硅部分。

10. 发明授权

US07084033B2 Method for fabricating a trench power MOSFET 失效
标题翻译：沟槽功率MOSFET的制造方法
公开(公告)号：US07084033B2
公开(公告)日：2006-08-01
申请号：US10906140
申请日：2005-02-04
申请人： Hsiu-Wen Hsu
发明人： Hsiu-Wen Hsu
IPC分类号： H01L21/336
CPC分类号： H01L29/66727 , H01L29/456 , H01L29/4933 , H01L29/66719 , H01L29/66734
摘要： A method for fabricating a trench power MOSFET, comprising an epitaxial layer and a mask layer formed over a substrate, a trench formed in the epitaxial layer and the mask layer, a gate oxide layer formed on the trench, then the mask layer removed, a body well region formed in the epitaxial layer beside the trench, a source region formed in and adjacent to the body well region, and a spacer formed on the sidewalls of the exposed gate layer exposing the source region partially. Masking by spacer, an opening exposing the body well is formed by partially removing the source region and the gate layer. A body region is formed in the body well region under the opening. A silicide layer is formed on the surfaces of the gate layer and the opening.
摘要翻译：一种制造沟槽功率MOSFET的方法，包括在衬底上形成的外延层和掩模层，在外延层中形成的沟槽和掩模层，形成在沟槽上的栅氧化层，然后去除掩模层，形成在沟槽旁边的外延层中的主体区域，形成在主体阱区域中并与身体阱区域相邻的源区域，以及形成在暴露的栅极层的侧壁上的部分地暴露源极区域的间隔物。通过间隔件掩蔽，通过部分去除源极区域和栅极层来形成良好的暴露体的开口。身体区域形成在开口下方的身体区域中。在栅极层和开口的表面上形成硅化物层。

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