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1. 发明申请

US20110318895A1 FABRICATION METHOD OF TRENCHED POWER MOSFET 有权
标题翻译：激光功率MOSFET的制造方法
公开(公告)号：US20110318895A1
公开(公告)日：2011-12-29
申请号：US13225555
申请日：2011-09-06
申请人： Kou-Way Tu , Hsiu-Wen Hsu , Yi-Yun Tsai , Yuan-Shun Chang
发明人： Kou-Way Tu , Hsiu-Wen Hsu , Yi-Yun Tsai , Yuan-Shun Chang
IPC分类号： H01L21/336
CPC分类号： H01L29/7813 , H01L21/26586 , H01L29/0878 , H01L29/41766 , H01L29/4236 , H01L29/42368 , H01L29/66719 , H01L29/66727 , H01L29/66734
摘要： A fabrication method of a trenched power MOSFET is provided. A pattern layer having a first opening is formed on a substrate. A portion of the substrate is removed, using the pattern layer as a mask, to form a trench in the substrate. A width of the trench is expanded. A gate oxide layer is formed on a surface of the trench. A portion of the gate oxide layer on a bottom of the trench is removed, using the pattern layer as a mask, to form a second opening in the gate oxide layer. The width of the expanded trench is greater than that of the second opening. A thick oxide layer is formed in the second opening. Heavily doped regions are formed beside the thick oxide layer. A gate is formed in the trench. A body layer surrounding the trench is formed. Sources are formed beside the trench.
摘要翻译：提供了一种沟槽功率MOSFET的制造方法。在基板上形成具有第一开口的图案层。使用图案层作为掩模去除衬底的一部分，以在衬底中形成沟槽。沟槽的宽度扩大。栅极氧化层形成在沟槽的表面上。使用图案层作为掩模，去除沟槽底部上的栅极氧化物层的一部分，以在栅极氧化物层中形成第二个开口。扩展沟槽的宽度大于第二开口的宽度。在第二开口中形成厚的氧化物层。在厚氧化物层旁边形成重掺杂区域。在沟槽中形成栅极。形成围绕沟槽的主体层。源头在沟槽旁边形成。

2. 发明授权

US08426275B2 Fabrication method of trenched power MOSFET 有权
标题翻译：沟槽功率MOSFET的制造方法
公开(公告)号：US08426275B2
公开(公告)日：2013-04-23
申请号：US13225555
申请日：2011-09-06
申请人： Kou-Way Tu , Hsiu-Wen Hsu , Yi-Yun Tsai , Yuan-Shun Chang
发明人： Kou-Way Tu , Hsiu-Wen Hsu , Yi-Yun Tsai , Yuan-Shun Chang
IPC分类号： H01L21/336
CPC分类号： H01L29/7813 , H01L21/26586 , H01L29/0878 , H01L29/41766 , H01L29/4236 , H01L29/42368 , H01L29/66719 , H01L29/66727 , H01L29/66734
摘要： A fabrication method of a trenched power MOSFET is provided. A pattern layer having a first opening is formed on a substrate. A portion of the substrate is removed, using the pattern layer as a mask, to form a trench in the substrate. A width of the trench is expanded. A gate oxide layer is formed on a surface of the trench. A portion of the gate oxide layer on a bottom of the trench is removed, using the pattern layer as a mask, to form a second opening in the gate oxide layer. The width of the expanded trench is greater than that of the second opening. A thick oxide layer is formed in the second opening. Heavily doped regions are formed beside the thick oxide layer. A gate is formed in the trench. A body layer surrounding the trench is formed. Sources are formed beside the trench.
摘要翻译：提供了一种沟槽功率MOSFET的制造方法。在基板上形成具有第一开口的图案层。使用图案层作为掩模去除衬底的一部分，以在衬底中形成沟槽。沟槽的宽度扩大。栅极氧化层形成在沟槽的表面上。使用图案层作为掩模，去除沟槽底部上的栅极氧化物层的一部分，以在栅极氧化物层中形成第二个开口。扩展沟槽的宽度大于第二开口的宽度。在第二开口中形成厚的氧化物层。在厚氧化物层旁边形成重掺杂区域。在沟槽中形成栅极。形成围绕沟槽的主体层。源头在沟槽旁边形成。

3. 发明申请

US20100176444A1 POWER MOSFET AND METHOD OF FABRICATING THE SAME 审中-公开
标题翻译：功率MOSFET及其制造方法
公开(公告)号：US20100176444A1
公开(公告)日：2010-07-15
申请号：US12389360
申请日：2009-02-19
申请人： Kou-Way Tu , Hsiu-Wen Hsu
发明人： Kou-Way Tu , Hsiu-Wen Hsu
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7813 , H01L29/0878 , H01L29/41766 , H01L29/4236 , H01L29/42368 , H01L29/66727 , H01L29/66734
摘要： A power MOSFET including a substrate of first conductivity type, an epitaxial layer of first conductivity type on the substrate, a body layer of second conductivity type in the epitaxial layer, a first insulating layer, a second insulating layer, a first conductive layer and two source regions of first conductivity type is provided. The body layer has a first trench therein. The epitaxial layer has a second trench therein. The second trench is below the first trench, and the width of the second trench is much smaller than that of the first trench. The first insulating layer is at least in the second trench. The first conductive layer is in the first trench. The second insulating layer is at least between the sidewall of the first trench and the first conductive layer. The source regions are disposed in the body layer beside the first trench respectively.
摘要翻译：一种功率MOSFET，包括第一导电类型的衬底，衬底上的第一导电类型的外延层，外延层中的第二导电类型的主体层，第一绝缘层，第二绝缘层，第一导电层和第二导电层提供了第一导电类型的源区。体层在其中具有第一沟槽。外延层中具有第二沟槽。第二沟槽在第一沟槽的下方，第二沟槽的宽度比第一沟槽的宽度小得多。第一绝缘层至少在第二沟槽中。第一导电层在第一沟槽中。第二绝缘层至少在第一沟槽的侧壁和第一导电层之间。源区域分别设置在第一沟槽旁边的体层中。

4. 发明申请

US20100289074A1 SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20100289074A1
公开(公告)日：2010-11-18
申请号：US12506264
申请日：2009-07-21
申请人： Kou-Way Tu
发明人： Kou-Way Tu
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7802 , H01L29/0634 , H01L29/0657 , H01L29/0834 , H01L29/0869 , H01L29/0886 , H01L29/1095 , H01L29/41766 , H01L29/66348 , H01L29/66727 , H01L29/66734 , H01L29/7397 , H01L29/7813
摘要： A semiconductor device is provided. The semiconductor device includes a semiconductor substrate, at least a doped region, an electrical contact layer and a metal oxide semiconductor cell. The semiconductor substrate includes opposing first and second surfaces and at least a trench extending from the second surface into interior portion thereof. The doped region is located in the semiconductor substrate under the bottom of the trench. The dopant concentration of the doped region is higher than that of the semiconductor substrate. The electrical contact layer is located on the second surface of the semiconductor substrate and connects to the doped region. The metal oxide semiconductor cell is located on the semiconductor substrate adjacent the first surface thereof.
摘要翻译：提供半导体器件。半导体器件包括半导体衬底，至少掺杂区域，电接触层和金属氧化物半导体单元。半导体衬底包括相对的第一表面和第二表面以及从第二表面延伸到其内部的至少一个沟槽。掺杂区域位于沟槽底部下方的半导体衬底中。掺杂区域的掺杂剂浓度高于半导体衬底的掺杂浓度。电接触层位于半导体衬底的第二表面上并与掺杂区连接。金属氧化物半导体单元位于与其第一表面相邻的半导体衬底上。

5. 发明授权

US06917117B2 Lower the on-resistance in protection circuit of rechargeable battery by using flip-chip technology 失效
标题翻译：使用倒装芯片技术降低可充电电池保护电路的导通电阻
公开(公告)号：US06917117B2
公开(公告)日：2005-07-12
申请号：US10625855
申请日：2003-07-23
申请人： Feng-Tso Chien , Chii-Wen Chen , Kou-Way Tu , Zheng-Feng Lin
发明人： Feng-Tso Chien , Chii-Wen Chen , Kou-Way Tu , Zheng-Feng Lin
IPC分类号： H01L21/60 , H01L23/48
CPC分类号： H01L24/81 , H01L2224/05568 , H01L2224/05573 , H01L2224/056 , H01L2224/16 , H01L2224/81801 , H01L2224/83192 , H01L2924/01005 , H01L2924/01006 , H01L2924/01023 , H01L2924/01033 , H01L2924/0105 , H01L2924/01082 , H01L2924/014 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/19041 , H01L2924/00 , H01L2924/00014
摘要： A method of mounting flip-chip for lowering the on-resistance of power transistor in the protection circuit of rechargeable battery, which comprises a power field effect transistor and a protection IC, has the following steps: first, serially connect drain metal contacts of two transistors to form a chip cell during fabrication of wafer; then, use welding torch to point weld the metal wire on contact of each chip cell, so that the source and gate contacts will form welding metal bumps respectively; cut the wafer to form bare chip cells of two serially connected gate electrodes; stain said chip cell with tin so that said welding metal bumps on contacts are attached with tin balls; apply plastic material to positioned points of printed circuit board; use flip-chip technology to make drain of a bare chip cell face upward, so that said tin balls are aligned with the positioned points of printed circuit board; finally, passing through an oven for heating and pressuring, so that said tin balls will fuse and said plastic material will be hardened and soldered together with contacts on the printed circuit board. Thus, it is possible to omit steps of wire welding and packing for power transistor, not only lower the cost and reduce the volume of the protection circuit but also lower the on-resistance of power field effect transistor.
摘要翻译：包括功率场效应晶体管和保护IC的可再充电电池的保护电路中功率晶体管导通电阻降低的方法包括以下步骤：首先串联两个漏极金属触点晶体管在晶片制造期间形成芯片单元; 然后用焊炬点焊金属线接触每个芯片单元，使源极和栅极接触分别形成焊接金属凸块; 切割晶片以形成两个串联连接的栅电极的裸芯片单元; 用锡污染所述芯片单元，使得触点上的所述焊接金属凸块与锡球相连; 将塑料材料应用于印刷电路板的定位点; 使用倒装芯片技术使裸芯片单元的漏极面向上，使得所述锡球与印刷电路板的定位点对准; 最后，通过烘箱进行加热和加压，使得所述锡球将熔化，并且所述塑料材料将被硬化并与印刷电路板上的触点一起焊接。因此，可以省略功率晶体管的焊丝和包装的步骤，不仅降低了成本并降低了保护电路的体积，而且降低了功率场效应晶体管的导通电阻。

6. 发明授权

US08247868B2 Power MOSFET and fabricating method thereof 有权
标题翻译：功率MOSFET及其制造方法
公开(公告)号：US08247868B2
公开(公告)日：2012-08-21
申请号：US12403893
申请日：2009-03-13
申请人： Kou-Way Tu
发明人： Kou-Way Tu
IPC分类号： H01L29/78 , H01L29/66
CPC分类号： H01L29/7813 , H01L29/0623 , H01L29/0634 , H01L29/4236 , H01L29/66719 , H01L29/66734
摘要： A power MOSFET is disclosed. In the power MOSFET, an epitaxial layer doped with dopants of a first conduction type is formed on a substrate. A first trench extends downward from a first region of the top surface of the epitaxial layer, and a second trench extends downward from the bottom of the first trench. The width of the second trench is smaller than that of the first trench. The first well is located adjacent to the bottom of the first trench and the bottom of the second trench, and is doped with dopants of a second conduction type. The second well extends downward from a second region of the top surface and is doped with dopants of the second conduction type. The first well and the second well are separated. A source region doped with dopants of the first conduction type is formed in the second well.
摘要翻译：公开了功率MOSFET。在功率MOSFET中，在衬底上形成掺杂有第一导电类型的掺杂剂的外延层。第一沟槽从外延层的顶表面的第一区域向下延伸，并且第二沟槽从第一沟槽的底部向下延伸。第二沟槽的宽度小于第一沟槽的宽度。第一阱位于第一沟槽的底部和第二沟槽的底部附近，并掺杂有第二导电类型的掺杂剂。第二阱从顶表面的第二区域向下延伸并且掺杂有第二导电类型的掺杂剂。第一口井和第二口井分开。在第二阱中形成掺杂有第一导电类型的掺杂剂的源区。

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