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1. 发明授权

US07660469B2 Image decoding apparatus and image decoding method 有权
标题翻译：图像解码装置和图像解码方法
公开(公告)号：US07660469B2
公开(公告)日：2010-02-09
申请号：US10577769
申请日：2004-10-26
申请人： Yoichi Katayama
发明人： Yoichi Katayama
IPC分类号： G06K9/36
CPC分类号： H04N19/44 , H04N19/127 , H04N19/63 , H04N19/91
摘要： An image decoding apparatus includes an analyzing section and an image decoding section. The analyzing section determines a process quantity of a coded image data to each of a plurality of image decoding processes within a unit process time based on a parameter of the coded image data, prior to the plurality of image decoding processes. The image decoding section carries out each of the plurality of image decoding processes to the coded image data for the determined process quantity such that a decoded image data is generated from the coded image data.
摘要翻译：图像解码装置包括分析部分和图像解码部分。分析部在多个图像解码处理之前，基于编码图像数据的参数，在单位处理时间内的多个图像解码处理中的每一个图像数据的处理量。图像解码部分对所确定的处理量的编码图像数据执行多个图像解码处理中的每一个，使得从编码图像数据生成解码图像数据。

2. 发明申请

US20060277131A1 HYBRID FINANCING STRUCTURE FOR RENEWABLE POWER FACILITIES 审中-公开
标题翻译：可再生能源设施的混合融资结构
公开(公告)号：US20060277131A1
公开(公告)日：2006-12-07
申请号：US11421733
申请日：2006-06-01
申请人： Richard Bacon , Charles Cardall , Yoichi Katayama
发明人： Richard Bacon , Charles Cardall , Yoichi Katayama
IPC分类号： G06Q40/00
CPC分类号： G06Q40/02 , G06Q40/00 , Y04S10/58
摘要： The present invention provides a hybrid financing structure for renewable power facilities that reduces the cost of power supplied from such facilities. In a preferred embodiment, the hybrid financing structure combines low cost financing, e.g., bonds, available to governmental entities, e.g., municipalities, with tax benefits and similar benefits available to private entities to lower the cost of power supplied from a renewable power facility. The renewable power facility is owned and operated by a private company to take advantage of tax benefits and similar benefits available to the private sector. To further reduce costs, a municipality prepays for power supplied from the facility using low cost financing, e.g., tax exempt bonds, available to the municipality. The hybrid financing structure also includes a production tracking account that reduces risk associated with prepayment of fluctuating renewable power supplies for the municipality by notionally tracking actual power production against predicted levels.
摘要翻译：本发明提供了一种用于可再生电力设施的混合融资结构，其降低了从这些设施供应的电力的成本。在优选实施例中，混合融资结构将低成本融资（例如，政府实体（例如城市）可获得的债券）与私人实体可获得的税收优惠和类似利益相结合，以降低从可再生电力设施供应的电力成本。可再生能源设施由私营公司拥有并经营，以利用私营部门的税收优惠和类似福利。为了进一步降低成本，市政府可以使用低成本融资（例如免税债券）从该设施提供的电力预付给市政府。混合型融资结构还包括一个生产跟踪账户，通过将实际电力生产与预测水平进行对比，可以降低与市政府波动的可再生电力供应相关的风险。

3. 发明申请

US20050278401A1 Apparatus and method for motion vector search and post filtering with reduced hardware resources 审中-公开
标题翻译：用于减少硬件资源的运动矢量搜索和后置滤波的装置和方法
公开(公告)号：US20050278401A1
公开(公告)日：2005-12-15
申请号：US11148177
申请日：2005-06-09
申请人： Yoichi Katayama
发明人： Yoichi Katayama
IPC分类号： H04N19/50 , G06F7/00 , G06T5/00 , G06T7/20 , H04N19/42 , H04N19/503 , H04N19/51 , H04N19/60 , H04N19/61 , H04N19/80 , H04N19/86
CPC分类号： H04N19/43 , G06T5/002 , G06T7/238 , G06T2200/28 , G06T2207/10016
摘要： An image processing circuit is composed of: a plurality of registers retaining pixel data, respectively; a plurality of absolute difference calculator/adders; at least one selective multiplier, each disposed between associated one of said registers and associated one of said absolute difference calculator/adders; and an adder calculating a sum of outputs of said absolute difference calculator/adders. Each of said at least one selective multiplier is designed to perform selected one of first and second operations; said first operation involving transferring pixel data retained in said associated one of said registers as it is to said associated one of said absolute difference calculator/adders, and said second operation outputting a product of a predetermined coefficient and said pixel data retained in said associated one of said registers onto an input of said associated one of said absolute difference calculator/adders. Each of said absolute difference calculator/adders is designed to perform selected one of absolute difference calculation and adding operation, said absolute difference calculation involving calculating an absolute difference of pixel data inputted thereto, and said adding operation involving calculating a sum of said pixel data inputted thereto.
摘要翻译：图像处理电路分别由多个保持像素数据的寄存器组成，多个绝对差分计算器/加法器; 至少一个选择性乘法器，每个选择性乘法器分别设置在相关联的所述寄存器之一和所述绝对差分计算器/ 以及计算所述绝对差计算器/加法器的输出之和的加法器。所述至少一个选择乘法器中的每一个被设计为执行第一和第二操作中的所选择的一个; 所述第一操作涉及将保存在所述相关联的一个所述寄存器中的像素数据原样传送到所述相关联的所述绝对差计算器/加法器之一，并且所述第二操作输出预定系数的乘积和保留在所述相关联的一个中的所述像素数据所述寄存器的所述绝对差值计算器/加法器的所述相关联的一个的输入端。所述绝对差计算器/加法器中的每一个被设计为执行绝对差计算和相加操作中的所选择的一个，所述绝对差计算涉及计算输入到其中的像素数据的绝对差，并且所述相加操作涉及计算所输入的所述像素数据的和到此。

4. 发明授权

US06420979B1 Method for compressing and decompressing image signals and apparatus for compressing and decompressing image signals 有权
标题翻译：用于压缩和解压缩图像信号的方法以及用于压缩和解压缩图像信号的装置
公开(公告)号：US06420979B1
公开(公告)日：2002-07-16
申请号：US09713828
申请日：2000-11-15
申请人： Yoichi Katayama
发明人： Yoichi Katayama
IPC分类号： H03M734
CPC分类号： G06F17/147 , G06T9/007
摘要： A method is provided for achieving high-speed 2N-2N DCT and 2−2N−1−2N DCT in a miniaturized circuit. An 8-8 DCT is performed by using multiplexers, registers, adding circuits, subtracting circuits, adding/subtracting circuits, fixed coefficient multiplying circuits, AND circuits or a like. A 2-4-8 DCT is performed by using a part of the circuit for performing the 8-8 DCT by switching operations of multiplexers, adding/subtracting circuits, fixed coefficient multiplying circuits, registers between operations for the 8-8 DCT and for the 2-4-8 DCT.
摘要翻译：提供了一种用于在小型化电路中实现高速2N-2N DCT和2-2N-1-2N DCT的方法。通过使用多路复用器，寄存器，加法电路，减法电路，加/减电路固定系数乘法电路，AND电路等。通过使用用于通过多路复用器，加法/减法电路，固定系数乘法电路的切换操作执行8-8 DCT的电路的一部分来执行2-4-8 DCT，用于8-8DCT的操作和用于 2-4-8 DCT。

5. 发明授权

US5831882A Orthogonal transformation processing device 失效
标题翻译：正交变换处理装置
公开(公告)号：US5831882A
公开(公告)日：1998-11-03
申请号：US611943
申请日：1996-03-07
申请人： Yoichi Katayama
发明人： Yoichi Katayama
IPC分类号： G06F17/14
CPC分类号： G06F17/14
摘要： When adding a first data and a second data, a selection circuit outputs the first data and a constant number 1 to a multiplication circuit and the second data to an addition circuit. When subtracting the second data from the first data, the selection circuit outputs the first data and a constant number -1 to the multiplication circuit and the second data to the addition circuit. When multiplying the first data by the second data, the selection circuit outputs the first data and the second data to the multiplication circuit and a constant number zero to the addition circuit. The multiplication circuit multiplies two input values and outputs a result to the addition circuit. The addition circuit adds the two input values.
摘要翻译：当添加第一数据和第二数据时，选择电路将第一数据和常数1输出到乘法电路，并将第二数据输出到加法电路。当从第一数据中减去第二数据时，选择电路向乘法电路输出第一数据和常数-1，并将第二数据输出到加法电路。当将第一数据乘以第二数据时，选择电路将第一数据和第二数据输出到乘法电路，并将常数零输出到加法电路。乘法电路将两个输入值相乘，并将结果输出到加法电路。加法电路添加两个输入值。

6. 发明授权

US5376973A Image memory device 失效
标题翻译：图像存储设备
公开(公告)号：US5376973A
公开(公告)日：1994-12-27
申请号：US186129
申请日：1994-01-25
申请人： Yoichi Katayama , Hidenobu Harasaki
发明人： Yoichi Katayama , Hidenobu Harasaki
IPC分类号： G09G5/36 , G06T1/60 , G06T3/40 , G06T13/00 , G06T13/80 , H04N5/262 , H04N5/907 , H04N7/01
CPC分类号： G06T3/4007 , H04N5/907 , H04N7/0105 , H04N7/0135
摘要： An image memory device wherein data necessary for interpolation is read out simply and successively from a frame memory at a time without requiring a complicated timing control circuit to allow interpolation processing to be performed at a high speed. Image data are temporarily stored into a plurality of parallel frame memories having an interleave construction. Conversion addresses for the frame memories are generated based on different conversion rules from a plurality of address decoders and applied in parallel at a time to the frame memories so that data at neighboring points of a coordinate position for an object of interpolation are outputted at a time from the frame memories. The neighboring point data are inputted in parallel at a time, or pipeline inputted, to an interpolation calculation circuit so that coefficients are generated from individual pipelines. Product sum calculation is performed for the coefficients and the neighboring point data.
摘要翻译：一种图像存储装置，其中一次从帧存储器中简单地和连续地读出插值所必需的数据，而不需要复杂的定时控制电路以允许高速执行插值处理。图像数据被临时存储到具有交织结构的多个并行帧存储器中。基于来自多个地址解码器的不同的转换规则生成帧存储器的转换地址，并且一次并行地应用于帧存储器，从而一次输出用于插值对象的坐标位置的相邻点处的数据从帧记忆。将相邻点数据一次输入或流水线输入到插值计算电路，从而从各个管线生成系数。对系数和相邻点数据执行产品和计算。

7. 发明授权

US07876830B2 Video encoder and decoder for achieving inter-and intra-frame predictions with reduced memory resource 有权
标题翻译：视频编码器和解码器，用于实现帧内和帧内预测，并减少内存资源
公开(公告)号：US07876830B2
公开(公告)日：2011-01-25
申请号：US11376197
申请日：2006-03-16
申请人： Yoichi Katayama , Hisashi Takamura
发明人： Yoichi Katayama , Hisashi Takamura
IPC分类号： H04N7/12
CPC分类号： H04N19/433 , H04N19/426 , H04N19/593 , H04N19/61
摘要： A video encoder is composed of a DC/AC prediction unit performing DC/AC prediction, a motion vector prediction unit performing motion vector prediction, and a memory. The memory is accessible from both of the DC/AC prediction unit and the motion vector prediction unit.
摘要翻译：视频编码器由执行DC / AC预测的DC / AC预测单元，执行运动矢量预测的运动矢量预测单元和存储器组成。存储器可从DC / AC预测单元和运动矢量预测单元两者接近。

8. 发明申请

US20090094303A1 FILTER OPERATION UNIT AND MOTION-COMPENSATING DEVICE 有权
标题翻译：过滤器操作单元和运动补偿装置
公开(公告)号：US20090094303A1
公开(公告)日：2009-04-09
申请号：US12237198
申请日：2008-09-24
申请人： Yoichi KATAYAMA
发明人： Yoichi KATAYAMA
IPC分类号： G06F17/10
CPC分类号： G06F17/147 , G06F7/5338 , G06F7/5443 , H03H17/0225 , H03H2218/10 , H04N19/43 , H04N19/436 , H04N19/61 , H04N19/82
摘要： A filter operation unit that performs a multiply-accumulate operation on input data and a filter coefficient group including a plurality of coefficients using Booth's algorithm. The filter operation unit includes: at least two filter multiplier units that multiply the input data and a difference between adjacent filter coefficients in a filter coefficient group to obtain multiplication results; and an adder that adds the multiplication results of the multiplier units adjacent to each other. The filter multiplier units each include: a partial product generation unit that repeatedly generates a partial product according to Booth's algorithm; and an adder that cumulatively adds the partial products generated by the partial product generation unit.
摘要翻译：滤波器操作单元，其使用布斯算法对输入数据执行乘法运算和包括多个系数的滤波器系数组。滤波器操作单元包括：至少两个滤波器乘法器单元，其将输入数据乘以滤波器系数组中的相邻滤波器系数之间的差，以获得乘法结果; 以及将乘法器单元的相乘结果相加的加法器。滤波器乘法器单元各自包括：部分乘积生成单元，其根据布斯算法反复产生部分乘积; 以及累加部分乘积生成部生成的部分乘积的加法器。

9. 发明申请

US20060209960A1 Video encoder and decoder for achieving inter-and intra-frame predictions with reduced memory resource 有权
标题翻译：视频编码器和解码器，用于实现帧内和帧内预测，并减少内存资源
公开(公告)号：US20060209960A1
公开(公告)日：2006-09-21
申请号：US11376197
申请日：2006-03-16
申请人： Yoichi Katayama , Hisashi Takamura
发明人： Yoichi Katayama , Hisashi Takamura
IPC分类号： H04N11/02
CPC分类号： H04N19/433 , H04N19/426 , H04N19/593 , H04N19/61
摘要： A video encoder is composed of a DC/AC prediction unit performing DC/AC prediction, a motion vector prediction unit performing motion vector prediction, and a memory. The memory is accessible from both of the DC/AC prediction unit and the motion vector prediction unit.
摘要翻译：视频编码器由执行DC / AC预测的DC / AC预测单元，执行运动矢量预测的运动矢量预测单元和存储器组成。存储器可从DC / AC预测单元和运动矢量预测单元两者接近。

10. 发明授权

US5566279A Method of and apparatus for reading out digital image data from three-dimensional memory 失效
标题翻译：从三维存储器读出数字图像数据的方法和装置
公开(公告)号：US5566279A
公开(公告)日：1996-10-15
申请号：US243851
申请日：1994-05-17
申请人： Yoichi Katayama
发明人： Yoichi Katayama
IPC分类号： G06T15/06 , G06T15/40 , G06T15/00
CPC分类号： G06T15/06 , G06T15/40
摘要： A three-dimensional image processing apparatus and method wherein a three-dimensional digital image in a three-dimensional memory is cut and read out to perform image processing. Addresses of a two-dimensional digital differential analyzer are first calculated by ray tracing in a direction of a vector on one plane of a three plane coordinate system of a three-dimensional coordinate system, and then data of voxel columns, arranged perpendicularly to the one plane coordinate system in the three-dimensional space along straight lines perpendicular to the ray at the addresses, are read out in units of a column for the individual voxel columns from the three-dimensional memory. A pair of three-dimensional memories are utilized, and a writing operation of a three-dimensional digital image into one of the three-dimensional memories and a reading out operation of the voxel columns from the other three-dimensional memory are performed simultaneously in a parallel relationship.
摘要翻译：一种三维图像处理装置和方法，其中切割并读出三维存储器中的三维数字图像以执行图像处理。首先通过在三维坐标系的三平面坐标系的一个平面上的矢量的方向上的光线跟踪来计算二维数字差分分析器的地址，然后垂直于该三维坐标系排列的体素列的数据以垂直于地址处的射线的直线在三维空间中的平面坐标系以三维存储器中的各个体素列的列为单位读出。使用一对三维存储器，并且在三维存储器中的一个三维存储器中的三维数字图像的写入操作和来自另一个三维存储器的体素列的读出操作在平行关系

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