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1. 发明授权

US08884266B2 Thin film transistor using a carbon nanotube as a channel and a display device including the same 有权
标题翻译：使用碳纳米管作为通道的薄膜晶体管和包括该纳米管的显示装置
公开(公告)号：US08884266B2
公开(公告)日：2014-11-11
申请号：US13495045
申请日：2012-06-13
申请人： Sang Ho Park , Young Ki Shin , Yoon Ho Khang , Joo Hyung Lee , Hyung Woo Lee , Seung Hun Hong
发明人： Sang Ho Park , Young Ki Shin , Yoon Ho Khang , Joo Hyung Lee , Hyung Woo Lee , Seung Hun Hong
IPC分类号： H01L29/06 , H01L51/05 , H01L27/32 , H01L51/00
CPC分类号： H01L27/283 , B82Y10/00 , H01L27/3274 , H01L51/0048 , H01L51/0558
摘要： A thin film transistor includes a gate electrode configured to receive a control voltage, a source electrode insulated from the gate electrode, and configured to receive an input voltage, a drain electrode insulated from the gate electrode, and configured to receive an output voltage, at least two carbon nanotube patterns formed in a channel region between the source electrode and the drain electrode, wherein the carbon nanotube patterns are separated from each other, and at least one floating electrode connecting the two carbon nanotube patterns to each other.
摘要翻译：薄膜晶体管包括被配置为接收控制电压的栅电极，与栅电极绝缘的源电极，并且被配置为接收输入电压，与栅电极绝缘的漏电极，并且被配置为接收输出电压，在源电极和漏电极之间的沟道区域中形成的至少两个碳纳米管图案，其中碳纳米管图案彼此分离，以及至少一个将两个碳纳米管图案彼此连接的浮动电极。

2. 发明申请

US20130119345A1 THIN FILM TRANSISTOR AND A DISPLAY DEVICE INCLUDING THE SAME 有权
标题翻译：薄膜晶体管和包括其的显示器件
公开(公告)号：US20130119345A1
公开(公告)日：2013-05-16
申请号：US13495045
申请日：2012-06-13
申请人： Sang Ho PARK , Young Ki SHIN , Yoon Ho KHANG , Joo Hyung LEE , Hyung Woo LEE , Seung Hun HONG
发明人： Sang Ho PARK , Young Ki SHIN , Yoon Ho KHANG , Joo Hyung LEE , Hyung Woo LEE , Seung Hun HONG
IPC分类号： H01L29/775 , H01L33/04
CPC分类号： H01L27/283 , B82Y10/00 , H01L27/3274 , H01L51/0048 , H01L51/0558
摘要： A thin film transistor includes a gate electrode configured to receive a control voltage, a source electrode insulated from the gate electrode, and configured to receive an input voltage, a drain electrode insulated from the gate electrode, and configured to receive an output voltage, at least two carbon nanotube patterns formed in a channel region between the source electrode and the drain electrode, wherein the carbon nanotube patterns are separated from each other, and at least one floating electrode connecting the two carbon nanotube patterns to each other.
摘要翻译：薄膜晶体管包括被配置为接收控制电压的栅电极，与栅电极绝缘的源电极，并且被配置为接收输入电压，与栅电极绝缘的漏电极，并且被配置为接收输出电压，在源电极和漏电极之间的沟道区域中形成的至少两个碳纳米管图案，其中碳纳米管图案彼此分离，以及至少一个将两个碳纳米管图案彼此连接的浮动电极。

3. 发明申请

US20130098869A1 Method for Forming Minute Pattern and Method for Forming Minute Pattern Mask 有权
标题翻译：形成分钟图案的方法和形成分钟图案掩模的方法
公开(公告)号：US20130098869A1
公开(公告)日：2013-04-25
申请号：US13431516
申请日：2012-03-27
申请人： Se-Hwan Yu , Ji Seon Lee , Yoon Ho Khang , Kahp Yang Suh , Hyoung Sick Um , Jae Jun Chae , Sung Hun Lee
发明人： Se-Hwan Yu , Ji Seon Lee , Yoon Ho Khang , Kahp Yang Suh , Hyoung Sick Um , Jae Jun Chae , Sung Hun Lee
IPC分类号： B44C1/22
CPC分类号： G03F7/0002 , B82Y10/00 , B82Y40/00
摘要： A method for forming a minute pattern mask includes forming an etching target layer on a substrate. A convex pattern including a plurality of convex parts is formed on the etching target layer. A resin composition is coated on the convex pattern to form a resin layer including a first region neighboring the convex part and a second region positioned between the neighboring convex parts. The resin layer is ashed or etched to form the plurality of first resin patterns. The plurality of first resin patterns is processed to form a minute pattern mask including a plurality of second resin patterns. The etching target layer is etched using the plurality of second resin patterns as an etch mask to form a minute pattern.
摘要翻译：形成微图案掩模的方法包括在基板上形成蚀刻目标层。在蚀刻目标层上形成包括多个凸部的凸形图案。将树脂组合物涂覆在凸形图案上以形成包括邻近凸部的第一区域和位于相邻凸部之间的第二区域的树脂层。树脂层被灰化或蚀刻以形成多个第一树脂图案。处理多个第一树脂图案以形成包括多个第二树脂图案的微小图案掩模。使用多个第二树脂图案作为蚀刻掩模蚀刻蚀刻目标层以形成微小图案。

4. 发明申请

US20130032794A1 THIN FILM TRANSISTOR AND THIN FILM TRANSISTOR ARRAY PANEL 有权
标题翻译：薄膜晶体管和薄膜晶体管阵列
公开(公告)号：US20130032794A1
公开(公告)日：2013-02-07
申请号：US13367076
申请日：2012-02-06
申请人： Yong Su LEE , Yoon Ho KHANG , Se Hwan YU , Chong Sup CHANG
发明人： Yong Su LEE , Yoon Ho KHANG , Se Hwan YU , Chong Sup CHANG
IPC分类号： H01L29/786 , B82Y99/00
CPC分类号： H01L29/458 , H01L29/45 , H01L29/78618 , H01L29/7869
摘要： Provided is a thin film transistor and thin film transistor panel array. The thin film transistor includes: a substrate; a gate electrode disposed on the substrate; a semiconductor layer disposed on the substrate and partially overlapping with the gate electrode; a source electrode and a drain electrode spaced apart from each other with respect to a channel region of the semiconductor layer; an insulating layer disposed between the gate electrode and the semiconductor layer; and a barrier layer disposed between the semiconductor layer and the source electrode and between the semiconductor layer and the drain electrode, in which the barrier layer comprises graphene. An ohmic contact is provided based on the type of material used for the semiconductor layer.
摘要翻译：提供了一种薄膜晶体管和薄膜晶体管阵列阵列。薄膜晶体管包括：基板; 设置在所述基板上的栅电极; 设置在所述基板上并与所述栅电极部分重叠的半导体层; 源电极和漏电极相对于半导体层的沟道区彼此分开; 设置在所述栅电极和所述半导体层之间的绝缘层; 以及设置在所述半导体层和所述源电极之间以及所述半导体层和所述漏电极之间的阻挡层，其中所述阻挡层包括石墨烯。基于用于半导体层的材料的类型提供欧姆接触。

5. 发明授权

US07728172B2 Precursor, thin layer prepared including the precursor, method of preparing the thin layer and phase-change memory device 有权
标题翻译：前体，薄层制备包括前体，制备薄层的方法和相变存储器件
公开(公告)号：US07728172B2
公开(公告)日：2010-06-01
申请号：US12078751
申请日：2008-04-04
申请人： Jung-Hyun Lee , Yoon-Ho Khang
发明人： Jung-Hyun Lee , Yoon-Ho Khang
IPC分类号： C07C395/00 , C23C16/00
CPC分类号： C23C16/305 , C07F7/10 , H01L27/2436 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/1616
摘要： A Te precursor containing Te, a 15-group compound (for example, N) and/or a 14-group compound (for example, Si), a method of preparing the Te precursor, a Te-containing chalcogenide thin layer including the Te precursor, a method of preparing the thin layer; and a phase-change memory device. The Te precursor may be deposited at lower temperatures for forming a Te-containing chalcogenide thin layer doped with a 15-group compound (for example, N) and/or a 14-group compound (for example, Si). For example, the Te precursor may employ plasma enhanced chemical vapor deposition (PECVD) or plasma enhanced atomic layer deposition (PEALD) at lower deposition temperatures. The GST phase-change layer doped with a 15-group compound (for example, N) and/or a 14-group compound (for example, Si) formed by employing the Te precursor may have a decreased reset current, and thus when a memory device including the same is employed, its integration may be possible, and operation with higher capacity and/or higher speed may be possible.
摘要翻译：含有Te，15组化合物（例如N）和/或14组化合物（例如Si）的Te前体，制备Te前体的方法，含Te的硫族化物薄层，包括Te 前体，制备薄层的方法; 和相变存储器件。可以在较低温度下沉积Te前体以形成掺杂有15族化合物（例如N）和/或14-基团化合物（例如Si）的含Te的硫族化物薄层。例如，Te前体可以在较低的沉积温度下使用等离子体增强化学气相沉积（PECVD）或等离子体增强原子层沉积（PEALD）。掺杂有通过使用Te前体形成的15族化合物（例如N）和/或14族化合物（例如Si）的GST相变层可能具有降低的复位电流，因此当使用包括其的存储器件，其集成是可能的，并且具有更高容量和/或更高速度的操作可能是可能的。

6. 发明授权

US07635628B2 Nonvolatile memory device and method of manufacturing the same 有权
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：US07635628B2
公开(公告)日：2009-12-22
申请号：US11354011
申请日：2006-02-15
申请人： Yoon-ho Khang , Eun-hye Lee , Myoung-jae Lee , Sun-ae Seo , Seung-Eon Ahn
发明人： Yoon-ho Khang , Eun-hye Lee , Myoung-jae Lee , Sun-ae Seo , Seung-Eon Ahn
IPC分类号： H01L21/336
CPC分类号： H01L21/28282 , B82Y10/00 , G11C16/0416 , H01L29/51 , H01L29/513 , H01L29/792
摘要： The nonvolatile memory device includes a semiconductor substrate on which a source, a drain, and a channel region are formed, a tunneling oxide film formed on the channel region, a floating gate formed of a transition metal oxide (TMO) on the tunneling oxide, a blocking oxide film formed on the floating gate, a gate electrode formed on the blocking oxide film.
摘要翻译：非易失性存储器件包括其上形成有源极，漏极和沟道区的半导体衬底，在沟道区上形成的隧道氧化膜，在隧道氧化物上由过渡金属氧化物（TMO）形成的浮动栅，形成在浮置栅极上的阻挡氧化膜，形成在阻挡氧化膜上的栅电极。

7. 发明授权

US07592618B2 Nanoparticle electroluminescence and method of manufacturing the same 有权
标题翻译：纳米颗粒电致发光及其制造方法
公开(公告)号：US07592618B2
公开(公告)日：2009-09-22
申请号：US11356122
申请日：2006-02-17
申请人： Yoon-ho Khang , Eun-hyu Lee , Kyo-yeol Lee , Joo-hyun Lee , Seong-il Im
发明人： Yoon-ho Khang , Eun-hyu Lee , Kyo-yeol Lee , Joo-hyun Lee , Seong-il Im
IPC分类号： H01L33/00
CPC分类号： H05B33/14 , C09K11/02 , C09K11/59 , C09K11/592 , Y10S977/95 , Y10S977/952 , Y10T428/259
摘要： The nanoparticle electroluminescence device includes: a front electrode formed of a transparent conductive material; a rear electrode formed of a conductive material; and an emitting layer interposed between the front electrode and the rear electrode and comprising a plurality of nanoparticles having a core/shell structure comprising a core formed of silicon and a shell formed of silicon oxide or silicon nitride on the surface of the core.
摘要翻译：纳米颗粒电致发光器件包括：由透明导电材料形成的前电极; 由导电材料形成的后电极; 以及插入在前电极和后电极之间的发射层，并且包括多个纳米颗粒，其具有包含由硅形成的芯和在芯的表面上由氧化硅或氮化硅形成的壳的芯/壳结构。

8. 发明授权

US07572662B2 Method of fabricating phase change RAM including a fullerene layer 有权
标题翻译：制造包含富勒烯层的相变RAM的方法
公开(公告)号：US07572662B2
公开(公告)日：2009-08-11
申请号：US11604824
申请日：2006-11-28
申请人： Yoon-ho Khang , Sang-Mock Lee , Jin-seo Noh , Woong-Chul Shin
发明人： Yoon-ho Khang , Sang-Mock Lee , Jin-seo Noh , Woong-Chul Shin
IPC分类号： H01L21/00 , H01L21/06 , H01L21/4763 , H01L21/44
CPC分类号： G11C13/025 , B82Y10/00 , G11C11/5678 , G11C13/0004 , G11C2213/35 , G11C2213/79 , H01L27/2436 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/1675 , Y10S977/734
摘要： A method of fabricating a phase change RAM (PRAM) having a fullerene layer is provided. The method of fabricating the PRAM may include forming a bottom electrode, forming an interlayer dielectric film covering the bottom electrode, and forming a bottom electrode contact hole exposing a portion of the bottom electrode in the interlayer dielectric film, forming a bottom electrode contact plug by filling the bottom electrode contact hole with a plug material, forming a fullerene layer on a region including at least an upper surface of the bottom electrode contact plug and sequentially stacking a phase change layer and an upper electrode on the fullerene layer. The method may further include forming a switching device on a substrate and a bottom electrode connected to the switching device, forming an interlayer dielectric film covering the bottom electrode and forming a bottom electrode contact hole exposing a portion of the bottom electrode in the interlayer dielectric film.
摘要翻译：提供了制造具有富勒烯层的相变RAM（PRAM）的方法。制造PRAM的方法可以包括形成底部电极，形成覆盖底部电极的层间电介质膜，以及形成暴露层间电介质膜中底部电极的一部分的底部电极接触孔，形成底部电极接触插塞用塞子材料填充底部电极接触孔，在包括底部电极接触塞的至少上表面的区域上形成富勒烯层，并且在富勒烯层上依次层叠相变层和上部电极。该方法还可以包括在基板上形成开关器件和连接到开关器件的底部电极，形成覆盖底部电极的层间电介质膜，并形成露出层间绝缘膜中底部电极的一部分的底部电极接触孔。

9. 发明申请

US20090173927A1 Storage node, phase change memory device and methods of manufacturing and operating the same 审中-公开
标题翻译：存储节点，相变存储器件及其制造和操作方法
公开(公告)号：US20090173927A1
公开(公告)日：2009-07-09
申请号：US12232961
申请日：2008-09-26
申请人： Cheol-kyu Kim , Min-ho Kwon , Yoon-ho Khang , Youn-seon Kang , Tae-yon Lee , Sung Heo , Ki-bum Kim , Sung-wook Nam , Dong-bok Lee
发明人： Cheol-kyu Kim , Min-ho Kwon , Yoon-ho Khang , Youn-seon Kang , Tae-yon Lee , Sung Heo , Ki-bum Kim , Sung-wook Nam , Dong-bok Lee
IPC分类号： H01L29/02 , H01L21/44
CPC分类号： H01L45/126 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/16
摘要： Provided are a storage node, phase change memory device and methods of manufacturing and operating the same. The storage node may include an electrode, a phase change layer, and an anti-diffusion layer between the electrode and the phase change layer and including a silicide compound. The phase change memory device may include the storage node and a switching device connected to the storage node.
摘要翻译：提供了一种存储节点，相变存储器件及其制造和操作方法。存储节点可以包括在电极和相变层之间的电极，相变层和抗扩散层，并且包括硅化物化合物。相变存储器件可以包括存储节点和连接到存储节点的交换设备。

10. 发明授权

US07504280B2 Nonvolatile memory device and method of manufacturing the same 有权
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：US07504280B2
公开(公告)日：2009-03-17
申请号：US11357221
申请日：2006-02-21
申请人： Yoon-ho Khang , Kyo-yeol Lee , Eun-hye Lee , Joo-hyun Lee
发明人： Yoon-ho Khang , Kyo-yeol Lee , Eun-hye Lee , Joo-hyun Lee
IPC分类号： H01L51/40
CPC分类号： H01L21/28273 , B82Y10/00 , H01L29/42332 , H01L29/7881 , Y10S438/962
摘要： Provided is a nonvolatile memory device and a method of manufacturing the same. The nonvolatile memory device includes a semiconductor substrate on which a source, a drain, and a channel region are formed, a tunneling oxide film formed on the channel region, a floating gate formed of a fullerene material on the tunneling oxide, a blocking oxide film formed on the floating gate, and a gate electrode formed on the blocking oxide film.
摘要翻译：提供一种非易失性存储器件及其制造方法。非易失性存储器件包括其上形成有源极，漏极和沟道区的半导体衬底，在沟道区上形成的隧道氧化物膜，在隧道氧化物上由富勒烯材料形成的浮动栅，阻挡氧化膜形成在浮置栅极上，以及形成在该阻挡氧化膜上的栅电极。

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