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    • 3. 发明申请
    • SOLID-STATE IMAGING DEVICE AND CAMERA SYSTEM
    • 固态成像装置和摄像机系统
    • US20120307120A1
    • 2012-12-06
    • US13474287
    • 2012-05-17
    • Masamichi ItoTsuyoshi HaraYoshiaki Inada
    • Masamichi ItoTsuyoshi HaraYoshiaki Inada
    • H04N5/335H01L27/146
    • H04N5/37455H04N5/341H04N5/3456H04N5/347H04N5/357H04N5/374H04N5/3741H04N5/3745H04N5/3765H04N5/378
    • A solid-state imaging device includes a pixel array with unit pixels each having a photoelectric conversion device arranged in a matrix. Column signal lines are wired with respect to one column in the pixel arrangement and pixels are regularly connected to the column signal lines in accordance with rows in which pixels are positioned. A pixel signal reading unit has a column processing unit that reads pixel signals in units of plural pixels from the pixel array and performs column processing to read signals on a column basis, wherein the pixel signal reading unit includes a column input unit which can connect one or plural column signal lines arranged at a corresponding column to an input of one column processing unit through plural capacitors connected in parallel The column input unit has switches which can change a connection state between capacitors and column signal lines corresponding to the column.
    • 固态成像装置包括具有单位像素的像素阵列,每个像素阵列具有以矩阵形式布置的光电转换装置。 列信号线相对于像素布置中的一列被布线,并且像素根据像素所在的行而规则地连接到列信号线。 像素信号读取单元具有列处理单元,其从像素阵列读取以多个像素为单位的像素信号,并执行列处理以逐列读取信号,其中像素信号读取单元包括列输入单元,其可以连接一个 或多列列信号线,通过并联连接的多个电容器配置在与列列处理单元的输入相对应的列上。列输入单元具有可改变电容器与列对应的列信号线之间的连接状态的开关。
    • 4. 发明授权
    • Capacitive load drive circuit
    • 电容负载驱动电路
    • US06380690B1
    • 2002-04-30
    • US09878102
    • 2001-06-08
    • Yoshiaki Inada
    • Yoshiaki Inada
    • H05B3702
    • H02M3/07
    • In a capacitive load drive circuit, in order to bring an output terminal used for supplying a drive voltage to a non-selected capacitive load into a high impedance state and in order to prevent the capacitive load from being unnecessarily driven by electric charge flowing to parasitic diodes at the output terminal, such as to prevent a non-selected electroluminescence element from turning on, a synchronizing unit generates second selecting signals by synchronizing first selecting signals to a clock signal constituting a basis of a drive signal of a common inverter for generating drive voltage to a common output terminal of plural electroluminescence elements, a drive signal generating unit brings individual output terminals into the high impedance state based thereon and a timing thereof is synchronized to a timing at which a potential difference between two poles of the non-selected electroluminescence element is nullified.
    • 在电容性负载驱动电路中,为了使用于将驱动电压提供给未选择的容性负载的输出端子变为高阻抗状态,并且为了防止电容性负载被电荷流向寄生的电荷不必要地驱动 在输出端子处的二极管,以防止未选择的电致发光元件导通,同步单元通过将第一选择信号与构成用于产生驱动的公共逆变器的驱动信号的基础的时钟信号同步来产生第二选择信号 电压到多个电致发光元件的公共输出端子,驱动信号生成单元使各个输出端子基于其高阻抗状态,并且其定时与未选择的电致发光的两极之间的电位差同步 元素无效。
    • 6. 发明授权
    • Solid-state imaging device and camera system
    • 固态成像装置和相机系统
    • US08854520B2
    • 2014-10-07
    • US13474287
    • 2012-05-17
    • Masamichi ItoTsuyoshi HaraYoshiaki Inada
    • Masamichi ItoTsuyoshi HaraYoshiaki Inada
    • H04N5/335H04N5/378H04N5/347H04N5/357H04N5/341H04N5/3745H04N5/376H04N5/345
    • H04N5/37455H04N5/341H04N5/3456H04N5/347H04N5/357H04N5/374H04N5/3741H04N5/3745H04N5/3765H04N5/378
    • A solid-state imaging device includes a pixel array with unit pixels each having a photoelectric conversion device arranged in a matrix. Column signal lines are wired with respect to one column in the pixel arrangement and pixels are regularly connected to the column signal lines in accordance with rows in which pixels are positioned. A pixel signal reading unit has a column processing unit that reads pixel signals in units of plural pixels from the pixel array and performs column processing to read signals on a column basis, wherein the pixel signal reading unit includes a column input unit which can connect one or plural column signal lines arranged at a corresponding column to an input of one column processing unit through plural capacitors connected in parallel The column input unit has switches which can change a connection state between capacitors and column signal lines corresponding to the column.
    • 固态成像装置包括具有单位像素的像素阵列,每个像素阵列具有以矩阵形式布置的光电转换装置。 列信号线相对于像素布置中的一列被布线,并且像素根据像素所在的行而规则地连接到列信号线。 像素信号读取单元具有列处理单元,其从像素阵列读取以多个像素为单位的像素信号,并执行列处理以逐列读取信号,其中像素信号读取单元包括列输入单元,其可以连接一个 或多列列信号线,通过并联连接的多个电容器配置在与列列处理单元的输入相对应的列上。列输入单元具有可改变电容器与列对应的列信号线之间的连接状态的开关。
    • 10. 发明授权
    • A/D converter, solid-state image pickup device and driving method of the same, and electronic apparatus
    • A / D转换器,固态摄像装置及其驱动方法以及电子装置
    • US09369644B2
    • 2016-06-14
    • US14002020
    • 2012-03-23
    • Kenichi HiguchiYoshiaki Inada
    • Kenichi HiguchiYoshiaki Inada
    • H04N3/14H04N5/347H03M1/14H04N5/378H04N5/335H03M1/12H03M1/56
    • H04N5/347H03M1/123H03M1/145H03M1/56H04N5/378
    • The present technology relates to an A/D converter, a solid-state image pickup device and a method of driving the same, and an electronic apparatus which are capable of reducing power consumption while reducing a circuit size. A comparator compares a reference voltage with an input voltage, the reference voltage having a ramp waveform whose voltage value varies with time, a lower-bit storage element holds a count value in a predetermined count pattern, based on an output signal from the comparator, a Gray code binary conversion circuit converts the count value in the count pattern held by the lower-bit storage element into binary data, and a storing operation control circuit supplies a pulse signal corresponding to the binary data obtained by conversion in the Gray code binary conversion circuit to a lower-bit U/D CNT. The present technology is applicable to, for example, an image sensor storing a count value in a storage element with use of a Gray code or a phase shift code as a clock signal.
    • 本技术涉及A / D转换器,固态图像拾取装置及其驱动方法,以及能够在减小电路尺寸的同时降低功耗的电子设备。 比较器将参考电压与输入电压进行比较,参考电压具有电压值随时间变化的斜坡波形,低位存储元件基于来自比较器的输出信号保持预定计数模式中的计数值, 格雷码二进制转换电路将由低位存储元件保持的计数模式中的计数值转换为二进制数据,并且存储操作控制电路提供与通过格雷码二进制转换中的转换获得的二进制数据相对应的脉冲信号 电路到低位U / D CNT。 本技术适用于例如使用格雷码或相移码作为时钟信号存储存储元件中的计数值的图像传感器。