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1. 发明申请

US20110217990A1 MOBILE COMMUNICATION TERMINAL, BASE STATION, WARNING SYSTEM AND METHOD FOR CONTROLLING MOBILE COMMUNICATION TERMINAL 审中-公开
标题翻译：移动通信终端，基站，用于控制移动通信终端的警告系统和方法
公开(公告)号：US20110217990A1
公开(公告)日：2011-09-08
申请号：US13128751
申请日：2009-11-16
申请人： Hideaki Tetsuhashi , Takuya Murakami , Yoshiaki Okuyama
发明人： Hideaki Tetsuhashi , Takuya Murakami , Yoshiaki Okuyama
IPC分类号： H04W4/02 , H04W64/00
CPC分类号： G08G1/207 , G08G1/096741 , G08G1/096775 , H04W4/029
摘要： An object of the present invention is to provide a mobile communication terminal, a base station, a warning system and a method for controlling the mobile communication terminal which are able to inform user of a situation corresponding to a predetermined area when user exists in the predetermined area.In order to realize the object, the mobile communication terminal according to the present invention includes a setter which sets the mobile communication terminal to be in a state able to receive a predetermined wireless signal in the case that the mobile communication terminal moves to a predetermined communication area and receives a specific control signal from a destined base station, and an informer which informs user of the mobile communication terminal that the predetermined wireless signal is received in the case that the mobile communication terminal receives the predetermined wireless signal in the state able to receive the predetermined wireless signal.
摘要翻译：本发明的目的是提供一种移动通信终端，基站，警告系统和控制移动通信终端的方法，当用户存在于预定的时间内时，能够通知用户与预定区域相对应的情况区。为了实现该目的，根据本发明的移动通信终端包括：设置器，其在移动通信终端移动到预定通信的情况下将移动通信终端设置为能够接收预定无线信号的状态并且从目的地基站接收特定控制信号，以及在移动通信终端以能够接收的状态接收到预定无线信号的情况下通知移动通信终端的用户接收到预定无线信号的通知者预定的无线信号。

2. 发明申请

US20100180331A1 COMMUNICATION TERMINAL DEVICE, RULE DISTRIBUTION DEVICE, AND PROGRAM 审中-公开
标题翻译：通信终端设备，规则分发设备和程序
公开(公告)号：US20100180331A1
公开(公告)日：2010-07-15
申请号：US12295216
申请日：2007-02-09
申请人： Takuya Murakami , Masashi Itoh , Yoshiaki Okuyama
发明人： Takuya Murakami , Masashi Itoh , Yoshiaki Okuyama
IPC分类号： G06F21/20 , H04L12/66 , G06F13/00 , H04L12/28
CPC分类号： H04L63/0263 , G06F21/55 , H04L63/1441
摘要： A communication terminal device (10) that is provided with a communication device (11) that connects to a network and a firewall (12) that functions in accordance with firewall rules further includes: a rule storage unit (14) that holds network identification information and firewall rules in association with each other for each network; a rule storage control unit (15) that stores in the rule storage unit (14) firewall rules that are received from rule-distributing device (20) and the identification information of a network that is the object of application in association with each other; and a firewall control unit (13) that detects network identification information to both monitor and, when the identification information is newly detected or changes, reads from the rule storage unit (14) firewall rules that are placed in association with the identification information that has been detected or that has changed to set or update in the firewall (12).
摘要翻译：设置有连接到网络的通信设备（11）和根据防火墙规则工作的防火墙（12）的通信终端设备（10）还包括：规则存储单元（14），其保存网络标识信息和每个网络相互关联的防火墙规则; 在规则存储单元（14）中存储从规则分发装置（20）接收的防火墙规则和作为应用对象的网络的识别信息的规则存储控制单元（15）。以及防火墙控制单元（13），其检测网络识别信息以进行监视，并且当新检测到或更改了识别信息时，从规则存储单元（14）读取与已经具有的标识信息相关联的防火墙规则已被检测到或已更改为在防火墙中设置或更新（12）。

3. 发明授权

US07321517B2 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US07321517B2
公开(公告)日：2008-01-22
申请号：US11260200
申请日：2005-10-28
申请人： Hitoshi Ikeda , Kaoru Mori , Yoshiaki Okuyama
发明人： Hitoshi Ikeda , Kaoru Mori , Yoshiaki Okuyama
IPC分类号： G11C7/00
CPC分类号： G11C29/02 , G11C11/401 , G11C29/025
摘要： An equalizing circuit connects a pair of bit lines to each other in response to the activation of an equalizing control signal and connects the pair of bit lines to a precharge voltage line. An equalizing control circuit deactivates the equalizing control signal in response to the activation of a first timing signal. A word line driving circuit activates one of word lines in response to the activation of a second timing signal. A first signal generating circuit of a timing control circuit generates the first timing signal. A second signal generating circuit of the timing control circuit activates the second timing signal after the deactivation of the equalizing control signal accompanying the activation of the first timing signal. A delay control circuit of the second signal generating circuit delays an activation timing of the second timing signal in a test mode from that in a normal mode.
摘要翻译：均衡电路响应于均衡控制信号的激活而将一对位线彼此连接，并将一对位线连接到预充电电压线。均衡控制电路响应于第一定时信号的激活而去激活均衡控制信号。字线驱动电路响应于第二定时信号的激活而激活字线之一。定时控制电路的第一信号发生电路产生第一定时信号。定时控制电路的第二信号发生电路在伴随第一定时信号的激活的均衡控制信号的去激活之后激活第二定时信号。第二信号发生电路的延迟控制电路将测试模式中的第二定时信号的激活定时与正常模式中的激活定时相比较。

4. 发明授权

US07203114B2 Semiconductor memory which performs the refresh operation internally and automatically without refresh commands from the exterior 有权
标题翻译：半导体存储器，其在内部和自动地执行刷新操作，而没有来自外部的刷新命令
公开(公告)号：US07203114B2
公开(公告)日：2007-04-10
申请号：US11260201
申请日：2005-10-28
申请人： Yoshiaki Okuyama
发明人： Yoshiaki Okuyama
IPC分类号： G11C7/00
CPC分类号： G11C11/40603 , G11C11/406 , G11C11/40626 , G11C2211/4061 , G11C2211/4067
摘要： An oscillator generates a refresh request signal periodically. A storing circuit changes a stored value by a predetermined value in response to the refresh request signal and returns the stored value by one in response to a refresh operation. A store control circuit, when a state detecting circuit detects a change of an operational state of a semiconductor memory, increases or decreases the predetermined value which the storing circuit uses. A refresh decision circuit outputs refresh signals of a number corresponding to the stored value until the stored value returns to an initial value. This makes it possible to change the frequency of the refresh operations according to a change of the operational state without changing an oscillation cycle of the oscillator. Without unnecessary oscillation of the oscillator, it is possible to decrease a standby current of the semiconductor memory.
摘要翻译：振荡器周期性地产生刷新请求信号。存储电路响应于刷新请求信号而将存储值改变预定值，并且响应刷新操作将存储值返回一个。存储控制电路当状态检测电路检测出半导体存储器的工作状态的变化时，增加或减少存储电路使用的预定值。刷新判定电路输出对应于存储值的数字的刷新信号，直到存储的值返回到初始值。这使得可以在不改变振荡器的振荡周期的情况下根据操作状态的变化来改变刷新操作的频率。没有振荡器的不必要的振荡，可以减少半导体存储器的待机电流。

5. 发明授权

US07114025B2 Semiconductor memory having test function for refresh operation 有权
标题翻译：半导体存储器具有刷新操作的测试功能
公开(公告)号：US07114025B2
公开(公告)日：2006-09-26
申请号：US10689486
申请日：2003-10-21
申请人： Tatsuya Kanda , Akihiro Funyu , Takahiko Sato , Yoshiaki Okuyama , Jun Ohno , Hitoshi Ikeda
发明人： Tatsuya Kanda , Akihiro Funyu , Takahiko Sato , Yoshiaki Okuyama , Jun Ohno , Hitoshi Ikeda
IPC分类号： G11C7/00 , G06F13/00
CPC分类号： G11C11/406 , G11C11/401 , G11C11/40603 , G11C29/02 , G11C29/028 , G11C29/50 , G11C29/50016
摘要： A semiconductor memory includes a refresh timer and an arbiter for determining the order of precedence between an access operation and a refresh operation, in order to automatically perform refresh operations inside the memory. A detecting circuit operates in a test mode and outputs a detection signal indicating that the refresh operation is yet to be performed, when a new internal refresh request occurs before the refresh operation is performed. For example, the detection signal is output when the interval of access requests is short and no refresh operation can be inserted between the access operations. That is, in the semiconductor memory in which refresh operations are performed automatically, it is possible to evaluate the minimum interval of supplying access requests. As a result, the evaluation time can be reduced with a reduction in the development period of the semiconductor memory.
摘要翻译：半导体存储器包括刷新定时器和用于确定访问操作和刷新操作之间的优先级顺序的仲裁器，以便自动执行存储器内的刷新操作。检测电路在测试模式下工作，并且在执行刷新操作之前发生新的内部刷新请求时，输出指示刷新操作尚未执行的检测信号。例如，当访问请求的间隔短并且在访问操作之间不能插入刷新操作时，输出检测信号。也就是说，在自动执行刷新操作的半导体存储器中，可以评估提供访问请求的最小间隔。结果，随着半导体存储器的显影周期的减少，可以减少评估时间。

6. 发明授权

US07050353B2 Semiconductor memory having burst transfer function 有权
标题翻译：具有突发传送功能的半导体存储器
公开(公告)号：US07050353B2
公开(公告)日：2006-05-23
申请号：US10994630
申请日：2004-11-23
申请人： Shinya Fujioka , Yoshiaki Okuyama
发明人： Shinya Fujioka , Yoshiaki Okuyama
IPC分类号： G11C8/00
CPC分类号： G11C7/1051 , G11C7/1063 , G11C11/406 , G11C11/40615 , G11C11/4076
摘要： A refresh control circuit generates a refresh request in a predetermined cycle. A first burst control circuit outputs a predetermined number of strobe signals in accordance with an access command. A burst access operation is executed by an access command. A data input/output circuit successively inputs data to be transferred to a memory cell array or successively outputs data supplied from the memory cell array, in synchronization with the strobe signals. An arbiter determines which of a refresh operation or a burst access operation is to be executed first, when the refresh request and the access command conflict with each other. Therefore, the refresh operation and burst access operation can be sequentially executed without being overlapped. As a result, read data can be outputted at a high speed, and write data can be inputted at a high speed. That is, the data transfer rate can be improved.
摘要翻译：刷新控制电路以预定的周期生成刷新请求。第一突发控制电路根据访问命令输出预定数量的选通信号。通过访问命令执行突发存取操作。数据输入/输出电路连续输入要传送到存储单元阵列的数据，或者与选通信号同步地连续输出从存储单元阵列提供的数据。当刷新请求和访问命令彼此冲突时，仲裁器确定首先执行刷新操作或突发存取操作中的哪一个。因此，可以顺序地执行刷新操作和突发存取操作而不重叠。结果，可以高速地输出读取数据，并且可以高速地输入写入数据。也就是说，可以提高数据传输速率。

7. 发明申请

US20050185493A1 Data transfer method and system 失效
标题翻译：数据传输方式和系统
公开(公告)号：US20050185493A1
公开(公告)日：2005-08-25
申请号：US11113181
申请日：2005-04-25
申请人： Shinya Fujioka , Kotoku Sato , Hitoshi Ikeda , Yoshiaki Okuyama , Jun Ohno
发明人： Shinya Fujioka , Kotoku Sato , Hitoshi Ikeda , Yoshiaki Okuyama , Jun Ohno
IPC分类号： G06F12/00 , G06F12/08 , G06F13/16 , G11C7/10 , G11C8/00 , G11C11/406 , G11C16/12 , G11C16/34
CPC分类号： G06F12/0804 , G06F2212/2022 , G11C7/1006 , G11C11/406 , G11C11/40615 , G11C16/06 , G11C16/3454
摘要： A data transfer method and system are provided that prevent the length of a time required for writing to a flash memory from appearing on the surface as a system operation when the flash memory is used in place of an SRAM. The method of transferring data includes the steps of writing data from a controller to a volatile memory, placing the volatile memory in a transfer state, transferring the data from the volatile memory in the transfer state to a nonvolatile memory, and releasing the volatile memory from the transfer state in response to confirming completion of the transfer of the data.
摘要翻译：提供了一种数据传输方法和系统，其防止写入闪速存储器所需的时间长度出现在表面上，作为使用闪速存储器代替SRAM的系统操作。传送数据的方法包括以下步骤：将数据从控制器写入易失性存储器，将易失性存储器置于传送状态，将数据从传送状态的易失性存储器传送到非易失性存储器，并将易失性存储器从响应于确认完成数据传送的传送状态。

8. 发明授权

US06404688B2 Semiconductor memory device having a self-refresh operation 失效
标题翻译：具有自刷新操作的半导体存储器件
公开(公告)号：US06404688B2
公开(公告)日：2002-06-11
申请号：US09791839
申请日：2001-02-26
申请人： Yoshiaki Okuyama , Yoshitaka Takahashi , Shinya Fujioka , Akihiro Funyu
发明人： Yoshiaki Okuyama , Yoshitaka Takahashi , Shinya Fujioka , Akihiro Funyu
IPC分类号： G11C700
CPC分类号： G11C11/406 , G11C7/1045
摘要： A semiconductor memory device having a self-refresh operation includes a first circuit generating a first signal that specifies a first self-refresh cycle by a non-volatile circuit element provided in the semiconductor memory device, a second circuit receiving a second signal that specifies a second self-refresh cycle via a terminal that is used in common to another signal, and a third circuit generating a pulse signal having one of the first and second self-refresh cycles, the pulse signal being related to the self-refresh operation.
摘要翻译：具有自刷新操作的半导体存储器件包括：第一电路，产生由设置在半导体存储器件中的非易失性电路元件指定第一自刷新周期的第一信号;第二电路，接收指定第第二自刷新周期经由与另一信号共同使用的端子，以及第三电路，产生具有第一和第二自刷新周期中的一个的脉冲信号，所述脉冲信号与自刷新操作相关。

9. 发明申请

US20100177651A1 COMMUNICATION APPARATUS AND COMMUNICATION METHOD 审中-公开
标题翻译：通信设备和通信方法
公开(公告)号：US20100177651A1
公开(公告)日：2010-07-15
申请号：US12602549
申请日：2008-05-16
申请人： Yoshiaki Okuyama , Takuya Murakami , Gen Okuyama
发明人： Yoshiaki Okuyama , Takuya Murakami , Gen Okuyama
IPC分类号： H04L12/26
CPC分类号： H04L63/145 , H04L12/5692 , H04W12/12 , H04W48/18
摘要： A determination unit (101) determines, on the basis of the information of a first network (111) used to acquire a communication application and a communication state including a communication method used for acquisition, a network usable by the communication application using a criterion prepared in advance. For example, the determination unit (101) determines a second network (112) as a network usable by the communication application. A communication unit (102) executes communication by the communication application using the network determined by the determination unit (101). For example, the communication unit (102) executes communication by the communication application using the second network (112) determined as usable.
摘要翻译：确定单元（101）基于用于获取通信应用的第一网络（111）的信息和包括用于获取的通信方法的通信状态来确定由通信应用使用的标准准备的准备提前。例如，确定单元（101）将第二网络（112）确定为通信应用可用的网络。通信单元（102）使用由确定单元（101）确定的网络执行通信应用的通信。例如，通信单元（102）使用被确定为可用的第二网络（112）来执行通信应用的通信。

10. 发明授权

US07730232B2 Data transfer method and system 失效
标题翻译：数据传输方式和系统
公开(公告)号：US07730232B2
公开(公告)日：2010-06-01
申请号：US11113181
申请日：2005-04-25
申请人： Shinya Fujioka , Kotoku Sato , Hitoshi Ikeda , Yoshiaki Okuyama , Jun Ohno
发明人： Shinya Fujioka , Kotoku Sato , Hitoshi Ikeda , Yoshiaki Okuyama , Jun Ohno
IPC分类号： G06F13/00
CPC分类号： G06F12/0804 , G06F2212/2022 , G11C7/1006 , G11C11/406 , G11C11/40615 , G11C16/06 , G11C16/3454
摘要： A data transfer method and system are provided that prevent the length of a time required for writing to a flash memory from appearing on the surface as a system operation when the flash memory is used in place of an SRAM. The method of transferring data includes the steps of writing data from a controller to a volatile memory, placing the volatile memory in a transfer state, transferring the data from the volatile memory in the transfer state to a nonvolatile memory, and releasing the volatile memory from the transfer state in response to confirming completion of the transfer of the data.
摘要翻译：提供了一种数据传输方法和系统，其防止写入闪速存储器所需的时间长度出现在表面上，作为使用闪速存储器代替SRAM的系统操作。传送数据的方法包括以下步骤：将数据从控制器写入易失性存储器，将易失性存储器置于传送状态，将数据从传送状态的易失性存储器传送到非易失性存储器，并将易失性存储器从响应于确认完成数据传送的传送状态。

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