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1. 发明申请

US20120196555A1 SEMICONDUCTOR INTEGRATED CIRCUIT AND OPERATION METHOD OF THE SAME 有权
标题翻译：半导体集成电路及其工作方法
公开(公告)号：US20120196555A1
公开(公告)日：2012-08-02
申请号：US13353567
申请日：2012-01-19
申请人： Yutaka IGARASHI , Yusaku KATSUBE
发明人： Yutaka IGARASHI , Yusaku KATSUBE
IPC分类号： H03L5/00 , H04B1/16
CPC分类号： H04B1/30 , H03D2200/0045 , H03D2200/0047
摘要： The present invention is provided to shorten the period of DC offset cancellation operation. One of terminals of two calibration resistors is connected to the differential output terminals of an active low pass filter having a filter process and an amplification function, and two input terminals of a voltage comparator and two terminals of a switch are connected to the other terminal of the two calibration resistors. In a calculation period of calculating digital control signals for reducing DC offset voltage, the voltage comparator detects calibration voltage depending on a voltage drop of one of the calibration resistors caused by analog current of a digital-to-analog converter. In a calibration period of reducing the DC offset voltage, the calibration analog current of the digital-to-analog converter responding to the digital control signal is passed to the input side of the filter via the switch.
摘要翻译：提供本发明以缩短DC偏移消除操作的周期。两个校准电阻器的一个端子连接到具有滤波处理和放大功能的有源低通滤波器的差分输出端子，电压比较器的两个输入端子和开关的两个端子连接到两个校准电阻。在计算用于减小DC偏移电压的数字控制信号的计算周期中，电压比较器根据由数模转换器的模拟电流引起的校准电阻之一的电压降检测校准电压。在减小DC偏移电压的校准周期中，响应于数字控制信号的数模转换器的校准模拟电流通过开关传递到滤波器的输入侧。

2. 发明授权

US07945232B2 Multiband wireless device and semiconductor integrated circuit 失效
标题翻译：多频无线设备和半导体集成电路
公开(公告)号：US07945232B2
公开(公告)日：2011-05-17
申请号：US11769151
申请日：2007-06-27
申请人： Yoshikazu Sugiyama , Satoshi Adachi , Yusaku Katsube , Masazumi Tone , Taku Takaki
发明人： Yoshikazu Sugiyama , Satoshi Adachi , Yusaku Katsube , Masazumi Tone , Taku Takaki
IPC分类号： H04B1/28
CPC分类号： H03F3/195 , H03F1/22 , H03F1/565 , H03F3/24 , H03F2200/108 , H03F2200/111 , H03F2200/294 , H03F2200/381 , H03F2200/387 , H03F2200/391 , H03F2200/451 , H03F2200/519 , H03F2200/75
摘要： When switching over from a portable telephone system of 800 MHz band to a UWB communication system of 9 GHz band, depending upon a signal for changing over a high pass filter and a low pass filter, a reactance element, which is determined to be matching with a load Z of the high pass filter, is connected to an output terminal of a transmitting power amplifier. With this, it is possible to achieve a multi-band or multi-mode wireless receiver of using a frequency band from 800 MHz to 10 GHz, without an enlargement of a circuit scale and an increase of costs.
摘要翻译：当从800MHz频带的便携式电话系统切换到9GHz频带的UWB通信系统时，根据用于切换高通滤波器和低通滤波器的信号，确定为匹配的电抗元件高通滤波器的负载Z连接到发射功率放大器的输出端。由此，可以实现使用800MHz至10GHz的频带的多频带或多模式无线接收机，而不会扩大电路规模并增加成本。

3. 发明授权

US07805123B2 RF transceiver using hopping frequency synthesizer 失效
标题翻译： RF收发器采用跳频合成器
公开(公告)号：US07805123B2
公开(公告)日：2010-09-28
申请号：US11737802
申请日：2007-04-20
申请人： Yoshikazu Sugiyama , Isao Ikuta , Yusaku Katsube
发明人： Yoshikazu Sugiyama , Isao Ikuta , Yusaku Katsube
IPC分类号： H04B1/06 , H04B7/00
CPC分类号： H04L27/2067 , H03C1/52 , H03C3/00 , H04B1/7136 , H04B1/71635
摘要： A technique of frequency hopping communication capable of high-speed switching of a plurality of signals having ultra-wide band 528 MHz bandwidth at high-speed and setting and switching a band center frequency and the number of bands arbitrary is provided. A radio transceiver has a frequency hopping communication function of UWB system for switching the ultra wide band signal. In the device, high-speed frequency hopping is realized by controlling an SSB mixer in a local oscillator circuit and switching the frequency of a DDS. The device sets NCO data to the DDS and switches a quadrature phase signal of an output, and switches a signal input of an input terminal of the SSB mixer by a control of a phase switching switch. One of a sum component and a difference component of a mixture of first and second quadrature phase signals is outputted from the output terminal of the SSB mixer.
摘要翻译：提供一种跳频通信技术，其能够高速切换具有超宽带528MHz带宽的多个信号，并且设置和切换频带中心频率和频带数量的跳频通信。无线电收发器具有用于切换超宽带信号的UWB系统的跳频通信功能。在设备中，通过在本地振荡器电路中控制SSB混频器并切换DDS的频率来实现高速跳频。该装置将NCO数据设置为DDS并切换输出的正交相位信号，并通过相位切换开关的控制切换SSB混频器的输入端的信号输入。从SSB混频器的输出端子输出第一和第二正交相位信号的混合的和分量和差分分量之一。

4. 发明申请

US20070190961A1 Semiconductor integrated circuit and semiconductor integrated circuit for radio communication 有权
标题翻译：半导体集成电路和无线电通信半导体集成电路
公开(公告)号：US20070190961A1
公开(公告)日：2007-08-16
申请号：US11585996
申请日：2006-10-25
申请人： Yutaka Igarashi , Yusaku Katsube , Akio Yamamoto
发明人： Yutaka Igarashi , Yusaku Katsube , Akio Yamamoto
IPC分类号： H04B1/06 , H04B1/28
CPC分类号： H04B1/30
摘要： In a signal receiving circuit of a direct conversion system applied with a semiconductor integrated circuit for radio communication having a PLL requiring a clock signal, an LNA requiring low-noise receiving characteristics, and others, a variable coupling line is provided between clock signal buffers and at an input stage of the PLL, so that coupling between the variable coupling line and an input terminal of the LNA and coupling between the variable coupling line and a GND terminal of the LNA are made equal to each other at frequencies of higher harmonic waves of a clock signal. When the input terminal and the GND terminal of the LNA are excited at the same phase, since no output occurs at an output terminal of the LNA, an output of the LNA does not contain any higher harmonic wave of a clock signal.
摘要翻译：在应用于具有需要时钟信号的PLL的无线电通信用半导体集成电路的直接转换系统的信号接收电路中，需要低噪声接收特性的LNA等，在时钟信号缓冲器和在PLL的输入级，使得可变耦合线与LNA的输入端之间的耦合以及可变耦合线与LNA的GND端之间的耦合使得在高次谐波的频率处彼此相等一个时钟信号。当LNA的输入端子和GND端子在相同相位被激励时，由于在LNA的输出端子处没有输出，所以LNA的输出不包含时钟信号的任何高次谐波。

5. 发明申请

US20050233726A1 Communication terminal equipment 审中-公开
标题翻译：通讯终端设备
公开(公告)号：US20050233726A1
公开(公告)日：2005-10-20
申请号：US11059610
申请日：2005-02-15
申请人： Yusaku Katsube , Koichi Terui
发明人： Yusaku Katsube , Koichi Terui
IPC分类号： H04M1/00 , H04M11/00 , H04W4/20 , H04W4/22 , H04W76/06 , H04Q7/20
CPC分类号： H04W4/90 , H04W76/30 , H04W76/50
摘要： A cellular phone having a telephone communication unit and a data communication unit is provided with the function of notifying a user of emergency data communication immediately even when the emergency data communication was received while a call was in progress. There is provided a communication terminal equipment according to the present invention, which includes a data communication unit which receives emergency data communication, a display unit which displays the contents of the received data communication thereon, and a communication unit which communicates with a base station by phone or the like. The communication unit establishes a call link through a cellular phone network, and the data communication unit allows received data to interrupt a call upon emergency, displays it on the display unit and notifies a user that emergency data has been received.
摘要翻译：具有电话通信单元和数据通信单元的蜂窝电话具有即使当呼叫进行时接收到紧急数据通信时也立即通知用户紧急数据通信的功能。提供了根据本发明的通信终端设备，其包括接收紧急数据通信的数据通信单元，显示接收到的数据通信的内容的显示单元，以及通信单元，其与基站通信电话等。通信单元通过蜂窝电话网络建立呼叫链接，并且数据通信单元允许接收的数据在紧急情况下中断呼叫，将其显示在显示单元上并通知用户已经接收到紧急数据。

6. 发明申请

US20150310756A1 SYSTEM FOR SUPPORTING EDUCATION AND INFORMATION TERMINAL 审中-公开
标题翻译：支持教育和信息终端的系统
公开(公告)号：US20150310756A1
公开(公告)日：2015-10-29
申请号：US14374826
申请日：2012-09-12
申请人： Hideki NAKAMURA , Tetsuo NAKANO , Katsuya MIYATA , Yusaku KATSUBE , Masaaki YAMADA
发明人： Hideki NAKAMURA , Tetsuo NAKANO , Katsuya MIYATA , Yusaku KATSUBE , Masaaki YAMADA
IPC分类号： G09B7/02 , H04L29/08 , H04L29/06
CPC分类号： G09B7/02 , G06Q50/20 , G06Q90/00 , H04L65/4015 , H04L65/403 , H04L67/10
摘要： A learner's terminal is provided with a time acquiring unit for acquiring time, an input unit capable of carrying out a handwriting input, and answer input history data notifying unit for use in notifying a school server of the time acquired by the time acquiring unit and handwriting input data inputted thereto by the input unit as answer input history data, and the school server is provided with an answer input history data storage unit for storing the answer input history data notified by the learner's terminal and an answer input history data transmitting unit for transmitting the answer input history data stored in the answer input history data storage unit to an instructor's terminal, while the instructor's terminal is provided with an answer screen display unit for displaying a screen at the time of answering in time series based upon the answer input history data transmitted by the answer input history data transmitting unit.
摘要翻译：学习者终端设置有用于获取时间的时间获取单元，能够执行手写输入的输入单元，以及答复输入历史数据通知单元，用于通知学校服务器获取时间的时间和手写时间由输入单元输入的输入数据作为应答输入历史数据，学校服务器设置有答录输入历史数据存储单元，用于存储由学习者终端通知的应答输入历史数据和用于发送的应答输入历史数据发送单元存储在应答输入历史数据存储单元中的答案输入历史数据到教师终端，同时教师终端设置有答录画面显示单元，用于基于回答输入历史数据按时间序列显示屏幕由答案输入历史数据发送单元发送。

7. 发明授权

US08229384B2 Filter circuit and receiving apparatus 失效
标题翻译：滤波电路和接收装置
公开(公告)号：US08229384B2
公开(公告)日：2012-07-24
申请号：US12419355
申请日：2009-04-07
申请人： Masaaki Yamada , Yusaku Katsube , Junichi Takahashi , Toshihito Habuka , Fumihito Yamaguchi
发明人： Masaaki Yamada , Yusaku Katsube , Junichi Takahashi , Toshihito Habuka , Fumihito Yamaguchi
IPC分类号： H04B1/06
CPC分类号： H03H7/0153 , H03H7/1708 , H03H7/24 , H03H7/425
摘要： A filter circuit includes first capacitors, second capacitors capable of altering a cutoff frequency by being connected in parallel with the first capacitors, first switches for connecting the second capacitors in parallel with the first capacitors, and charging circuits for the second capacitors. The charging circuits include second switches, and resistances for attenuating the amplitudes of input voltages to be fed to the second capacitors, by being connected in series with the second capacitors. The second capacitors are charged through the resistances in a state where the first switches are turned OFF and where the second switches are turned ON. Thus, a DC offset which is ascribable to the cutoff frequency switching of a filter is reduced.
摘要翻译：滤波器电路包括第一电容器，能够通过与第一电容器并联连接来改变截止频率的第二电容器，用于将第二电容器与第一电容器并联连接的第一开关和用于第二电容器的充电电路。充电电路包括第二开关和用于衰减要馈送到第二电容器的输入电压的振幅的电阻，通过与第二电容器串联连接。在第一开关断开的状态和第二开关导通的状态下，通过电阻对第二电容器进行充电。因此，降低了归因于滤波器的截止频率切换的DC偏移。

8. 发明申请

US20120194265A1 SEMICONDUCTOR INTEGRATED CIRCUIT AND OPERATION METHOD OF THE SAME 有权
标题翻译：半导体集成电路及其工作方法
公开(公告)号：US20120194265A1
公开(公告)日：2012-08-02
申请号：US13357664
申请日：2012-01-25
申请人： Yusaku KATSUBE , Kosuke TSUIJI , Yutaka IGARASHI , Akio YAMAMOTO
发明人： Yusaku KATSUBE , Kosuke TSUIJI , Yutaka IGARASHI , Akio YAMAMOTO
IPC分类号： H03H11/04
CPC分类号： H03H11/1252 , H03H11/1291 , H03H2210/012 , H03H2210/015 , H03H2210/025 , H03H2210/028
摘要： The present invention is directed to accurately set a frequency characteristic of a filter integrated in a semiconductor integrated circuit. A semiconductor integrated circuit includes a filter circuit, a cutoff frequency calibration circuit, and a Q-factor calibration circuit. The cutoff frequency calibration circuit adjusts cutoff frequency of the filter circuit to a desired value by adjusting capacitance components of the filter circuit. After adjustment of the cutoff frequency of the filter circuit by the cutoff frequency calibration circuit, the Q-factor calibration circuit adjusts the Q factor of the filter circuit to a desired value by adjusting a resistance component of the filter circuit.
摘要翻译：本发明旨在精确地设定集成在半导体集成电路中的滤波器的频率特性。半导体集成电路包括滤波电路，截止频率校准电路和Q因子校准电路。截止频率校准电路通过调整滤波器电路的电容分量来将滤波器电路的截止频率调整到期望值。在通过截止频率校准电路调节滤波电路的截止频率之后，Q因子校准电路通过调整滤波器电路的电阻分量来将滤波器电路的Q因子调节到期望值。

9. 发明申请

US20110026507A1 FILTER CIRCUIT AND RECEIVER USING THE SAME 有权
标题翻译：滤波电路和接收器
公开(公告)号：US20110026507A1
公开(公告)日：2011-02-03
申请号：US12789771
申请日：2010-05-28
申请人： Yusaku KATSUBE , Junichi TAKAHASHI , Masaaki YAMADA , Toshihito HABUKA , Kenichi SHIBATA , Fumihito YAMAGUCHI
发明人： Yusaku KATSUBE , Junichi TAKAHASHI , Masaaki YAMADA , Toshihito HABUKA , Kenichi SHIBATA , Fumihito YAMAGUCHI
IPC分类号： H04W88/02 , H03H7/01 , H04B1/16
CPC分类号： H04B1/30 , H03H7/0153 , H03H11/1291 , H03H2210/012 , H03H2210/025 , H03H2210/036 , H03H2250/00
摘要： Gain setting can be performed at high speed while reducing DC offset due to a filter cutoff frequency changeover without the need for input signal muting. A filter circuit having first and second filters is capable of allowing settings of first and second cutoff frequencies. First and second filter switch circuits and a charging circuit including a charging resistor and a charging switch are provided. For a first time period, the first switch circuit is controllably turned on while the second switch circuit is controllably turned off, thereby providing the first filter function. For a second time period, the first switch circuit is controllably turned off while the second switch circuit is controllably turned on, thereby providing the second filter function. For the first time period, the charging switch is controllably turned on so that the second capacitor is charged via the charging resistor.
摘要翻译：增益设置可以高速执行，同时减少由于滤波器截止频率切换引起的直流偏移，而不需要输入信号静音。具有第一和第二滤波器的滤波器电路能够允许第一和第二截止频率的设置。提供第一和第二滤波器开关电路以及包括充电电阻器和充电开关的充电电路。在第一时间段中，第一开关电路被可控地导通，而第二开关电路被可控地关断，从而提供第一滤波器功能。对于第二时间段，第一开关电路在第二开关电路被可控地接通的同时被可控制地截止，从而提供第二滤波器功能。在第一时间段中，充电开关被可控地导通，使得第二电容器经由充电电阻器充电。

10. 发明申请

US20100311381A1 RECEIVING CIRCUIT 失效
标题翻译：接收电路
公开(公告)号：US20100311381A1
公开(公告)日：2010-12-09
申请号：US12846618
申请日：2010-07-29
申请人： Yusaku KATSUBE , Akio YAMAMOTO
发明人： Yusaku KATSUBE , Akio YAMAMOTO
IPC分类号： H04B1/10
CPC分类号： H04B1/1018
摘要： A receiving circuit is provided for performing reception of a plurality of band signals and suppression of blockers that remain in the plurality of band signals being received and converted in frequency. The receiving circuit includes a first low-pass filter that has a first pole position to suppress blockers remaining in a received signal by the first pole position, and a second low-pass filter that has a second pole position to suppress blockers remaining in a signal that has passed through said first low-pass filter by the second pole position. A switch that switches on/off an input-output path including the filters so that the received signal passes through said first filter without passing through the second filter when receiving a first band signal, while the received signal passes through both filters when receiving a second band signal different from the first band signal.
摘要翻译：提供接收电路，用于执行多个频带信号的接收和抑制在频率上接收和转换的多个频带信号中的阻塞。接收电路包括第一低通滤波器，该第一低通滤波器具有第一极位置，以通过第一极位置来抑制接收信号中残留的阻滞剂;以及第二低通滤波器，其具有第二极位置以抑制信号中残留的阻滞剂其通过所述第一低通滤波器通过第二极位置。一种开关，其接通/关闭包括滤波器的输入 - 输出路径，使得当接收到第一频带信号时接收信号通过所述第一滤波器而不通过第二滤波器，同时当接收到的信号在接收到第二滤波器时通过两个滤波器频带信号与第一频带信号不同。

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