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1. 发明申请

US20160365970A1 SPLIT LOOP TIMING RECOVERY 有权
标题翻译：分段循环时序恢复
公开(公告)号：US20160365970A1
公开(公告)日：2016-12-15
申请号：US15208769
申请日：2016-07-13
申请人： APPLIED MICRO CIRCUITS CORPORATION
发明人： Moshe Malkin , Tarun Gupta
IPC分类号： H04L7/00 , H04B1/04 , H04L12/26
CPC分类号： H04L7/0087 , H04B1/04 , H04L7/0025 , H04L7/0079 , H04L7/0091 , H04L43/087
摘要： Various embodiments provide systems and methods for performing clock recovery on a received signal using a split loop architecture. A split loop timing recovery apparatus is provided comprising a first path configured for performing frequency offset tracking on a signal by adjusting a receiver clock frequency to match a remote transmitter frequency associated with the signal and a second path configured for tracking random jitter on the signal.
摘要翻译：各种实施例提供了使用分割环路架构对接收到的信号执行时钟恢复的系统和方法。提供了一种分路定时恢复装置，包括：第一路径，被配置为通过调整接收机时钟频率来匹配与该信号相关联的远程发射机频率和被配置用于跟踪该信号上的随机抖动的第二路径来对信号进行频率偏移跟踪。

2. 发明授权

US09397822B1 Split loop timing recovery 有权
标题翻译：分路回路定时恢复
公开(公告)号：US09397822B1
公开(公告)日：2016-07-19
申请号：US14736754
申请日：2015-06-11
申请人： APPLIED MICRO CIRCUITS CORPORATION
发明人： Moshe Malkin , Tarun Gupta
IPC分类号： H03D3/24 , H04L7/00 , H04L12/26
CPC分类号： H04L7/0087 , H04B1/04 , H04L7/0025 , H04L7/0079 , H04L7/0091 , H04L43/087
摘要： Various embodiments provide systems and methods for performing clock recovery on a received signal using a split loop architecture. A split loop timing recovery apparatus is provided comprising a first path configured for performing frequency offset tracking on a signal by adjusting a receiver clock frequency to match a remote transmitter frequency associated with the signal and a second path configured for tracking random jitter on the signal.
摘要翻译：各种实施例提供了使用分割环路架构对接收到的信号执行时钟恢复的系统和方法。提供了一种分路定时恢复装置，包括：第一路径，被配置为通过调整接收机时钟频率来匹配与该信号相关联的远程发射机频率和被配置用于跟踪该信号上的随机抖动的第二路径来对信号进行频率偏移跟踪。

3. 发明授权

US09485039B1 Calibration and tracking of receiver 有权
标题翻译：接收机的校准和跟踪
公开(公告)号：US09485039B1
公开(公告)日：2016-11-01
申请号：US14736874
申请日：2015-06-11
申请人： APPLIED MICRO CIRCUITS CORPORATION
发明人： Moshe Malkin , Tarun Gupta
IPC分类号： H03M1/10 , H04B17/21
CPC分类号： H04B17/21 , H04B17/14
摘要： Techniques for calibrating interleaved analog-to-digital converter (ADC) arrays are presented. A transceiver comprises an ADC component comprising an array of interleaved sub-ADCs, and an auxiliary path associated with an auxiliary sub-ADC used to facilitate calibrating a sampling array by comparing the auxiliary path signal to signals of the sub-ADCs in the array. A calibration component employs a phase-interpolator and analog delay lines to adjust the auxiliary sub-ADC to enable the auxiliary sub-ADC to be lined up to any one of the sampling instants of the sampling array. The calibration component compares the auxiliary signal to sub-ADC signals, determines path differences between the sub-ADC paths based on the comparison results, and calibrates the sub-ADCs and sub-ADC paths to reduce the path differences to mitigate distortion in a digital stream produced from combining the digital substreams produced by the sub-ADCs in the array.
摘要翻译：提出了校准交错模数转换器（ADC）阵列的技术。收发器包括包括交错子ADC阵列的ADC组件，以及与辅助子ADC相关联的辅助路径，用于通过将辅助路径信号与阵列中的子ADC的信号进行比较来便于校准采样阵列。校准组件采用相位内插器和模拟延迟线来调整辅助子ADC，使辅助子ADC能够排列到采样阵列的任何一个采样时刻。校准组件将辅助信号与子ADC信号进行比较，根据比较结果确定子ADC路径之间的路径差异，并校准子ADC和子ADC路径以减少路径差异以减轻数字中的失真通过组合由阵列中的子ADC产生的数字子流产生的流。

4. 发明授权

US10110334B2 High speed serializer using quadrature clocks 有权
公开(公告)号：US10110334B2
公开(公告)日：2018-10-23
申请号：US15137187
申请日：2016-04-25
申请人： APPLIED MICRO CIRCUITS CORPORATION
发明人： Vijay Gupta , Tarun Gupta
IPC分类号： H04J3/06 , H04L7/00 , H03M9/00 , H04J3/04
摘要： Techniques efficiently serialize multiple data streams using quadrature clocks. Serializer employs first, second, third, and fourth clock signals. Serializer receives multiple data streams via registers, with each of four paths comprising a register, buffer, and switch, with registers of first and fourth paths associated with third clock signal, and registers of second and third paths associated with first clock signal, and with switches of first and fourth paths associated with first clock signal, and switches of second and third paths associated with third clock signal. Switches of first and second paths transfer respective data bits to fifth switch via another buffer, wherein fifth switch is associated with a delayed second clock signal of a time delay component (TDC). Switches of third and fourth paths transfer respective data bits to sixth switch via another buffer, wherein sixth switch is associated with a delayed fourth clock signal of TDC.

5. 发明申请

US20170310412A1 HIGH SPEED SERIALIZER USING QUADRATURE CLOCKS 审中-公开
公开(公告)号：US20170310412A1
公开(公告)日：2017-10-26
申请号：US15137187
申请日：2016-04-25
申请人： APPLIED MICRO CIRCUITS CORPORATION
发明人： Vijay Gupta , Tarun Gupta
IPC分类号： H04J3/06 , H04L7/00
CPC分类号： H04J3/0691 , H03M9/00 , H04J3/047 , H04J3/0682 , H04J3/0685 , H04L7/0037
摘要： Techniques efficiently serialize multiple data streams using quadrature clocks. Serializer employs first, second, third, and fourth clock signals. Serializer receives multiple data streams via registers, with each of four paths comprising a register, buffer, and switch, with registers of first and fourth paths associated with third clock signal, and registers of second and third paths associated with first clock signal, and with switches of first and fourth paths associated with first clock signal, and switches of second and third paths associated with third clock signal. Switches of first and second paths transfer respective data bits to fifth switch via another buffer, wherein fifth switch is associated with a delayed second clock signal of a time delay component (TDC). Switches of third and fourth paths transfer respective data bits to sixth switch via another buffer, wherein sixth switch is associated with a delayed fourth clock signal of TDC.

6. 发明申请

US20150326197A1 PROGRAMMABLE GAIN AMPLIFIER WITH CONTROLLED GAIN STEPS 有权
标题翻译：具有控制增益步长的可编程增益放大器
公开(公告)号：US20150326197A1
公开(公告)日：2015-11-12
申请号：US14162896
申请日：2014-01-24
申请人： APPLIED MICRO CIRCUITS CORPORATION
发明人： Nanda Govind Jayaraman , Tarun Gupta
IPC分类号： H03G3/30
CPC分类号： H03G3/30 , H03G1/0029
摘要： Provided is a programmable gain amplifier that includes controlled gain steps that dynamically control an output voltage in real-time. The programmable gain amplifier includes a first transistor and a second transistor that includes respective control ports, input ports, and output ports. The programmable gain amplifier also includes a resistor connected to the output ports of the transistors. Further, at least a third transistor is connected to the output ports, in parallel with the resistor. On applying a control voltage to the third transistor and applying an input voltage to the first control port, the second control port is selectively modified by the control voltage to produce a desired output at the first input port and the second input port
摘要翻译：提供了一种可编程增益放大器，其包括可实时动态地控制输出电压的受控增益步长。可编程增益放大器包括第一晶体管和第二晶体管，其包括相应的控制端口，输入端口和输出端口。可编程增益放大器还包括连接到晶体管的输出端口的电阻器。此外，至少第三晶体管与电阻器并联连接到输出端口。在对第三晶体管施加控制电压并向第一控制端口施加输入电压时，通过控制电压选择性地修改第二控制端口，以在第一输入端口和第二输入端口产生期望的输出

7. 发明授权

US09716583B2 Split loop timing recovery 有权
公开(公告)号：US09716583B2
公开(公告)日：2017-07-25
申请号：US15208769
申请日：2016-07-13
申请人： APPLIED MICRO CIRCUITS CORPORATION
发明人： Moshe Malkin , Tarun Gupta
IPC分类号： H03D3/24 , H04L7/00 , H04L12/26 , H04B1/04
CPC分类号： H04L7/0087 , H04B1/04 , H04L7/0025 , H04L7/0079 , H04L7/0091 , H04L43/087
摘要： Various embodiments provide systems and methods for performing clock recovery on a received signal using a split loop architecture. A split loop timing recovery apparatus is provided comprising a first path configured for performing frequency offset tracking on a signal by adjusting a receiver clock frequency to match a remote transmitter frequency associated with the signal and a second path configured for tracking random jitter on the signal.

8. 发明申请

US20150326379A1 DUPLEX TRANSMISSION OVER REDUCED PAIRS OF TWINAX CABLES 有权
标题翻译：双重传输双绞线传输
公开(公告)号：US20150326379A1
公开(公告)日：2015-11-12
申请号：US14179727
申请日：2014-02-13
申请人： APPLIED MICRO CIRCUITS CORPORATION
发明人： Dariush Dabiri , Tarun Gupta , Venkatesh Nagapudi
IPC分类号： H04L5/14
CPC分类号： H03M13/29 , H03M13/1102 , H03M13/134 , H03M13/152 , H03M13/19 , H03M13/253 , H03M13/256 , H03M13/258 , H03M13/2909 , H03M13/2957 , H03M13/3916 , H03M13/616 , H03M13/63 , H04B1/38 , H04B3/02 , H04L1/0041 , H04L1/0045 , H04L1/0058 , H04L1/0061 , H04L1/0067 , H04L5/14 , H04L5/1423 , H04L7/042 , H04L27/0002 , H04L27/3483
摘要： Cable systems and assemblies integrate a reduced number of twin axial copper pairs to transmit and received in a full-duplex transmission signals at transmission speeds greater than or equal to one hundred Giga bytes per second. The reduced number of twin axial copper pairs comprise four or less twin axial copper pairs, in which each pair forms a single twin axial full-duplex cable for passive or active communication of the signals. A processor can be integrated with the twin axial copper pairs operate to encode the signals for fast transmission speeds.
摘要翻译：有线系统和组件集成了减少数量的双轴铜对，以传输速度大于或等于每千兆字节的传输速度传输和接收全双工传输信号。双轴向铜对的数量减少包括四个或更少的双轴铜对，其中每对形成单个双轴全双工电缆，用于信号的无源或主动通信。处理器可以与双轴铜对集成，以对信号进行编码以实现快速传输速度。

9. 发明申请

US20150326376A1 MULTI-RATE TRANSMISSIONS OVER TWINAX CABLES 有权
标题翻译：多纳米线上的多路传输
公开(公告)号：US20150326376A1
公开(公告)日：2015-11-12
申请号：US14466327
申请日：2014-08-22
申请人： APPLIED MICRO CIRCUITS CORPORATION
发明人： Dariush Dabiri , Tarun Gupta , Venkatesh Nagapudi
IPC分类号： H04L5/14 , H04B3/02 , H04B1/38
CPC分类号： H03M13/29 , H03M13/1102 , H03M13/134 , H03M13/152 , H03M13/19 , H03M13/253 , H03M13/256 , H03M13/258 , H03M13/2909 , H03M13/2957 , H03M13/3916 , H03M13/616 , H03M13/63 , H04B1/38 , H04B3/02 , H04L1/0041 , H04L1/0045 , H04L1/0058 , H04L1/0061 , H04L1/0067 , H04L5/14 , H04L5/1423 , H04L7/042 , H04L27/0002 , H04L27/3483
摘要： Cable systems and assemblies integrate a reduced number of twin axial cables to transmit and received in a full-duplex transmission signals at transmission speeds greater than or equal to one hundred Giga bytes per second. The reduced number of twin axial cables comprise four or less twin axial cables, in which each pair forms a single twin axial full-duplex cable for passive or active communication of the signals at multiple different transmission rates concurrently. A processor can be integrated with the twin axial cables and operate to encode the signals for fast transmission speeds at the different transmission rates.
摘要翻译：电缆系统和组件集成了减少数量的双轴电缆，以传输速度大于或等于每千兆字节的传输速度传输和接收全双工传输信号。双轴向电缆的数量减少包括四个或更少的双轴向电缆，其中每对形成单个双轴全双工电缆，用于同时以多个不同传输速率无源或主动地通信信号。处理器可以与双轴向电缆集成，并且以不同的传输速率对信号进行编码以实现快速传输速度。

10. 发明授权

US09787519B2 Multi-rate transmissions over twinax cables 有权
公开(公告)号：US09787519B2
公开(公告)日：2017-10-10
申请号：US14466327
申请日：2014-08-22
申请人： APPLIED MICRO CIRCUITS CORPORATION
发明人： Dariush Dabiri , Tarun Gupta , Venkatesh Nagapudi
IPC分类号： H03M13/25 , H04L27/34 , H04L5/14 , H04B1/38 , H04B3/02 , H04L27/00 , H04L1/00 , H03M13/39 , H04L7/04 , H03M13/13
CPC分类号： H03M13/29 , H03M13/1102 , H03M13/134 , H03M13/152 , H03M13/19 , H03M13/253 , H03M13/256 , H03M13/258 , H03M13/2909 , H03M13/2957 , H03M13/3916 , H03M13/616 , H03M13/63 , H04B1/38 , H04B3/02 , H04L1/0041 , H04L1/0045 , H04L1/0058 , H04L1/0061 , H04L1/0067 , H04L5/14 , H04L5/1423 , H04L7/042 , H04L27/0002 , H04L27/3483
摘要： Cable systems and assemblies integrate a reduced number of twin axial cables to transmit and received in a full-duplex transmission signals at transmission speeds greater than or equal to one hundred Giga bytes per second. The reduced number of twin axial cables comprise four or less twin axial cables, in which each pair forms a single twin axial full-duplex cable for passive or active communication of the signals at multiple different transmission rates concurrently. A processor can be integrated with the twin axial cables and operate to encode the signals for fast transmission speeds at the different transmission rates.

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