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1. 发明授权

US07123113B1 Regulated, symmetrical crystal oscillator circuit and method 有权
标题翻译：调节对称晶体振荡电路及方法
公开(公告)号：US07123113B1
公开(公告)日：2006-10-17
申请号：US10866510
申请日：2004-06-11
申请人： Aaron Brennan , Jonathon Stiff , Mike McMenamy
发明人： Aaron Brennan , Jonathon Stiff , Mike McMenamy
IPC分类号： H03B5/36 , H03B1/00 , H03L1/00 , H03L5/00
CPC分类号： H03L5/00 , H03B5/04 , H03B5/36 , H03B2200/0012
摘要： An oscillator circuit is provided that is preferably a crystal oscillator, where voltage placed across the crystal is regulated. The regulated voltage or amplitude of the cyclical signal across the crystal is monitored and maintained through a regulation circuit that measures a peak voltage across the crystal. Once the peak voltage exceeds a predetermined setpoint value, then a controller within the regulation circuit will reduce a biasing current through an amplifying transistor within the amplifier coupled across the crystal input and output nodes. By regulating the biasing current, gain from the amplifier is also regulated so that unwanted non-linearities and harmonic distortion is not induced within the crystal to cause frequency distortion and unwanted modes of oscillation within the crystal. The amplifier is preferably symmetrical in that the amplifier sources and sinks equal current to reduce unwanted peaks at the negative or positive half cycles of the sinusoidal signal.
摘要翻译：提供了一种振荡器电路，其优选是晶体振荡器，其中调节晶体两端的电压。晶体周期信号的调节电压或幅度通过调节电路进行监测和维持，该电路测量晶体两端的峰值电压。一旦峰值电压超过预定的设定值，则调节电路内的控制器将减小通过晶体输入和输出节点耦合的放大器内的放大晶体管的偏置电流。通过调节偏置电流，放大器的增益也被调节，使得在晶体内不会引起不需要的非线性和谐波失真，从而导致晶体内的频率失真和不期望的振荡模式。放大器优选对称，因为放大器源和吸收器相等电流以减少在正弦信号的负半周期或正半周期的不期望的峰值。

2. 发明授权

US07196586B1 Oscillator amplifier circuit operable to provide symmetric current limiting and method of same 有权
标题翻译：振荡器放大器电路可操作以提供对称限流及其方法
公开(公告)号：US07196586B1
公开(公告)日：2007-03-27
申请号：US11009816
申请日：2004-12-10
申请人： Jonathon Stiff , Aaron Brennan
发明人： Jonathon Stiff , Aaron Brennan
IPC分类号： H03F3/04
CPC分类号： H03F1/342 , H03B5/364 , H03B2202/06 , H03F1/223 , H03F3/345 , H03F2200/121 , H03F2200/357 , H03F2200/381 , H03F2200/75
摘要： An amplifier circuit operable to provide symmetric current limiting. The amplifier circuit includes a common source amplifier for sourcing a current and receiving an voltage input, a current source, and a current limiting device coupled between the common source amplifier and the current source. The current limiting device is operable to limit the current sourced by the common source amplifier. A bias network coupled to the current limiting device biases the current limiting device. An output is coupled to the current limiting device. The amount of current that is sourced to the output of the amplifier circuit may be limited, such that current limiting is symmetrical.
摘要翻译：可操作以提供对称电流限制的放大器电路。放大器电路包括用于提供电流并接收电压输入的公共源放大器，电流源和耦合在公共源放大器和电流源之间的限流装置。限流装置可操作以限制由公共源放大器产生的电流。耦合到限流装置的偏置网络偏压限流装置。输出耦合到限流装置。可以限制来自放大器电路的输出的电流量，使得限流是对称的。

3. 发明授权

US07961060B1 Amplitude regulated resonant oscillator with sampled feedback 有权
标题翻译：具有采样反馈的幅度调节谐振振荡器
公开(公告)号：US07961060B1
公开(公告)日：2011-06-14
申请号：US11764880
申请日：2007-06-19
申请人： Michael McMenamy , Adam El-Mansouri , Jonathon Stiff , Mandonev Rajasekaran
发明人： Michael McMenamy , Adam El-Mansouri , Jonathon Stiff , Mandonev Rajasekaran
IPC分类号： H03L1/00
CPC分类号： H03L5/00
摘要： Disclosed is an oscillator circuit, comprising a crystal oscillator, an amplifier having an input and an output coupled across the crystal oscillator, a comparator having a reference input and an input coupled to the crystal oscillator and a pole network coupled between the comparator and the amplifier.
摘要翻译：公开了一种振荡器电路，包括晶体振荡器，具有耦合在晶体振荡器两端的输入和输出的放大器，具有参考输入和耦合到晶体振荡器的输入的比较器和耦合在比较器和放大器之间的极点。

4. 发明授权

US08085067B1 Differential-to-single ended signal converter circuit and method 有权
标题翻译：差分到单端信号转换电路及方法
公开(公告)号：US08085067B1
公开(公告)日：2011-12-27
申请号：US11644100
申请日：2006-12-21
申请人： Jonathon Stiff
发明人： Jonathon Stiff
IPC分类号： G11C7/06
CPC分类号： H03F3/45179 , H03F2203/45318
摘要： A differential-to-single ended converter circuit can include a latching circuit having first and second latch field effect transistors (FETs) with drains and gates cross-coupled between a first latch node and a second latch node. The source-drain paths of the first and second latch FETs are coupled to a first reference potential node via separate current paths. A sense circuit can include a first sense FET having a source-drain path coupled between the first sense node and the first reference potential node, and a gate coupled to a first input node. A second sense FET has a source-drain path coupled between the second sense node and the first reference potential node, and a gate coupled to a second input node. An output circuit can have a first output FET with a source-drain path coupled between a first output supply node and an output signal node, and a gate coupled to the first latch node, and a second output FET with a source-drain path coupled between the output signal node and a second output supply node.
摘要翻译：差分到单端转换器电路可以包括具有第一和第二锁存场效应晶体管（FET）的锁存电路，其中漏极和栅极交叉耦合在第一锁存节点和第二锁存器节点之间。第一和第二锁存FET的源极 - 漏极路径经由分离的电流路径耦合到第一参考电位节点。感测电路可以包括具有耦合在第一感测节点和第一参考电位节点之间的源极 - 漏极路径的第一感测FET以及耦合到第一输入节点的栅极。第二感测FET具有耦合在第二感测节点和第一参考电位节点之间的源极 - 漏极路径，以及耦合到第二输入节点的栅极。输出电路可以具有第一输出FET，源极 - 漏极路径耦合在第一输出电源节点和输出信号节点之间，栅极耦合到第一锁存节点，第二输出FET的源极 - 漏极路径耦合在输出信号节点和第二输出供应节点之间。

5. 发明授权

US07265633B1 Open loop bandwidth test architecture and method for phase locked loop (PLL) 有权
标题翻译：开环带宽测试架构和锁相环（PLL）方法
公开(公告)号：US07265633B1
公开(公告)日：2007-09-04
申请号：US11132894
申请日：2005-05-19
申请人： Jonathon Stiff
发明人： Jonathon Stiff
IPC分类号： H03L7/00 , G01R23/00
CPC分类号： H03L7/0891 , H03L7/093
摘要： A phase locked loop (PLL) can include a test loop filter (100) that generates a control voltage (VCTRL) for input to a voltage controlled oscillator (VCO). In a test mode, a control voltage can be varied and resulting output frequencies recorded, from which an open loop bandwidth can be determined. A control voltage can be varied by enabling a switch element (104-1) that can provide a current path through load resistance (RL) of test loop filter (100). Current provided to the test loop filter can be varied according to test signals to provide a variable control voltage (VCTRL).
摘要翻译：锁相环（PLL）可以包括产生用于输入到压控振荡器（VCO）的控制电压（V SUB CTRL）的测试环路滤波器（100）。在测试模式中，可以改变控制电压并记录所得到的输出频率，从而可以确定开环带宽。可以通过启用能够提供通过测试环路滤波器（100）的负载电阻（RL）的电流路径的开关元件（104-1）来改变控制电压。提供给测试环路滤波器的电流可以根据测试信号而变化，以提供可变的控制电压（V CTRL）。

6. 发明申请

US20080136470A1 Method and circuit for rapid alignment of signals 有权
标题翻译：信号快速对准的方法和电路
公开(公告)号：US20080136470A1
公开(公告)日：2008-06-12
申请号：US11985340
申请日：2007-11-13
申请人： Nathan Moyal , Jonathon Stiff
发明人： Nathan Moyal , Jonathon Stiff
IPC分类号： H03L7/00
CPC分类号： H03K5/135 , H03K5/156
摘要： Circuits and methods for aligning two or more signals including a first and second signal. In one embodiment, a shift register generates two or more shifted copies of the second signal, and each of a plurality of phase detectors receives the first signal and one of the shifted copies of the second signal, each phase detector providing an output indicating whether the first signal is substantially aligned with the shifted copy of the second signal. A multiplexer may also be provided for receiving each of the shifted copies of the second signal, the multiplexer having a plurality of select lines coupled with the output signals of the phase detectors. Some embodiments may include a power saving mode.
摘要翻译：用于对准包括第一和第二信号的两个或多个信号的电路和方法。在一个实施例中，移位寄存器产生第二信号的两个或更多个偏移副本，并且多个相位检测器中的每一个接收第一信号和第二信号的移位副本之一，每个相位检测器提供一个输出，第一信号基本上与第二信号的偏移副本对准。还可以提供多路复用器用于接收第二信号的每个移位副本，多路复用器具有与相位检测器的输出信号耦合的多条选择线。一些实施例可以包括省电模式。

7. 发明授权

US07030662B1 Rail-to-rail input linear voltage to current converter 失效
标题翻译：轨到轨输入线电压到电流转换器
公开(公告)号：US07030662B1
公开(公告)日：2006-04-18
申请号：US10809238
申请日：2004-03-24
申请人： Jonathon Stiff
发明人： Jonathon Stiff
IPC分类号： H03B1/00
CPC分类号： G05F1/561
摘要： A voltage-to-current converter circuit is disclosed. In one embodiment, the present invention includes a first metal oxide semiconductor field effect transistor (MOSFET) stage operable in a low to medium power range. The present invention also includes a second MOSFET stage operable in a medium to high power range. An additive circuit is utilized to add the contributions of both the first MOSFET stage and the second MOSFET stage. A subtractive circuit is further used to subtract either the first MOSFET stage or the second MOSFET stage when both the first MOSFET stage and the second MOSFET stage are operating in the medium power range and outputting current in a voltage-to-current converting circuit.
摘要翻译：公开了一种电压 - 电流转换器电路。在一个实施例中，本发明包括可在低功率到中等功率范围内操作的第一金属氧化物半导体场效应晶体管（MOSFET）级。本发明还包括在中等到高功率范围内可操作的第二MOSFET级。利用加法电路来增加第一MOSFET级和第二MOSFET级的贡献。当第一MOSFET级和第二MOSFET级都工作在中等功率范围并且在电压 - 电流转换电路中输出电流时，减法电路还用于减去第一MOSFET级或第二MOSFET级。

8. 发明授权

US07893724B2 Method and circuit for rapid alignment of signals 有权
标题翻译：信号快速对准的方法和电路
公开(公告)号：US07893724B2
公开(公告)日：2011-02-22
申请号：US11985340
申请日：2007-11-13
申请人： Nathan Moyal , Jonathon Stiff
发明人： Nathan Moyal , Jonathon Stiff
IPC分类号： G01R25/00
CPC分类号： H03K5/135 , H03K5/156
摘要： Circuits and methods for aligning two or more signals including a first and second signal. In one embodiment, a shift register generates two or more shifted copies of the second signal, and each of a plurality of phase detectors receives the first signal and one of the shifted copies of the second signal, each phase detector providing an output indicating whether the first signal is substantially aligned with the shifted copy of the second signal. A multiplexer may also be provided for receiving each of the shifted copies of the second signal, the multiplexer having a plurality of select lines coupled with the output signals of the phase detectors. Some embodiments may include a power saving mode.
摘要翻译：用于对准包括第一和第二信号的两个或多个信号的电路和方法。在一个实施例中，移位寄存器产生第二信号的两个或更多个偏移副本，并且多个相位检测器中的每一个接收第一信号和第二信号的移位副本之一，每个相位检测器提供一个输出，第一信号基本上与第二信号的偏移副本对准。还可以提供多路复用器用于接收第二信号的每个移位副本，多路复用器具有与相位检测器的输出信号耦合的多条选择线。一些实施例可以包括省电模式。

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