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1. 发明申请

US20180033960A1 NONVOLATILE MEMORY ELEMENTS HAVING CONDUCTIVE STRUCTURES WITH SEMIMETALS AND/OR SEMICONDUCTORS 审中-公开
公开(公告)号：US20180033960A1
公开(公告)日：2018-02-01
申请号：US15650719
申请日：2017-07-14
申请人： Adesto Technologies Corporation
发明人： John Ross Jameson, III , Foroozan Sarah Koushan
IPC分类号： H01L45/00
CPC分类号： H01L45/1253 , H01L45/085 , H01L45/1233 , H01L45/1266 , H01L45/146 , H01L45/16 , H01L45/1658
摘要： A memory element programmable between different impedance states, comprising: a first electrode layer comprising a semimetal or semiconductor (semimetal/semiconductor) and at least one other first electrode element; a second electrode; and a switch layer formed between the first and second electrodes and comprising an insulating material; wherein atoms of the semimetal/semiconductor provide a reversible change in conductivity of the switch layer by application of electric fields.

2. 发明授权

US09734902B2 Resistive memory device with ramp-up/ramp-down program/erase pulse 有权
公开(公告)号：US09734902B2
公开(公告)日：2017-08-15
申请号：US14861680
申请日：2015-09-22
申请人： Adesto Technologies Corporation , Axon Technologies Corporation
发明人： Deepak Kamalanathan , Foroozan Sarah Koushan , Juan Pablo Saenz Echeverry , John Dinh , Shane C. Hollmer , Michael Kozicki
IPC分类号： G11C13/00
CPC分类号： G11C13/003 , G11C13/0002 , G11C13/0004 , G11C13/0007 , G11C13/0011 , G11C13/0028 , G11C13/004 , G11C13/0061 , G11C13/0069 , G11C13/0097 , G11C2013/0071 , G11C2013/0092 , G11C2213/79
摘要： In one embodiment, a method of operating a resistive switching device includes applying a signal comprising a pulse on a first terminal of a two terminal resistive switching device having the first terminal and a second terminal. The resistive switching device has a first state and a second state. The pulse includes a first ramp from a first voltage to a second voltage over a first time period. The first time period is at least 0.1 times a total time period of the pulse.

3. 发明授权

US11537754B1 Pseudo physically unclonable functions (PUFS) using one or more addressable arrays of elements having random/pseudo-random values 有权
公开(公告)号：US11537754B1
公开(公告)日：2022-12-27
申请号：US16571051
申请日：2019-09-13
申请人： Adesto Technologies Corporation
发明人： John R. Jameson , David Kim , Foroozan Sarah Koushan
IPC分类号： G06F21/75 , H04L9/32 , G06F21/72 , G11C13/00 , G06F7/58 , G11C11/16
摘要： An integrated circuit device can include a plurality of nonvolatile memory elements having values that vary randomly or pseudo-randomly from one another; a selection circuit configured to select a plurality of nonvolatile memory elements that vary randomly or pseudo-randomly in response to a received challenge value; and sense circuits configured to generate a response value based on the values of the selected nonvolatile memory elements. Related methods and systems are also disclosed.

4. 发明申请

US20160012885A1 Resistive Devices and Methods of Operation Thereof 审中-公开
公开(公告)号：US20160012885A1
公开(公告)日：2016-01-14
申请号：US14861680
申请日：2015-09-22
申请人： Adesto Technologies Corporation , Axon Technologies Corporation
发明人： Deepak Kamalanathan , Foroozan Sarah Koushan , Juan Pablo Saenz Echeverry , John Dinh , Shane C. Hollmer , Michael Kozicki
IPC分类号： G11C13/00
CPC分类号： G11C13/003 , G11C13/0002 , G11C13/0004 , G11C13/0007 , G11C13/0011 , G11C13/0028 , G11C13/004 , G11C13/0061 , G11C13/0069 , G11C13/0097 , G11C2013/0071 , G11C2013/0092 , G11C2213/79
摘要： In one embodiment, a method of operating a resistive switching device includes applying a signal comprising a pulse on a first terminal of a two terminal resistive switching device having the first terminal and a second terminal. The resistive switching device has a first state and a second state. The pulse includes a first ramp from a first voltage to a second voltage over a first time period. The first time period is at least 0.1 times a total time period of the pulse.

5. 发明申请

US20150162079A1 Resistive Devices and Methods of Operation Thereof 有权
标题翻译：电阻器件及其操作方法
公开(公告)号：US20150162079A1
公开(公告)日：2015-06-11
申请号：US14599654
申请日：2015-01-19
申请人： Adesto Technologies Corporation
发明人： Foroozan Sarah Koushan , Michael A. Van Buskirk
IPC分类号： G11C13/00
CPC分类号： G11C13/003 , G11C13/0002 , G11C13/0004 , G11C13/0007 , G11C13/0009 , G11C13/0011 , G11C13/004 , G11C13/0069 , G11C2013/0071 , G11C2013/0092 , G11C2213/74 , G11C2213/79
摘要： In accordance with an embodiment of the present invention, a method of operating a resistive switching device includes applying a signal including a pulse on a first access terminal of an access device having the first access terminal and a second access terminal. The second access terminal is coupled to a first terminal of a two terminal resistive switching device. The resistive switching device has the first terminal and a second terminal. The resistive switching device has a first state and a second state. The pulse includes a first ramp from a first voltage to a second voltage over a first time period, a second ramp from the second voltage to a third voltage over a second time period, and a third ramp from the third voltage to a fourth voltage over a third time period. The second ramp and the third ramp have an opposite slope to the first ramp. The sum of the first time period and the second time period is less than the third time period.
摘要翻译：根据本发明的实施例，一种操作电阻式交换设备的方法包括：在具有第一接入终端的接入设备的第一接入终端和第二接入终端上应用包括脉冲的信号。第二接入终端耦合到两端电阻式交换设备的第一终端。电阻式开关装置具有第一端子和第二端子。电阻式开关装置具有第一状态和第二状态。脉冲包括在第一时间段内从第一电压到第二电压的第一斜坡，在第二时间段内从第二电压到第三电压的第二斜坡，以及从第三电压到第四电压的第三斜坡第三个时期。第二斜坡和第三斜坡与第一坡道具有相反的斜坡。第一时间段和第二时间段的总和小于第三时间段。

6. 发明授权

US09025396B1 Pre-conditioning circuits and methods for programmable impedance elements in memory devices 有权
标题翻译：存储器件中可编程阻抗元件的预调节电路和方法
公开(公告)号：US09025396B1
公开(公告)日：2015-05-05
申请号：US13763461
申请日：2013-02-08
申请人： Adesto Technologies Corporation
发明人： Foroozan Sarah Koushan , Deepak Kamalanathan , Juan Pablo Saenz Echeverry , Venkatesh P. Gopinath , Janet Wang
IPC分类号： G11C7/00 , G11C13/00
CPC分类号： G11C13/0069 , G11C13/0011 , G11C2013/0073 , G11C2013/0083
摘要： A memory device can include a plurality of programmable impedance elements programmable between a low impedance state in response to a program voltage and a higher impedance state in response to an erase voltage having a different polarity than the program voltage; a programming circuit configured to apply the program and erase voltages to selected elements; and a pre-condition path configured to apply a pre-condition voltage only of the erase voltage polarity to fresh elements in a pre-condition operation; wherein fresh elements are elements that have not been subject to any programming voltages. The pre-condition electrical conditions can also include high voltage low current conditions that apply a greater magnitude voltage and smaller current than the first or second electrical conditions, or high voltage low current conditions that apply a greater magnitude voltage and greater current than the first or second electrical conditions.
摘要翻译：存储器件可以包括响应于具有与编程电压不同的极性的擦除电压而响应于编程电压和较高阻抗状态而在低阻抗状态之间可编程的多个可编程阻抗元件; 编程电路，被配置为将编程和擦除电压施加到所选择的元件; 以及预条件路径，被配置为仅在所述前置操作中将新的所述擦除电压极性的前提电压施加于新元件; 其中新鲜元件是未经过任何编程电压的元件。预条件电气条件还可以包括施加比第一或第二电气条件更大的电压和更小的电流的高电压低电流条件，或者施加比第一或第二电气条件更大的电压和更大的电流的高压低电流条件第二电气条件。

7. 发明授权

US09431101B2 Resistive devices and methods of operation thereof 有权
公开(公告)号：US09431101B2
公开(公告)日：2016-08-30
申请号：US14599654
申请日：2015-01-19
申请人： Adesto Technologies Corporation
发明人： Foroozan Sarah Koushan , Michael A. Van Buskirk
IPC分类号： G11C7/00 , G11C13/00
CPC分类号： G11C13/003 , G11C13/0002 , G11C13/0004 , G11C13/0007 , G11C13/0009 , G11C13/0011 , G11C13/004 , G11C13/0069 , G11C2013/0071 , G11C2013/0092 , G11C2213/74 , G11C2213/79
摘要： In accordance with an embodiment of the present invention, a method of operating a resistive switching device includes applying a signal including a pulse on a first access terminal of an access device having the first access terminal and a second access terminal. The second access terminal is coupled to a first terminal of a two terminal resistive switching device. The resistive switching device has the first terminal and a second terminal. The resistive switching device has a first state and a second state. The pulse includes a first ramp from a first voltage to a second voltage over a first time period, a second ramp from the second voltage to a third voltage over a second time period, and a third ramp from the third voltage to a fourth voltage over a third time period. The second ramp and the third ramp have an opposite slope to the first ramp. The sum of the first time period and the second time period is less than the third time period.

8. 发明授权

US09305643B2 Solid electrolyte based memory devices and methods having adaptable read threshold levels 有权
标题翻译：基于固体电解质的存储器件和具有适应性读取阈值水平的方法
公开(公告)号：US09305643B2
公开(公告)日：2016-04-05
申请号：US13851011
申请日：2013-03-26
申请人： Adesto Technologies Corporation
发明人： Venkatesh P. Gopinath , Foroozan Sarah Koushan , Derric Jawaher Herman Lewis
IPC分类号： G11C13/00 , G11C11/56 , G11C16/28
CPC分类号： G11C13/004 , G11C11/5614 , G11C13/0011 , G11C13/0035 , G11C13/0064 , G11C13/0069 , G11C16/28
摘要： A method can include determining at least one use characteristic for the memory cells comprising a solid electrolyte, the use characteristic corresponding to a number of times the memory cells have been programmed to at least one impedance level; and adjusting a read threshold level for the memory cells based on at least the use characteristic, the read threshold level determining data values stored in the memory cells in a read operation.
摘要翻译：一种方法可以包括确定包括固体电解质的存储单元的至少一个使用特性，所述使用特性对应于存储器单元已被编程至少一个阻抗水平的次数; 以及至少基于所述使用特性来调整所述存储器单元的读取阈值电平，所述读取阈值电平确定在读取操作中存储在所述存储器单元中的数据值。

9. 发明授权

US09252359B2 Resistive switching devices having a switching layer and an intermediate electrode layer and methods of formation thereof 有权
标题翻译：具有开关层和中间电极层的电阻式开关器件及其形成方法
公开(公告)号：US09252359B2
公开(公告)日：2016-02-02
申请号：US13829941
申请日：2013-03-14
申请人： Adesto Technologies Corporation
发明人： John R. Jameson, III , John E. Sanchez , Wei Ti Lee , Foroozan Sarah Koushan
IPC分类号： H01L47/00 , H01L45/00 , H01L27/24
CPC分类号： H01L45/1625 , H01L27/2409 , H01L27/2463 , H01L45/08 , H01L45/1233 , H01L45/1253 , H01L45/146 , H01L45/16 , H01L45/165
摘要： In one embodiment of the present invention, a resistive switching device includes a first electrode disposed over a substrate and coupled to a first potential node, a switching layer disposed over the first electrode, a conductive amorphous layer disposed over the switching layer, and a second electrode disposed on the conductive amorphous layer and coupled to a second potential node.
摘要翻译：在本发明的一个实施例中，电阻式开关器件包括设置在衬底上并耦合到第一电位节点的第一电极，设置在第一电极上的开关层，设置在开关层上的导电非晶层，以及第二电极电极，其设置在导电非晶层上并且耦合到第二电位节点。

10. 发明申请

US20140246641A1 Resistive Switching Devices Having a Switching Layer And An Intermediate Electrode Layer and Methods of Formation Thereof 有权
标题翻译：具有开关层和中间电极层的电阻式开关器件及其形成方法
公开(公告)号：US20140246641A1
公开(公告)日：2014-09-04
申请号：US13829941
申请日：2013-03-14
申请人： ADESTO TECHNOLOGIES CORPORATION
发明人： John R. Jameson, III , John E. Sanchez , Wei Ti Lee , Yi Ma , Venkatesh P. Gopinath , Foroozan Sarah Koushan
IPC分类号： H01L45/00
CPC分类号： H01L45/1625 , H01L27/2409 , H01L27/2463 , H01L45/08 , H01L45/1233 , H01L45/1253 , H01L45/146 , H01L45/16 , H01L45/165
摘要： In one embodiment of the present invention, a resistive switching device includes a first electrode disposed over a substrate and coupled to a first potential node, a switching layer disposed over the first electrode, a conductive amorphous layer disposed over the switching layer, and a second electrode disposed on the conductive amorphous layer and coupled to a second potential node.
摘要翻译：在本发明的一个实施例中，电阻式开关装置包括设置在衬底上并耦合到第一电位节点的第一电极，设置在第一电极上的开关层，设置在开关层上的导电非晶层，以及第二电极电极，其设置在导电非晶层上并且耦合到第二电位节点。

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