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1. 发明授权

US08473812B2 Method and system for error correction in flash memory 有权
标题翻译：闪存中纠错方法和系统
公开(公告)号：US08473812B2
公开(公告)日：2013-06-25
申请号：US12946520
申请日：2010-11-15
申请人： Aditya Ramamoorthy , Zining Wu , Pantas Sutardja
发明人： Aditya Ramamoorthy , Zining Wu , Pantas Sutardja
IPC分类号： H03M13/00
CPC分类号： G06F11/1068 , G06F11/1072 , G06F11/1666 , G06F2212/403 , G11C7/02 , G11C7/1006 , G11C7/16 , G11C11/56 , G11C11/5621 , G11C16/10 , G11C27/005 , G11C29/00 , G11C2029/0411 , G11C2207/16 , G11C2211/562 , G11C2211/563 , H03M13/1177 , H03M13/1515
摘要： A multi-level solid state non-volatile memory array has memory cells that store data using a first number of digital levels. A controller of the memory array encodes a series of data bits to generate a series of encoded data bits, and converts the series of encoded data bits into a series of data symbols. The controller sends, to the memory array, a stored series of data symbols based on the series of data symbols for storage in a memory cell of the multi-level solid state non-volatile memory array. The controller generates an output signal based on data associated with the stored series of data symbols. The output signal is characterized by a second number of digital levels greater than the first number of digital levels. The controller outputs a series of output data symbols based on the output signal.
摘要翻译：多级固态非易失性存储器阵列具有使用第一数字级别存储数据的存储器单元。存储器阵列的控制器对一系列数据位进行编码以产生一系列编码数据位，并将该系列编码数据位转换为一系列数据符号。控制器基于用于存储在多级固态非易失性存储器阵列的存储单元中的一系列数据符号将存储的一系列数据符号发送到存储器阵列。控制器基于与所存储的一系列数据符号相关联的数据产生输出信号。输出信号的特征在于大于数字电平的第一数量的第二数字电平。控制器根据输出信号输出一系列输出数据符号。

2. 发明授权

US08363501B1 Method and apparatus for calibrating a read/write channel in a memory arrangement 有权
公开(公告)号：US08363501B1
公开(公告)日：2013-01-29
申请号：US13099997
申请日：2011-05-03
申请人： Aditya Ramamoorthy , Gregory Burd , Xueshi Yang
发明人： Aditya Ramamoorthy , Gregory Burd , Xueshi Yang
IPC分类号： G11C7/02
CPC分类号： G11C7/02 , G11C11/5621 , G11C11/5628 , G11C11/5642 , G11C11/5671 , G11C11/5678 , G11C13/0004 , G11C13/0033 , G11C13/0069 , G11C29/00
摘要： A memory arrangement including a memory block and a controller. The memory block comprises a plurality of memory cells, wherein each memory cell operable to store one of a plurality of different levels of charge. The controller is configured to write (i) a first reference signal threshold into a first memory cell and (ii) a second reference signal threshold into a second memory cell. The first reference signal threshold corresponds to a first level of charge of the plurality of different levels of charge, and the second reference signal threshold corresponds to a second level of charge of the plurality of different levels of charge. Each of the first level of charge and the second level of charge is used to calibrate a read back of any of the one of the plurality of different levels of charge stored among the plurality of memory cells in the memory block.

3. 发明授权

US08281213B1 LDPC codes and expansion method 有权
标题翻译： LDPC码和扩展方法
公开(公告)号：US08281213B1
公开(公告)日：2012-10-02
申请号：US12852817
申请日：2010-08-09
申请人： Adina Matache , Heng Tang , Gregory Burd , Aditya Ramamoorthy , Jun Xu , Zining Wu
发明人： Adina Matache , Heng Tang , Gregory Burd , Aditya Ramamoorthy , Jun Xu , Zining Wu
IPC分类号： H03M13/00
CPC分类号： H03M13/1177 , H03M13/116 , H03M13/1188
摘要： A multiple-input multiple-output (MIMO) transmitter including a scrambler and a forward error correction encoder. The scrambler is configured to receive user data and generate scrambled data in response to the user data. The forward error correction encoder is configured to generate encoded data, in response to the scrambled data, using a low density parity check (LDPC) matrix, wherein the LDPC matrix is derived from a specified base matrix.
摘要翻译：一种包括扰频器和前向纠错编码器的多输入多输出（MIMO）发射机。加扰器被配置为接收用户数据并响应于用户数据产生加扰数据。前向纠错编码器被配置为使用低密度奇偶校验（LDPC）矩阵来响应于加扰的数据生成编码数据，其中从指定的基本矩阵导出LDPC矩阵。

4. 发明申请

US20070171730A1 Method and system for error correction in flash memory 有权
标题翻译：闪存中纠错方法和系统
公开(公告)号：US20070171730A1
公开(公告)日：2007-07-26
申请号：US11598117
申请日：2006-11-08
申请人： Aditya Ramamoorthy , Zining Wu , Pantas Sutardja
发明人： Aditya Ramamoorthy , Zining Wu , Pantas Sutardja
IPC分类号： G11C16/04
CPC分类号： G06F11/1068 , G06F11/1072 , G06F11/1666 , G06F2212/403 , G11C7/02 , G11C7/1006 , G11C7/16 , G11C11/56 , G11C11/5621 , G11C16/10 , G11C27/005 , G11C29/00 , G11C2029/0411 , G11C2207/16 , G11C2211/562 , G11C2211/563 , H03M13/1177 , H03M13/1515
摘要： A solid state non-volatile memory unit. The memory unit includes a multi-level solid state non-volatile memory array adapted to store data characterized by a first number of digital levels. The memory unit also includes an analog-to-digital converter having an input and an output. The input of the analog-to-digital converter is adapted to receive data from the multi-level solid state non-volatile memory array. The output of the analog-to-digital converter is adapted to output a digital signal characterized by a second number of digital levels greater than the first number of digital levels.
摘要翻译：固态非易失性存储器单元。存储器单元包括适于存储由第一数字级别表征的数据的多级固态非易失性存储器阵列。存储器单元还包括具有输入和输出的模拟 - 数字转换器。模拟 - 数字转换器的输入适于从多级固态非易失性存储器阵列接收数据。模拟 - 数字转换器的输出适于输出特征在于数字电平大于第一数字电平数量的第二数字电平的数字信号。

5. 发明授权

US08489960B1 LDPC codes and expansion method 有权
标题翻译： LDPC码和扩展方法
公开(公告)号：US08489960B1
公开(公告)日：2013-07-16
申请号：US13614065
申请日：2012-09-13
申请人： Adina Matache , Heng Tang , Gregory Burd , Aditya Ramamoorthy , Jun Xu , Zining Wu
发明人： Adina Matache , Heng Tang , Gregory Burd , Aditya Ramamoorthy , Jun Xu , Zining Wu
IPC分类号： H03M13/00
CPC分类号： H03M13/1177 , H03M13/116 , H03M13/1188
摘要： A communications device including a low-density parity check (LDPC) encoder and a transmitter. The LDPC encoder is configured to (i) receive data, and (ii) in response to the received data, generate encoded data using a predetermined LDPC matrix, in which the predetermined LDPC matrix is specified by a predetermined base matrix. The transmitter is configured to transmit the encoded data over a communications channel.
摘要翻译：一种包括低密度奇偶校验（LDPC）编码器和发射机的通信设备。 LDPC编码器被配置为（i）接收数据，并且（ii）响应于所接收的数据，使用预定的LDPC矩阵来生成编码数据，其中预定的LDPC矩阵由预定的基本矩阵指定。发射机被配置为通过通信信道发送编码数据。

6. 发明授权

US07904792B2 Apparatus and method for transmitting/receiving signal in a communication system 有权
标题翻译：在通信系统中发送/接收信号的装置和方法
公开(公告)号：US07904792B2
公开(公告)日：2011-03-08
申请号：US11603585
申请日：2006-11-22
申请人： Dong-Ho Kim , Jaehong Kim , Aditya Ramamoorthy , Steven W. McLaughlin
发明人： Dong-Ho Kim , Jaehong Kim , Aditya Ramamoorthy , Steven W. McLaughlin
IPC分类号： H03M13/35
CPC分类号： H03M13/1102 , H03M13/033 , H03M13/6362 , H03M13/6393
摘要： In a communication system, a signal transmission apparatus includes an encoder for encoding an information vector into a low density parity check (LDPC) codeword with an LDPC coding scheme, and a puncturer for puncturing the LDPC codeword according to a coding rate using a puncturing scheme. A signal reception apparatus includes a ‘0’ inserter for inserting ‘0’ symbols in a received signal according to a coding rate used in a signal transmission apparatus, and a decoder for decoding the ‘0’ symbol-inserted signal with a decoding scheme corresponding to a low density parity check (LDPC) coding scheme used in the signal transmission apparatus, thereby detecting an information vector.
摘要翻译：在通信系统中，信号传输装置包括：编码器，用于将信息矢量编码为具有LDPC编码方案的低密度奇偶校验（LDPC）码字;以及穿孔器，用于使用穿孔方案根据编码率对所述LDPC码字进行穿孔。信号接收装置包括：根据在信号发送装置中使用的编码率在接收信号中插入“0”符号的“0”插入器，以及用于对应于解码方案对应的“0”符号插入信号进行解码的解码器涉及在信号发送装置中使用的低密度奇偶校验（LDPC）编码方案，从而检测信息向量。

7. 发明授权

US07844879B2 Method and system for error correction in flash memory 有权
标题翻译：闪存中纠错方法和系统
公开(公告)号：US07844879B2
公开(公告)日：2010-11-30
申请号：US11598117
申请日：2006-11-08
申请人： Aditya Ramamoorthy , Zining Wu , Pantas Sutardja
发明人： Aditya Ramamoorthy , Zining Wu , Pantas Sutardja
IPC分类号： G11C29/00
CPC分类号： G06F11/1068 , G06F11/1072 , G06F11/1666 , G06F2212/403 , G11C7/02 , G11C7/1006 , G11C7/16 , G11C11/56 , G11C11/5621 , G11C16/10 , G11C27/005 , G11C29/00 , G11C2029/0411 , G11C2207/16 , G11C2211/562 , G11C2211/563 , H03M13/1177 , H03M13/1515
摘要： A solid state non-volatile memory unit. The memory unit includes a multi-level solid state non-volatile memory array adapted to store data characterized by a first number of digital levels. The memory unit also includes an analog-to-digital converter having an input and an output. The input of the analog-to-digital converter is adapted to receive data from the multi-level solid state non-volatile memory array. The output of the analog-to-digital converter is adapted to output a digital signal characterized by a second number of digital levels greater than the first number of digital levels.
摘要翻译：固态非易失性存储器单元。存储器单元包括适于存储由第一数字级别表征的数据的多级固态非易失性存储器阵列。存储器单元还包括具有输入和输出的模拟 - 数字转换器。模拟 - 数字转换器的输入适于从多级固态非易失性存储器阵列接收数据。模拟 - 数字转换器的输出适于输出特征在于数字电平大于第一数字电平数量的第二数字电平的数字信号。

8. 发明授权

US07774675B1 LDPC codes and expansion method 有权
标题翻译： LDPC码和扩展方法
公开(公告)号：US07774675B1
公开(公告)日：2010-08-10
申请号：US11481141
申请日：2006-07-05
申请人： Adina Matache , Heng Tang , Gregory Burd , Aditya Ramamoorthy , Jun Xu , Zining Wu
发明人： Adina Matache , Heng Tang , Gregory Burd , Aditya Ramamoorthy , Jun Xu , Zining Wu
IPC分类号： H03M13/00
CPC分类号： H03M13/1177 , H03M13/116 , H03M13/1188
摘要： A MIMO transmitter comprises a scrambler; an encoder parser responsive to the scrambler; a forward error correction encoder responsive to the encoder parser, wherein the encoder applies a parity check matrix derived from a base matrix; an interleaver responsive to the forward error correction encoder; a QAM mapping module responsive to the interleaver; an inverse fast Fourier transform module responsive to the QAM mapping module; and an output module responsive to the inverse fast Fourier transform module.
摘要翻译： MIMO发射机包括扰频器; 响应于扰频器的编码器解析器; 响应于所述编码器解析器的前向纠错编码器，其中所述编码器应用从基本矩阵导出的奇偶校验矩阵; 响应于前向纠错编码器的交织器; 响应于交织器的QAM映射模块; 响应于QAM映射模块的快速傅立叶逆变换模块; 以及响应快速傅立叶逆变换模块的输出模块。

9. 发明申请

US20070245214A1 MULTI-LEVEL SIGNAL MEMORY WITH LDPC AND INTERLEAVING 有权
标题翻译：具有LDPC和交互的多级信号存储器
公开(公告)号：US20070245214A1
公开(公告)日：2007-10-18
申请号：US11627250
申请日：2007-01-25
申请人： Aditya Ramamoorthy
发明人： Aditya Ramamoorthy
IPC分类号： H03M13/00
CPC分类号： H03M13/255 , G06F11/1072 , G11C11/5621 , H03M13/11
摘要： Embodiments of the present invention provide multi-level signal memory with LDPC and interleaving. Thus, various embodiments of the present invention provide a memory apparatus that includes a memory block comprising a plurality of memory cells, each memory cell adapted to operate with multi-level signals. Such a memory apparatus also includes a low density parity check (LDPC) coder to LDPC code data values to be written into the memory cells and an interleaver adapted to apply bit interleaved code modulation (BICM) to the LDPC coded data values to generate BICM coded data values. Other embodiments may be described and claimed.
摘要翻译：本发明的实施例提供具有LDPC和交织的多级信号存储器。因此，本发明的各种实施例提供一种存储装置，其包括包括多个存储单元的存储块，每个存储单元适于与多电平信号一起工作。这种存储装置还包括：低密度奇偶校验（LDPC）编码器，用于将要写入存储单元的数据值LDPC编码;以及适用于对LDPC编码数据值应用位交织码调制（BICM）的交织器，以生成BICM编码数据值。可以描述和要求保护其他实施例。

10. 发明授权

US08583991B1 High density multi-level memory 有权
标题翻译：高密度多级存储器
公开(公告)号：US08583991B1
公开(公告)日：2013-11-12
申请号：US13542353
申请日：2012-07-05
申请人： Pantas Sutardja , Zining Wu , Toai Doan , Aditya Ramamoorthy
发明人： Pantas Sutardja , Zining Wu , Toai Doan , Aditya Ramamoorthy
IPC分类号： G06F11/00
CPC分类号： G06F11/1072 , G11C7/1006 , G11C11/5621 , G11C11/5628 , G11C11/5642 , G11C2029/0411
摘要： Embodiments of the present invention provide high density, multi-level memory. Thus, various embodiments of the present invention provide a memory apparatus in accordance with various embodiments of the present invention includes a memory block comprising a plurality of cells, each cell adapted to operate with multi-level signal. Such a memory apparatus also includes a channel block adapted to code data values in accordance with a coding scheme that favorably effects a distribution of the multi-levels of the multi-level signals, and to output the corresponding multi-level signals of the coded data values to the memory block. Other embodiments may be described and claimed.
摘要翻译：本发明的实施例提供了高密度，多级存储器。因此，本发明的各种实施例提供了根据本发明的各种实施例的存储器装置，其包括包括多个单元的存储器块，每个单元适于用多电平信号进行操作。这种存储装置还包括适于根据有利地实现多电平信号的多电平分布的编码方案对数据值进行编码的信道块，并且输出编码数据的相应多电平信号值到内存块。可以描述和要求保护其他实施例。

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