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1. 发明授权

US08031954B2 Image encoding apparatus and control method thereof using prediction encoding and pixel classification 有权
标题翻译：图像编码装置及其使用预测编码和像素分类的控制方法
公开(公告)号：US08031954B2
公开(公告)日：2011-10-04
申请号：US12107844
申请日：2008-04-23
申请人： Akio Nakagawa , Hisashi Ishikawa , Ryoko Mise
发明人： Akio Nakagawa , Hisashi Ishikawa , Ryoko Mise
IPC分类号： G06K9/36 , G06K9/46
CPC分类号： H04N19/93 , H04N19/102 , H04N19/105 , H04N19/12 , H04N19/146 , H04N19/17 , H04N19/176 , H04N19/182 , H04N19/186 , H04N19/593 , H04N19/60
摘要： According to this invention, encoded data are generated by sorting pixel data in a block according to different scan start positions and different scan routes upon generating encoded data for respective blocks, and encoded data with a smallest data amount of these encoded data is outputted. To this end, a block generation unit inputs blocks each defined by 8×8 pixels from image data to be encoded. Four encoding processing units respectively sort inputted 8×8 pixels according to the information stored in scan start position information storage units and scan route information storage units. The respective encoding processing units generate encoded data based on the sorted pixel data. A selector selects and outputs encoded data with a smallest data size from those generated by the encoding processing units.
摘要翻译：根据本发明，通过根据不同的扫描开始位置和不同的扫描路径对块中的像素数据进行排序，生成编码数据，生成各个块的编码数据，并输出这些编码数据的最小数据量的编码数据。为此，块生成单元从要编码的图像数据输入由8×8像素定义的块。四个编码处理单元根据存储在扫描开始位置信息存储单元和扫描路径信息存储单元中的信息分别输入8×8像素。相应的编码处理单元基于分类的像素数据生成编码数据。选择器选择并输出具有由编码处理单元生成的数据的最小数据大小的编码数据。

2. 发明申请

US20080292197A1 IMAGE ENCODING APPARATUS AND CONTROL METHOD THEREOF 有权
标题翻译：图像编码装置及其控制方法
公开(公告)号：US20080292197A1
公开(公告)日：2008-11-27
申请号：US12107844
申请日：2008-04-23
申请人： Akio Nakagawa , Hisashi Ishikawa , Ryoko Mise
发明人： Akio Nakagawa , Hisashi Ishikawa , Ryoko Mise
IPC分类号： G06K9/36
CPC分类号： H04N19/93 , H04N19/102 , H04N19/105 , H04N19/12 , H04N19/146 , H04N19/17 , H04N19/176 , H04N19/182 , H04N19/186 , H04N19/593 , H04N19/60
摘要： According to this invention, encoded data are generated by sorting pixel data in a block according to different scan start positions and different scan routes upon generating encoded data for respective blocks, and encoded data with a smallest data amount of these encoded data is outputted. To this end, a block generation unit inputs blocks each defined by 8×8 pixels from image data to be encoded. Four encoding processing units respectively sort inputted 8×8 pixels according to the information stored in scan start position information storage units and scan route information storage units. The respective encoding processing units generate encoded data based on the sorted pixel data. A selector selects and outputs encoded data with a smallest data size from those generated by the encoding processing units.
摘要翻译：根据本发明，通过根据不同的扫描开始位置和不同的扫描路径对块中的像素数据进行排序，生成编码数据，生成各个块的编码数据，并输出这些编码数据的最小数据量的编码数据。为此，块生成单元从要编码的图像数据输入由8×8像素定义的块。四个编码处理单元根据存储在扫描开始位置信息存储单元和扫描路径信息存储单元中的信息分别输入8×8像素。相应的编码处理单元基于分类的像素数据生成编码数据。选择器选择并输出具有由编码处理单元生成的数据的最小数据大小的编码数据。

3. 发明申请

US20110134443A1 DATA PROCESSING APPARATUS, IMAGE PROCESSING APPARATUS, AND METHOD THEREFOR 有权
标题翻译：数据处理设备，图像处理设备及其方法
公开(公告)号：US20110134443A1
公开(公告)日：2011-06-09
申请号：US13019122
申请日：2011-02-01
申请人： Hisashi Ishikawa , Ryoko Mise
发明人： Hisashi Ishikawa , Ryoko Mise
IPC分类号： G06K15/02
CPC分类号： G06T3/4092 , G06T1/20 , Y10S707/99932 , Y10S707/99936
摘要： There are provided a data processing apparatus which makes an I/F for data processing modules (processors) versatile to facilitate addition/modification on a data processing module basis in accordance with processing contents, an image processing apparatus, and a method for the apparatuses. A data processing module (3) includes a read address generator (11), read FIFO (7), write address generator (13), write FIFO (9), and arbiter (10) and is connected to a host arbiter (4) through a 1-channel port. The read address generator (11) and write address generator (13) generate interrupts upon acceptance of final access requests so as to control activation of each data processing module (8-1-8-m) in accordance with the state of each data processing module in interrupt processing. Note that data transfer among the respective data processing modules is performed on a RAM (6).
摘要翻译：提供了一种数据处理装置，其根据处理内容，图像处理装置和方法为数据处理模块提供通用的数据处理模块（处理器）的I / F，以便于对数据处理模块的添加/修改。数据处理模块（3）包括读地址生成器（11），读FIFO（7），写地址生成器（13），写FIFO（9）和仲裁器（10），并连接到主仲裁器（4）通过一个1通道端口。读取地址生成器（11）和写入地址生成器（13）在接受最终访问请求时产生中断，以便根据每个数据处理的状态来控制每个数据处理模块（8-1-8-m）的激活模块中断处理。注意，在RAM（6）中执行各个数据处理模块之间的数据传送。

4. 发明授权

US07899275B2 Data processing apparatus, image processing apparatus, and method therefor 有权
标题翻译：数据处理装置，图像处理装置及其方法
公开(公告)号：US07899275B2
公开(公告)日：2011-03-01
申请号：US12430014
申请日：2009-04-24
申请人： Hisashi Ishikawa , Ryoko Mise
发明人： Hisashi Ishikawa , Ryoko Mise
IPC分类号： G06K9/60
CPC分类号： G06T3/4092 , G06T1/20 , Y10S707/99932 , Y10S707/99936
摘要： There are provided a data processing apparatus which makes an I/F for data processing modules (processors) versatile to facilitate addition/modification on a data processing module basis in accordance with processing contents, an image processing apparatus, and a method for the apparatuses. A data processing module (3) includes a read address generator (11), read FIFO (7), write address generator (13), write FIFO (9), and arbiter (10) and is connected to a host arbiter (4) through a 1-channel port. The read address generator (11) and write address generator (13) generate interrupts upon acceptance of final access requests so as to control activation of each data processing module (8-1-8-m) in accordance with the state of each data processing module in interrupt processing. Note that data transfer among the respective data processing modules is performed on a RAM (6).
摘要翻译：提供了一种数据处理装置，其根据处理内容，图像处理装置和方法为数据处理模块提供通用的数据处理模块（处理器）的I / F，以便于对数据处理模块的添加/修改。数据处理模块（3）包括读地址生成器（11），读FIFO（7），写地址生成器（13），写FIFO（9）和仲裁器（10），并连接到主仲裁器（4）通过一个1通道端口。读取地址生成器（11）和写入地址生成器（13）在接受最终访问请求时产生中断，以便根据每个数据处理的状态来控制每个数据处理模块（8-1-8-m）的激活模块中断处理。注意，在RAM（6）中执行各个数据处理模块之间的数据传送。

5. 发明申请

US20090208139A1 DATA PROCESSING APPARATUS, IMAGE PROCESSING APPARATUS, AND METHOD THEREFOR 有权
公开(公告)号：US20090208139A1
公开(公告)日：2009-08-20
申请号：US12430014
申请日：2009-04-24
申请人： Hisashi Ishikawa , Ryoko Mise
发明人： Hisashi Ishikawa , Ryoko Mise
IPC分类号： G06K9/54
CPC分类号： G06T3/4092 , G06T1/20 , Y10S707/99932 , Y10S707/99936
摘要： There are provided a data processing apparatus which makes an I/F for data processing modules (processors) versatile to facilitate addition/modification on a data processing module basis in accordance with processing contents, an image processing apparatus, and a method for the apparatuses. A data processing module (3) includes a read address generator (11), read FIFO (7), write address generator (13), write FIFO (9), and arbiter (10) and is connected to a host arbiter (4) through a 1-channel port. The read address generator (11) and write address generator (13) generate interrupts upon acceptance of final access requests so as to control activation of each data processing module (8-1-8-m) in accordance with the state of each data processing module in interrupt processing. Note that data transfer among the respective data processing modules is performed on a RAM (6).

6. 发明申请

US20090202161A1 DATA PROCESSING APPARATUS, IMAGE PROCESSING APPARATUS, AND METHOD THEREFOR 有权
标题翻译：数据处理设备，图像处理设备及其方法
公开(公告)号：US20090202161A1
公开(公告)日：2009-08-13
申请号：US12430735
申请日：2009-04-27
申请人： Hisashi Ishikawa , Ryoko Mise
发明人： Hisashi Ishikawa , Ryoko Mise
IPC分类号： G06K9/36 , G06K9/54
CPC分类号： G06T3/4092 , G06T1/20 , Y10S707/99932 , Y10S707/99936
摘要： There are provided a data processing apparatus which makes an I/F for data processing modules (processors) versatile to facilitate addition/modification on a data processing module basis in accordance with processing contents, an image processing apparatus, and a method for the apparatuses. A data processing module (3) includes a read address generator (11), read FIFO (7), write address generator (13), write FIFO (9), and arbiter (10) and is connected to a host arbiter (4) through a 1-channel port. The read address generator (11) and write address generator (13) generate interrupts upon acceptance of final access requests so as to control activation of each data processing module (8-1-8-m) in accordance with the state of each data processing module in interrupt processing. Note that data transfer among the respective data processing modules is performed on a RAM (6).
摘要翻译：提供了一种数据处理装置，其根据处理内容，图像处理装置和方法为数据处理模块提供通用的数据处理模块（处理器）的I / F，以便于对数据处理模块的添加/修改。数据处理模块（3）包括读地址生成器（11），读FIFO（7），写地址生成器（13），写FIFO（9）和仲裁器（10），并连接到主仲裁器（4）通过一个1通道端口。读取地址生成器（11）和写入地址生成器（13）在接受最终访问请求时产生中断，以便根据每个数据处理的状态来控制每个数据处理模块（8-1-8-m）的激活模块中断处理。注意，在RAM（6）中执行各个数据处理模块之间的数据传送。

7. 发明申请

US20120170871A1 DATA PROCESSING APPARATUS, IMAGE PROCESSING APPARATUS, AND METHOD THEREFOR 有权
标题翻译：数据处理设备，图像处理设备及其方法
公开(公告)号：US20120170871A1
公开(公告)日：2012-07-05
申请号：US13419376
申请日：2012-03-13
申请人： Hisashi Ishikawa , Ryoko Mise
发明人： Hisashi Ishikawa , Ryoko Mise
IPC分类号： G06K9/60
CPC分类号： G06T3/4092 , G06T1/20 , Y10S707/99932 , Y10S707/99936
摘要： There are provided a data processing apparatus which makes an I/F for data processing modules (processors) versatile to facilitate addition/modification on a data processing module basis in accordance with processing contents, an image processing apparatus, and a method for the apparatuses. A data processing module (3) includes a read address generator (11), read FIFO (7), write address generator (13), write FIFO (9), and arbiter (10) and is connected to a host arbiter (4) through a 1-channel port. The read address generator (11) and write address generator (13) generate interrupts upon acceptance of final access requests so as to control activation of each data processing module (8-1-8-m) in accordance with the state of each data processing module in interrupt processing. Note that data transfer among the respective data processing modules is performed on a RAM (6).
摘要翻译：提供了一种数据处理装置，其根据处理内容，图像处理装置和方法为数据处理模块提供通用的数据处理模块（处理器）的I / F，以便于对数据处理模块的添加/修改。数据处理模块（3）包括读地址生成器（11），读FIFO（7），写地址生成器（13），写FIFO（9）和仲裁器（10），并连接到主仲裁器（4）通过一个1通道端口。读取地址生成器（11）和写入地址生成器（13）在接受最终访问请求时产生中断，以便根据每个数据处理的状态来控制每个数据处理模块（8-1-8-m）的激活模块中断处理。注意，在RAM（6）中执行各个数据处理模块之间的数据传送。

8. 发明授权

US08165427B2 Data processing apparatus, image processing apparatus, and method therefor 有权
标题翻译：数据处理装置，图像处理装置及其方法
公开(公告)号：US08165427B2
公开(公告)日：2012-04-24
申请号：US13019122
申请日：2011-02-01
申请人： Hisashi Ishikawa , Ryoko Mise
发明人： Hisashi Ishikawa , Ryoko Mise
IPC分类号： G06K9/60
CPC分类号： G06T3/4092 , G06T1/20 , Y10S707/99932 , Y10S707/99936
摘要： There are provided a data processing apparatus which makes an I/F for data processing modules (processors) versatile to facilitate addition/modification on a data processing module basis in accordance with processing contents, an image processing apparatus, and a method for the apparatuses. A data processing module (3) includes a read address generator (11), read FIFO (7), write address generator (13), write FIFO (9), and arbiter (10) and is connected to a host arbiter (4) through a 1-channel port. The read address generator (11) and write address generator (13) generate interrupts upon acceptance of final access requests so as to control activation of each data processing module (8-1-8-m) in accordance with the state of each data processing module in interrupt processing. Note that data transfer among the respective data processing modules is performed on a RAM (6).
摘要翻译：提供了一种数据处理装置，其根据处理内容，图像处理装置和方法为数据处理模块提供通用的数据处理模块（处理器）的I / F，以便于对数据处理模块的添加/修改。数据处理模块（3）包括读地址生成器（11），读FIFO（7），写地址生成器（13），写FIFO（9）和仲裁器（10），并连接到主仲裁器（4）通过一个1通道端口。读取地址生成器（11）和写入地址生成器（13）在接受最终访问请求时产生中断，以便根据每个数据处理的状态来控制每个数据处理模块（8-1-8-m）的激活模块中断处理。注意，在RAM（6）中执行各个数据处理模块之间的数据传送。

9. 发明授权

US07889935B2 Data processing apparatus, image processing apparatus, and method therefor 有权
公开(公告)号：US07889935B2
公开(公告)日：2011-02-15
申请号：US12430735
申请日：2009-04-27
申请人： Hisashi Ishikawa , Ryoko Mise
发明人： Hisashi Ishikawa , Ryoko Mise
IPC分类号： G06K9/40
CPC分类号： G06T3/4092 , G06T1/20 , Y10S707/99932 , Y10S707/99936
摘要： There are provided a data processing apparatus which makes an I/F for data processing modules (processors) versatile to facilitate addition/modification on a data processing module basis in accordance with processing contents, an image processing apparatus, and a method for the apparatuses. A data processing module (3) includes a read address generator (11), read FIFO (7), write address generator (13), write FIFO (9), and arbiter (10) and is connected to a host arbiter (4) through a 1-channel port. The read address generator (11) and write address generator (13) generate interrupts upon acceptance of final access requests so as to control activation of each data processing module (8-1-8-m) in accordance with the state of each data processing module in interrupt processing. Note that data transfer among the respective data processing modules is performed on a RAM (6).

10. 发明授权

US07266254B2 Data processing apparatus, image processing apparatus, and method therefor 有权
公开(公告)号：US07266254B2
公开(公告)日：2007-09-04
申请号：US10365551
申请日：2003-02-13
申请人： Hisashi Ishikawa , Ryoko Mise
发明人： Hisashi Ishikawa , Ryoko Mise
IPC分类号： G06K9/54
CPC分类号： G06T3/4092 , G06T1/20 , Y10S707/99932 , Y10S707/99936
摘要： There are provided a data processing apparatus which makes an I/F for data processing modules (processors) versatile to facilitate addition/modification on a data processing module basis in accordance with processing contents, an image processing apparatus, and a method for the apparatuses. A data processing module (3) includes a read address generator (11), read FIFO (7), write address generator (13), write FIFO (9), and arbiter (10) and is connected to a host arbiter (4) through a 1-channel port. The read address generator (11) and write address generator (13) generate interrupts upon acceptance of final access requests so as to control activation of each data processing module (8-1-8-m) in accordance with the state of each data processing module in interrupt processing. Note that data transfer among the respective data processing modules is performed on a RAM (6).

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