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1. 发明授权

US07949909B2 Address controlling in the MBIST chain architecture 有权
标题翻译：地址控制在MBIST链架构
公开(公告)号：US07949909B2
公开(公告)日：2011-05-24
申请号：US12183562
申请日：2008-07-31
申请人： Alexandre Andreev , Anatoli Bolotov , Mikhail Grinchuk
发明人： Alexandre Andreev , Anatoli Bolotov , Mikhail Grinchuk
IPC分类号： G11C29/00 , G01R31/28
CPC分类号： G11C29/32 , G11C8/16 , G11C2029/3202
摘要： A memory collar includes a first circuit, a second circuit and a third circuit. The first circuit may be configured to generate a first control signal, a second control signal and a third control signal in response to one or more test commands. The second circuit may be configured to generate a fourth control signal in response to said third control signal and the fourth control signal. The third circuit may be configured to generate one or more address sequences. The one or more address sequences are presented to a memory during a test mode.
摘要翻译：存储器环包括第一电路，第二电路和第三电路。第一电路可以被配置为响应于一个或多个测试命令产生第一控制信号，第二控制信号和第三控制信号。第二电路可以被配置为响应于所述第三控制信号和第四控制信号而产生第四控制信号。第三电路可以被配置为生成一个或多个地址序列。在测试模式期间将一个或多个地址序列呈现给存储器。

2. 发明授权

US08156391B2 Data controlling in the MBIST chain architecture 失效
标题翻译： MBIST链架构中的数据控制
公开(公告)号：US08156391B2
公开(公告)日：2012-04-10
申请号：US12167305
申请日：2008-07-03
申请人： Alexandre Andreev , Anatoli Bolotov , Mikhail Grinchuk
发明人： Alexandre Andreev , Anatoli Bolotov , Mikhail Grinchuk
IPC分类号： G11C29/14 , G11C29/50
CPC分类号： G11C29/32 , G11C8/16 , G11C2029/3202
摘要： A memory collar including a first circuit and a second circuit. The first circuit may be configured to generate one or more data sequences in response to one or more test commands. The one or more data sequences may be presented to a memory during a test mode. The second circuit may be configured to pre-process one or more outputs generated by the memory in response to the one or more data sequences.
摘要翻译：一种包括第一电路和第二电路的存储器环。第一电路可以被配置为响应于一个或多个测试命令而生成一个或多个数据序列。在测试模式期间，可以将一个或多个数据序列呈现给存储器。第二电路可以被配置为响应于一个或多个数据序列预处理由存储器产生的一个或多个输出。

3. 发明申请

US20090300441A1 ADDRESS CONTROLLING IN THE MBIST CHAIN ARCHITECTURE 有权
标题翻译：地址控制在MBIST链建筑
公开(公告)号：US20090300441A1
公开(公告)日：2009-12-03
申请号：US12183562
申请日：2008-07-31
申请人： Alexandre Andreev , Anatoli Bolotov , Mikhail Grinchuk
发明人： Alexandre Andreev , Anatoli Bolotov , Mikhail Grinchuk
IPC分类号： G11C29/12 , G06F11/27
CPC分类号： G11C29/32 , G11C8/16 , G11C2029/3202
摘要： A memory collar includes a first circuit, a second circuit and a third circuit. The first circuit may be configured to generate a first control signal, a second control signal and a third control signal in response to one or more test commands. The second circuit may be configured to generate a fourth control signal in response to said third control signal and the fourth control signal. The third circuit may be configured to generate one or more address sequences. The one or more address sequences are presented to a memory during a test mode.
摘要翻译：存储器环包括第一电路，第二电路和第三电路。第一电路可以被配置为响应于一个或多个测试命令产生第一控制信号，第二控制信号和第三控制信号。第二电路可以被配置为响应于所述第三控制信号和第四控制信号而产生第四控制信号。第三电路可以被配置为生成一个或多个地址序列。在测试模式期间将一个或多个地址序列呈现给存储器。

4. 发明申请

US20090307543A1 TRANSPORT SUBSYSTEM FOR AN MBIST CHAIN ARCHITECTURE 失效
标题翻译：用于MBIST链架构的运输子系统
公开(公告)号：US20090307543A1
公开(公告)日：2009-12-10
申请号：US12183512
申请日：2008-07-31
申请人： Alexandre Andreev , Anatoli Bolotov , Mikhail Grinchuk
发明人： Alexandre Andreev , Anatoli Bolotov , Mikhail Grinchuk
IPC分类号： G11C29/12 , G06F11/27
CPC分类号： G11C29/48 , G11C29/1201 , G11C29/26 , G11C29/32 , G11C2029/2602 , G11C2029/5602
摘要： An apparatus comprising a controller, a plurality of transport circuits and a plurality of memory-controlling circuits. The controller may be configured to (i) present one or more commands and (ii) receive one or more responses. Each of the plurality of transport circuits may be configured to (i) receive one of the commands, (ii) present the responses, and (iii) generate one or more control signals. Each of the plurality of memory-controlling circuits may be (i) coupled to a respective one of the plurality of transport circuits and (ii) configured to (i) generate one or more memory access signals in response to the one or more control signals, (ii) receive one or more memory output signals from a respective memory in response to the one or more memory access signals and (iii) generate the responses in response to the one or more memory output signals. Each respective memory may be independently sized. The controller generally provides a common testing routine for each respective memory that may be adjusted for the size of each respective memory by the memory-controlling circuits.
摘要翻译：一种装置，包括控制器，多个传输电路和多个存储器控制电路。控制器可以被配置为（i）呈现一个或多个命令，并且（ii）接收一个或多个响应。多个传输电路中的每一个可以被配置为（i）接收命令之一，（ii）呈现响应，以及（iii）产生一个或多个控制信号。多个存储器控制电路中的每一个可以（i）耦合到多个传输电路中的相应一个，并且（ii）被配置为（i）响应于一个或多个控制信号而产生一个或多个存储器访问信号，（ii）响应于所述一个或多个存储器访问信号，从相应存储器接收一个或多个存储器输出信号，以及（iii）响应于所述一个或多个存储器输出信号产生响应。各个存储器可以独立地定尺寸。控制器通常为每个相应的存储器提供通用的测试程序，这些存储器可以通过存储器控制电路为每个相应的存储器的大小进行调整。

5. 发明申请

US20090300440A1 DATA CONTROLLING IN THE MBIST CHAIN ARCHITECTURE 失效
标题翻译：在MBIST链架构中的数据控制
公开(公告)号：US20090300440A1
公开(公告)日：2009-12-03
申请号：US12167305
申请日：2008-07-03
申请人： Alexandre Andreev , Anatoli Bolotov , Mikhail Grinchuk
发明人： Alexandre Andreev , Anatoli Bolotov , Mikhail Grinchuk
IPC分类号： G11C29/04 , G06F11/27
CPC分类号： G11C29/32 , G11C8/16 , G11C2029/3202
摘要： A memory collar including a first circuit and a second circuit. The first circuit may be configured to generate one or more data sequences in response to one or more test commands. The one or more data sequences may be presented to a memory during a test mode. The second circuit may be configured to pre-process one or more outputs generated by the memory in response to the one or more data sequences.
摘要翻译：一种包括第一电路和第二电路的存储器环。第一电路可以被配置为响应于一个或多个测试命令而生成一个或多个数据序列。在测试模式期间，可以将一个或多个数据序列呈现给存储器。第二电路可以被配置为响应于一个或多个数据序列预处理由存储器产生的一个或多个输出。

6. 发明授权

US08046643B2 Transport subsystem for an MBIST chain architecture 失效
标题翻译：用于MBIST链架构的传输子系统
公开(公告)号：US08046643B2
公开(公告)日：2011-10-25
申请号：US12183512
申请日：2008-07-31
申请人： Alexandre Andreev , Anatoli Bolotov , Mikhail Grinchuk
发明人： Alexandre Andreev , Anatoli Bolotov , Mikhail Grinchuk
IPC分类号： G11C29/00 , G01R31/28
CPC分类号： G11C29/48 , G11C29/1201 , G11C29/26 , G11C29/32 , G11C2029/2602 , G11C2029/5602
摘要： An apparatus including a controller configured to present one or more commands and receive one or more responses, a plurality of transport circuits configured to receive one of the commands, present the responses, and generate one or more control signals, and a plurality of memory-controlling circuits, each coupled to a respective one of the plurality of transport circuits and configured to generate one or more memory access signals in response to the one or more control signals, receive one or more memory output signals from a respective memory in response to the one or more memory access signals, and generate the responses in response to the one or more memory output signals. Each respective memory may be independently sized. The controller generally provides a common testing routine for each respective memory that may be adjusted for the size of each respective memory by the memory-controlling circuits.
摘要翻译：一种装置，包括：控制器，被配置为呈现一个或多个命令并接收一个或多个响应;多个传输电路，被配置为接收命令中的一个，呈现响应，并产生一个或多个控制信号;以及多个存储器 - 控制电路，每个耦合到所述多个传输电路中的相应一个，并被配置为响应于所述一个或多个控制信号而产生一个或多个存储器访问信号，响应于所述控制电路响应于所述控制电路接收来自相应存储器的一个或多个存储器输出信号一个或多个存储器访问信号，并且响应于一个或多个存储器输出信号而产生响应。各个存储器可以独立地定尺寸。控制器通常为每个相应的存储器提供通用的测试程序，这些存储器可以通过存储器控制电路为每个相应的存储器的大小进行调整。

7. 发明申请

US20110029980A1 LOW DEPTH PROGRAMMABLE PRIORITY ENCODERS 有权
标题翻译：低密度可编程优先编码器
公开(公告)号：US20110029980A1
公开(公告)日：2011-02-03
申请号：US12902376
申请日：2010-10-12
申请人： Mikhail Grinchuk , Anatoli Bolotov , Sergei B. Gashkov , Lav D. Ivanovic
发明人： Mikhail Grinchuk , Anatoli Bolotov , Sergei B. Gashkov , Lav D. Ivanovic
IPC分类号： G06F9/46
CPC分类号： G06F7/74
摘要： An apparatus having a plurality of first circuits, second circuits, third circuits and fourth circuits is disclosed. The first circuits may be configured to generate a plurality of first signals in response to (i) a priority signal and (ii) a request signal. The second circuits may be configured to generate a plurality of second signals in response to the first signals. The third circuits may be configured to generate a plurality of enable signals in response to the second signals. The fourth circuits may be configured to generate collectively an output signal in response to (i) the enable signals and (ii) the request signal. A combination of the first circuits, the second circuits, the third circuits and the fourth circuits generally establishes a programmable priority encoder. The second signals may be generated independent of the enable signals.
摘要翻译：公开了具有多个第一电路，第二电路，第三电路和第四电路的装置。第一电路可以被配置为响应于（i）优先级信号和（ii）请求信号而产生多个第一信号。第二电路可以被配置为响应于第一信号而产生多个第二信号。第三电路可以被配置为响应于第二信号而产生多个使能信号。第四电路可以被配置为响应于（i）使能信号和（ii）请求信号而一起产生输出信号。第一电路，第二电路，第三电路和第四电路的组合通常建立可编程优先编码器。可以独立于使能信号产生第二信号。

8. 发明申请

US20100293421A1 LOW DEPTH PROGRAMMABLE PRIORITY ENCODERS 有权
标题翻译：低密度可编程优先编码器
公开(公告)号：US20100293421A1
公开(公告)日：2010-11-18
申请号：US12465810
申请日：2009-05-14
申请人： Mikhail Grinchuk , Anatoli Bolotov , Sergei B. Gashkov , Lav D. Ivanovic
发明人： Mikhail Grinchuk , Anatoli Bolotov , Sergei B. Gashkov , Lav D. Ivanovic
IPC分类号： G01R31/28
CPC分类号： G06F7/74
摘要： An apparatus having a plurality of first circuits, second circuits, third circuits and fourth circuits is disclosed. The first circuits may be configured to generate a plurality of first signals in response to (i) a priority signal and (ii) a request signal. The second circuits may be configured to generate a plurality of second signals in response to the first signals. The third circuits may be configured to generate a plurality of enable signals in response to the second signals. The fourth circuits may be configured to generate collectively an output signal in response to (i) the enable signals and (ii) the request signal. A combination of the first circuits, the second circuits, the third circuits and the fourth circuits generally establishes a programmable priority encoder. The second signals may be generated independent of the enable signals.
摘要翻译：公开了具有多个第一电路，第二电路，第三电路和第四电路的装置。第一电路可以被配置为响应于（i）优先级信号和（ii）请求信号而产生多个第一信号。第二电路可以被配置为响应于第一信号而产生多个第二信号。第三电路可以被配置为响应于第二信号而产生多个使能信号。第四电路可以被配置为响应于（i）使能信号和（ii）请求信号而一起产生输出信号。第一电路，第二电路，第三电路和第四电路的组合通常建立可编程优先编码器。可以独立于使能信号产生第二信号。

9. 发明申请

US20050005255A1 Process for designing comparators and adders of small depth 失效
标题翻译：设计较小深度的比较器和加法器的过程
公开(公告)号：US20050005255A1
公开(公告)日：2005-01-06
申请号：US10602570
申请日：2003-06-24
申请人： Mikhail Grinchuk , Anatoli Bolotov
发明人： Mikhail Grinchuk , Anatoli Bolotov
IPC分类号： G06F7/02 , G06F7/506 , G06F17/50
CPC分类号： G06F17/5045 , G06F7/02 , G06F7/506
摘要： Logic circuits for logical operations, based on a function fN=x1 OR (x2 AND (x3 OR (x4 AND . . . xN . . . ))) or f′N=x1 AND (x2 OR (x3 AND (x4 OR . . . xN . . . ))), are designed by defining a top portion of the logic circuit based on a pre-selected pattern of 2-input $ and @ gates. The top portion has N inputs and approximately N/3 outputs. A smaller logic circuit is defined having approximately N/3 inputs coupled to the outputs of the top portion. In one embodiment, the circuit is designed for a circuit having N′ inputs, where N′ is 3n or 2*3n, and the N′-N most significant inputs are set to fixed values. The extra gates are removed resulting in a minimum depth circuit. In another embodiment, the depth is further reduced in some cases by designing a circuit for N-1 inputs and transforming the circuit to an N-input circuit. The $ and @ gates are converted to AND and/or OR gates, depending on the function.
摘要翻译：用于逻辑运算的逻辑电路基于函数fN = x1 OR（x2 AND（x3 OR（x4 AND ... xN ...））或f'N = x1 AND（x2 OR（x3 AND（x4 OR。通过基于2输入$和@门的预先选择的模式来定义逻辑电路的顶部来设计。顶部有N个输入和大约N / 3个输出。定义了较小的逻辑电路，其具有耦合到顶部部分的输出的大约N / 3个输入。在一个实施例中，电路被设计用于具有N'个输入的电路，其中N'是3n或2 * 3n，并且N'-N个最高有效输入被设置为固定值。额外的门被去除，导致最小的深度电路。在另一个实施例中，通过设计用于N-1输入的电路并将电路变换成N输入电路，在一些情况下深度进一步降低。根据功能，$和@门将转换为AND和/或OR门。

10. 发明申请

US20100086127A1 EFFICIENT IMPLEMENTATION OF ARITHMETICAL SECURE HASH TECHNIQUES 有权
标题翻译：有效实施算术安全技术
公开(公告)号：US20100086127A1
公开(公告)日：2010-04-08
申请号：US12246812
申请日：2008-10-07
申请人： Mikhail Grinchuk , Anatoli Bolotov , Lav D. Ivanovic , Andrej A. Zolotykh , Alexei V. Galatenko
发明人： Mikhail Grinchuk , Anatoli Bolotov , Lav D. Ivanovic , Andrej A. Zolotykh , Alexei V. Galatenko
IPC分类号： H04L9/06
CPC分类号： H04L9/0643 , H04L2209/125
摘要： An apparatus including an initialization circuit and a hash computation circuit. The initialization circuit may be configured to present a number of initialization values. The hash computation circuit may be configured to generate hash values for the message in response to the padded message blocks and the initialization values. The hash computation circuit generally performs a diagonal cut technique that simultaneously uses values from a plurality of different cycle rounds in a single cycle round analog.
摘要翻译：一种包括初始化电路和散列计算电路的装置。初始化电路可以被配置为呈现多个初始化值。哈希计算电路可以被配置为响应于填充的消息块和初始化值来生成消息的散列值。哈希计算电路通常执行对角切割技术，其同时使用来自单周期循环模拟中的多个不同循环回合的值。

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