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1. 发明申请

US20190042795A1 COMPRESSED INTEGRITY CHECK COUNTERS IN MEMORY 审中-公开
公开(公告)号：US20190042795A1
公开(公告)日：2019-02-07
申请号：US16022402
申请日：2018-06-28
申请人： Anatoli Bolotov , Mikhail Grinchuk
发明人： Anatoli Bolotov , Mikhail Grinchuk
IPC分类号： G06F21/64 , G06F11/10 , G11C29/52 , G06F12/0815 , H04L9/08
摘要： System and techniques for compressed integrity check counters in memory are described herein. A set of counters may be maintained for data areas in memory. A respective counter in the set of counters is used to provide a variance to encryption operations on a corresponding data area. The respective counter is each time data is modified in the corresponding data area. The respective counter implemented by a generalized multi-dimensional counter (GMDC). In response to a trigger, a counter reset is performed on the set of counters. The counter reset may include refreshing the corresponding data area using a new key and resetting the respective counter to a default value in response to the refresh.

2. 发明授权

US08654969B2 Cipher independent interface for cryptographic hardware service 有权
标题翻译：用于加密硬件服务的密码独立接口
公开(公告)号：US08654969B2
公开(公告)日：2014-02-18
申请号：US12673022
申请日：2009-04-10
申请人： Anatoli Bolotov , Mikhail Grinchuk , Lav Ivanovic , Christine E. Severns-Williams
发明人： Anatoli Bolotov , Mikhail Grinchuk , Lav Ivanovic , Christine E. Severns-Williams
IPC分类号： H04K1/00 , G06F11/30
CPC分类号： G06F21/602 , G09C1/00 , H04L9/0637 , H04L2209/125 , H04L2209/20
摘要： Disclosed is a cipher independent cryptographic hardware service. Cipher independent transactions are received into input slots (202). The input slots contain FIFOs to hold the transactions. The transactions are converted from cipher independent form to cipher dependent form (206) and timing as they are removed from the FIFOs. After cryptographic processing by cipher specific hardware, the results are sent to output FIFOs (212). Multiple FIFOs and cryptographic hardware may be used so that multiple cryptographic functions may be performed in parallel and simultaneously.
摘要翻译：公开了一种密码独立的密码硬件服务。密码独立事务被接收到输入时隙（202）中。输入插槽包含用于保存事务的FIFO。这些事务从密码独立形式转换为密码依赖格式（206），并将它们从FIFO中删除。在通过密码特定硬件的密码处理之后，将结果发送到输出FIFO（212）。可以使用多个FIFO和加密硬件，使得可以并行并且同时执行多个加密功能。

3. 发明授权

US08650146B2 Impulse regular expression matching 失效
标题翻译：冲动正则表达式匹配
公开(公告)号：US08650146B2
公开(公告)日：2014-02-11
申请号：US12822349
申请日：2010-06-24
申请人： Alexander Podkolzin , Lav Ivanovic , Anatoli Bolotov , Mikhail Grinchuk , Sergey Afonin
发明人： Alexander Podkolzin , Lav Ivanovic , Anatoli Bolotov , Mikhail Grinchuk , Sergey Afonin
IPC分类号： G06N5/02
CPC分类号： G06N5/022 , G06F7/02 , G06F17/30985 , G06F2207/025 , G06N5/047
摘要： Disclosed is a method and apparatus for matching regular expressions. A buffer of symbols giving a number of the last occurrence positions of each symbol is maintained. When two constants match on either side of a regular expression operator, the buffer of symbols is queried to determine if a member of the complement of the regular expression operator occurred between the two constants. If so, then the operator was not satisfied. If not, then the operator was satisfied.
摘要翻译：公开了一种用于匹配正则表达式的方法和装置。维持每个符号的最后出现位置数的符号缓冲器。当两个常数在正则表达式运算符的任一侧匹配时，查询符号缓冲区以确定正则表达式运算符的补码的成员是否在两个常量之间发生。如果是这样，那么操作员不满意。如果没有，那么操作员就满意了。

4. 发明授权

US08156391B2 Data controlling in the MBIST chain architecture 失效
标题翻译： MBIST链架构中的数据控制
公开(公告)号：US08156391B2
公开(公告)日：2012-04-10
申请号：US12167305
申请日：2008-07-03
申请人： Alexandre Andreev , Anatoli Bolotov , Mikhail Grinchuk
发明人： Alexandre Andreev , Anatoli Bolotov , Mikhail Grinchuk
IPC分类号： G11C29/14 , G11C29/50
CPC分类号： G11C29/32 , G11C8/16 , G11C2029/3202
摘要： A memory collar including a first circuit and a second circuit. The first circuit may be configured to generate one or more data sequences in response to one or more test commands. The one or more data sequences may be presented to a memory during a test mode. The second circuit may be configured to pre-process one or more outputs generated by the memory in response to the one or more data sequences.
摘要翻译：一种包括第一电路和第二电路的存储器环。第一电路可以被配置为响应于一个或多个测试命令而生成一个或多个数据序列。在测试模式期间，可以将一个或多个数据序列呈现给存储器。第二电路可以被配置为响应于一个或多个数据序列预处理由存储器产生的一个或多个输出。

5. 发明申请

US20090300441A1 ADDRESS CONTROLLING IN THE MBIST CHAIN ARCHITECTURE 有权
标题翻译：地址控制在MBIST链建筑
公开(公告)号：US20090300441A1
公开(公告)日：2009-12-03
申请号：US12183562
申请日：2008-07-31
申请人： Alexandre Andreev , Anatoli Bolotov , Mikhail Grinchuk
发明人： Alexandre Andreev , Anatoli Bolotov , Mikhail Grinchuk
IPC分类号： G11C29/12 , G06F11/27
CPC分类号： G11C29/32 , G11C8/16 , G11C2029/3202
摘要： A memory collar includes a first circuit, a second circuit and a third circuit. The first circuit may be configured to generate a first control signal, a second control signal and a third control signal in response to one or more test commands. The second circuit may be configured to generate a fourth control signal in response to said third control signal and the fourth control signal. The third circuit may be configured to generate one or more address sequences. The one or more address sequences are presented to a memory during a test mode.
摘要翻译：存储器环包括第一电路，第二电路和第三电路。第一电路可以被配置为响应于一个或多个测试命令产生第一控制信号，第二控制信号和第三控制信号。第二电路可以被配置为响应于所述第三控制信号和第四控制信号而产生第四控制信号。第三电路可以被配置为生成一个或多个地址序列。在测试模式期间将一个或多个地址序列呈现给存储器。

6. 发明申请

US20080046764A1 Data Shredding RAID Mode 有权
标题翻译：数据粉碎RAID模式
公开(公告)号：US20080046764A1
公开(公告)日：2008-02-21
申请号：US11620794
申请日：2007-01-08
申请人： Mikhail Grinchuk , Anatoli Bolotov , Ranko Scepanovic , Robert Waldron
发明人： Mikhail Grinchuk , Anatoli Bolotov , Ranko Scepanovic , Robert Waldron
IPC分类号： G06F12/14
CPC分类号： G06F21/6218
摘要： A method of storing sensitive data by generating randomization values, transforming the sensitive data and the randomization values into a result, and storing separate portions of the result on at least two storage devices, such that the sensitive data cannot be disclosed if any one of the storage devices is compromised.
摘要翻译：一种通过产生随机化值来存储敏感数据的方法，将敏感数据和随机化值变换为结果，并将结果的分离部分存储在至少两个存储设备上，使得如果敏感数据中的任何一个存储设备受到损害。

7. 发明申请

US20070143648A1 Memory timing model with back-annotating 失效
标题翻译：具有反向注释的内存计时模型
公开(公告)号：US20070143648A1
公开(公告)日：2007-06-21
申请号：US11311388
申请日：2005-12-19
申请人： Alexander Andreev , Anatoli Bolotov , Ranko Scepanovic
发明人： Alexander Andreev , Anatoli Bolotov , Ranko Scepanovic
IPC分类号： G11C29/00
CPC分类号： G11C5/04
摘要： A memory timing model is provided, which includes an address input, a multiple-bit data input, a multiple-bit data output, a capacity C and a width N. N one-bit wide memory modules are instantiated in parallel with one another between respective bits of the data input and the data output. Each memory module has a capacity of C bits addressed by the address input.
摘要翻译：提供了存储器定时模型，其包括地址输入，多位数据输入，多位数据输出，容量C和宽度N.N个1位宽存储器模块彼此并行地实例化数据输入的各个位和数据输出。每个存储器模块具有通过地址输入寻址的C位的容量。

8. 发明申请

US20060156088A1 Method and BIST architecture for fast memory testing in platform-based integrated circuit 有权
标题翻译：方法和BIST架构，用于基于平台的集成电路中的快速内存测试
公开(公告)号：US20060156088A1
公开(公告)日：2006-07-13
申请号：US10999493
申请日：2004-11-30
申请人： Alexander Andreev , Anatoli Bolotov , Raoko Scepanovic
发明人： Alexander Andreev , Anatoli Bolotov , Raoko Scepanovic
IPC分类号： G11C29/00
CPC分类号： G11C29/16 , G11C29/26 , G11C2029/2602
摘要： The present invention provides a method and BIST architecture for fast memory testing in a platform-based integrated circuit. The method may include steps as follows. An Mem-BIST controller transmitter is started to generate input signals for a memory in a platform using a deterministic and unconditional test algorithm. The input signals are delayed by a first group of pipelines by n clock cycles. The delayed input signals are received by the memory and an output signal is generated by the memory. The output signal is delayed by a second pipeline by m clock cycles. An Mem-BIST controller receiver is started to receive the delayed output signal for comparison.
摘要翻译：本发明提供了一种用于基于平台的集成电路中的快速存储器测试的方法和BIST架构。该方法可以包括以下步骤。启动Mem-BIST控制器发送器，使用确定性和无条件测试算法为平台中的存储器生成输入信号。输入信号被第一组管道延迟了n个时钟周期。延迟的输入信号由存储器接收，并且由存储器产生输出信号。输出信号被第二个流水线延迟了m个时钟周期。启动Mem-BIST控制器接收器以接收延迟的输出信号进行比较。

9. 发明申请

US20060129874A1 Master controller architecture 失效
标题翻译：主控制器架构
公开(公告)号：US20060129874A1
公开(公告)日：2006-06-15
申请号：US10999720
申请日：2004-11-30
申请人： Alexandre Andreev , Sergey Gribok , Anatoli Bolotov
发明人： Alexandre Andreev , Sergey Gribok , Anatoli Bolotov
IPC分类号： G06F11/00
CPC分类号： G11C29/16 , G11C29/44 , G11C29/4401 , G11C29/72
摘要： A master controller for an RRAM subsystem. An interface communicates with at least one RRAM controller. A main control unit selects and implements test and repair operations on the RRAM subsystem through the RRAM controller. A timer determines a maximum number of test and repair operations that can be implemented within a given time. Thus, a master controller is included in the RRAM subsystem. The master controller has a relatively simple interface, and performs test and repair operations on the RRAM subsystem. The advantages of using the master controller include an elimination of additional test ports, simplification of the process of preparing the test vectors for RRAM testing, and the master controller is able to accumulate test results and initiate repairs based on those results. In this manner, the RRAM subsystem has a self-repair functionality.
摘要翻译：用于RRAM子系统的主控制器。接口与至少一个RRAM控制器通信。主控单元通过RRAM控制器对RRAM子系统进行测试和修复操作。定时器确定在给定时间内可以实现的最大测试和修复操作数。因此，主控制器包含在RRAM子系统中。主控制器具有相对简单的接口，并对RRAM子系统执行测试和修复操作。使用主控制器的优点包括消除额外的测试端口，简化了用于RRAM测试的测试向量的准备过程，并且主控制器能够根据这些结果积累测试结果并启动修复。以这种方式，RRAM子系统具有自修复功能。

10. 发明申请

US20110029980A1 LOW DEPTH PROGRAMMABLE PRIORITY ENCODERS 有权
标题翻译：低密度可编程优先编码器
公开(公告)号：US20110029980A1
公开(公告)日：2011-02-03
申请号：US12902376
申请日：2010-10-12
申请人： Mikhail Grinchuk , Anatoli Bolotov , Sergei B. Gashkov , Lav D. Ivanovic
发明人： Mikhail Grinchuk , Anatoli Bolotov , Sergei B. Gashkov , Lav D. Ivanovic
IPC分类号： G06F9/46
CPC分类号： G06F7/74
摘要： An apparatus having a plurality of first circuits, second circuits, third circuits and fourth circuits is disclosed. The first circuits may be configured to generate a plurality of first signals in response to (i) a priority signal and (ii) a request signal. The second circuits may be configured to generate a plurality of second signals in response to the first signals. The third circuits may be configured to generate a plurality of enable signals in response to the second signals. The fourth circuits may be configured to generate collectively an output signal in response to (i) the enable signals and (ii) the request signal. A combination of the first circuits, the second circuits, the third circuits and the fourth circuits generally establishes a programmable priority encoder. The second signals may be generated independent of the enable signals.
摘要翻译：公开了具有多个第一电路，第二电路，第三电路和第四电路的装置。第一电路可以被配置为响应于（i）优先级信号和（ii）请求信号而产生多个第一信号。第二电路可以被配置为响应于第一信号而产生多个第二信号。第三电路可以被配置为响应于第二信号而产生多个使能信号。第四电路可以被配置为响应于（i）使能信号和（ii）请求信号而一起产生输出信号。第一电路，第二电路，第三电路和第四电路的组合通常建立可编程优先编码器。可以独立于使能信号产生第二信号。

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