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1. 发明申请

US20110029980A1 LOW DEPTH PROGRAMMABLE PRIORITY ENCODERS 有权
标题翻译：低密度可编程优先编码器
公开(公告)号：US20110029980A1
公开(公告)日：2011-02-03
申请号：US12902376
申请日：2010-10-12
申请人： Mikhail Grinchuk , Anatoli Bolotov , Sergei B. Gashkov , Lav D. Ivanovic
发明人： Mikhail Grinchuk , Anatoli Bolotov , Sergei B. Gashkov , Lav D. Ivanovic
IPC分类号： G06F9/46
CPC分类号： G06F7/74
摘要： An apparatus having a plurality of first circuits, second circuits, third circuits and fourth circuits is disclosed. The first circuits may be configured to generate a plurality of first signals in response to (i) a priority signal and (ii) a request signal. The second circuits may be configured to generate a plurality of second signals in response to the first signals. The third circuits may be configured to generate a plurality of enable signals in response to the second signals. The fourth circuits may be configured to generate collectively an output signal in response to (i) the enable signals and (ii) the request signal. A combination of the first circuits, the second circuits, the third circuits and the fourth circuits generally establishes a programmable priority encoder. The second signals may be generated independent of the enable signals.
摘要翻译：公开了具有多个第一电路，第二电路，第三电路和第四电路的装置。第一电路可以被配置为响应于（i）优先级信号和（ii）请求信号而产生多个第一信号。第二电路可以被配置为响应于第一信号而产生多个第二信号。第三电路可以被配置为响应于第二信号而产生多个使能信号。第四电路可以被配置为响应于（i）使能信号和（ii）请求信号而一起产生输出信号。第一电路，第二电路，第三电路和第四电路的组合通常建立可编程优先编码器。可以独立于使能信号产生第二信号。

2. 发明申请

US20100293421A1 LOW DEPTH PROGRAMMABLE PRIORITY ENCODERS 有权
标题翻译：低密度可编程优先编码器
公开(公告)号：US20100293421A1
公开(公告)日：2010-11-18
申请号：US12465810
申请日：2009-05-14
申请人： Mikhail Grinchuk , Anatoli Bolotov , Sergei B. Gashkov , Lav D. Ivanovic
发明人： Mikhail Grinchuk , Anatoli Bolotov , Sergei B. Gashkov , Lav D. Ivanovic
IPC分类号： G01R31/28
CPC分类号： G06F7/74
摘要： An apparatus having a plurality of first circuits, second circuits, third circuits and fourth circuits is disclosed. The first circuits may be configured to generate a plurality of first signals in response to (i) a priority signal and (ii) a request signal. The second circuits may be configured to generate a plurality of second signals in response to the first signals. The third circuits may be configured to generate a plurality of enable signals in response to the second signals. The fourth circuits may be configured to generate collectively an output signal in response to (i) the enable signals and (ii) the request signal. A combination of the first circuits, the second circuits, the third circuits and the fourth circuits generally establishes a programmable priority encoder. The second signals may be generated independent of the enable signals.
摘要翻译：公开了具有多个第一电路，第二电路，第三电路和第四电路的装置。第一电路可以被配置为响应于（i）优先级信号和（ii）请求信号而产生多个第一信号。第二电路可以被配置为响应于第一信号而产生多个第二信号。第三电路可以被配置为响应于第二信号而产生多个使能信号。第四电路可以被配置为响应于（i）使能信号和（ii）请求信号而一起产生输出信号。第一电路，第二电路，第三电路和第四电路的组合通常建立可编程优先编码器。可以独立于使能信号产生第二信号。

3. 发明申请

US20100070548A1 UNIVERSAL GALOIS FIELD MULTIPLIER 有权
标题翻译：通用GALOIS场地乘法器
公开(公告)号：US20100070548A1
公开(公告)日：2010-03-18
申请号：US12211268
申请日：2008-09-16
申请人： Sergei B. Gashkov , Alexandre Andreev
发明人： Sergei B. Gashkov , Alexandre Andreev
IPC分类号： G06F17/10
CPC分类号： G06F7/724
摘要： An apparatus including a multiplier circuit and a multiplexing circuit. The multiplier circuit may be configured to multiply a first multiplicand and a second multiplicand based on a programmable base value and generate a plurality of intermediate values, each intermediate value representing a result of the multiplication reduced by a respective irreducible polynomial. The multiplexing circuit may be configured to generate an output in response to the plurality of intermediate values received from the multiplier circuit and the programmable base value.
摘要翻译：一种包括乘法器电路和复用电路的装置。乘法器电路可以被配置为基于可编程基值乘以第一被乘数和第二被乘数，并且生成多个中间值，每个中间值表示乘法的结果减去相应的不可约多项式。复用电路可以被配置为响应于从乘法器电路接收的多个中间值和可编程基值产生输出。

4. 发明授权

US08312072B2 Universal Galois field multiplier 有权
标题翻译：通用伽罗瓦域乘法器
公开(公告)号：US08312072B2
公开(公告)日：2012-11-13
申请号：US12211268
申请日：2008-09-16
申请人： Sergei B. Gashkov , Alexandre Andreev
发明人： Sergei B. Gashkov , Alexandre Andreev
IPC分类号： G06F7/72
CPC分类号： G06F7/724
摘要： An apparatus including a multiplier circuit and a multiplexing circuit. The multiplier circuit may be configured to multiply a first multiplicand and a second multiplicand based on a programmable base value and generate a plurality of intermediate values, each intermediate value representing a result of the multiplication reduced by a respective irreducible polynomial. The multiplexing circuit may be configured to generate an output in response to the plurality of intermediate values received from the multiplier circuit and the programmable base value.
摘要翻译：一种包括乘法器电路和复用电路的装置。乘法器电路可以被配置为基于可编程基值乘以第一被乘数和第二被乘数，并且生成多个中间值，每个中间值表示乘法的结果减去相应的不可约多项式。复用电路可以被配置为响应于从乘法器电路接收的多个中间值和可编程基值产生输出。

5. 发明授权

US08063659B2 Low depth programmable priority encoders 有权
标题翻译：低深度可编程优先编码器
公开(公告)号：US08063659B2
公开(公告)日：2011-11-22
申请号：US12902376
申请日：2010-10-12
申请人： Mikhail Grinchuk , Anatoli Bolotov , Sergei B. Gashkov , Lav D. Ivanovic
发明人： Mikhail Grinchuk , Anatoli Bolotov , Sergei B. Gashkov , Lav D. Ivanovic
IPC分类号： G06F7/38 , H03K19/173
CPC分类号： G06F7/74
摘要： An apparatus having a plurality of first circuits, second circuits, third circuits and fourth circuits is disclosed. The first circuits may be configured to generate a plurality of first signals in response to (i) a priority signal and (ii) a request signal. The second circuits may be configured to generate a plurality of second signals in response to the first signals. The third circuits may be configured to generate a plurality of enable signals in response to the second signals. The fourth circuits may be configured to generate collectively an output signal in response to (i) the enable signals and (ii) the request signal. A combination of the first circuits, the second circuits, the third circuits and the fourth circuits generally establishes a programmable priority encoder. The second signals may be generated independent of the enable signals.
摘要翻译：公开了具有多个第一电路，第二电路，第三电路和第四电路的装置。第一电路可以被配置为响应于（i）优先级信号和（ii）请求信号而产生多个第一信号。第二电路可以被配置为响应于第一信号而产生多个第二信号。第三电路可以被配置为响应于第二信号而产生多个使能信号。第四电路可以被配置为响应于（i）使能信号和（ii）请求信号而一起产生输出信号。第一电路，第二电路，第三电路和第四电路的组合通常建立可编程优先编码器。可以独立于使能信号产生第二信号。

6. 发明授权

US07839164B1 Low depth programmable priority encoders 有权
标题翻译：低深度可编程优先编码器
公开(公告)号：US07839164B1
公开(公告)日：2010-11-23
申请号：US12465810
申请日：2009-05-14
申请人： Mikhail Grinchuk , Anatoli Bolotov , Sergei B. Gashkov , Lav D. Ivanovic
发明人： Mikhail Grinchuk , Anatoli Bolotov , Sergei B. Gashkov , Lav D. Ivanovic
IPC分类号： G06F7/38 , H03K19/173
CPC分类号： G06F7/74
摘要： An apparatus having a plurality of first circuits, second circuits, third circuits and fourth circuits is disclosed. The first circuits may be configured to generate a plurality of first signals in response to (i) a priority signal and (ii) a request signal. The second circuits may be configured to generate a plurality of second signals in response to the first signals. The third circuits may be configured to generate a plurality of enable signals in response to the second signals. The fourth circuits may be configured to generate collectively an output signal in response to (i) the enable signals and (ii) the request signal. A combination of the first circuits, the second circuits, the third circuits and the fourth circuits generally establishes a programmable priority encoder. The second signals may be generated independent of the enable signals.
摘要翻译：公开了具有多个第一电路，第二电路，第三电路和第四电路的装置。第一电路可以被配置为响应于（i）优先级信号和（ii）请求信号而产生多个第一信号。第二电路可以被配置为响应于第一信号而产生多个第二信号。第三电路可以被配置为响应于第二信号而产生多个使能信号。第四电路可以被配置为响应于（i）使能信号和（ii）请求信号而一起产生输出信号。第一电路，第二电路，第三电路和第四电路的组合通常建立可编程优先编码器。可以独立于使能信号产生第二信号。

7. 发明授权

US07167886B2 Method for constructing logic circuits of small depth and complexity for operation of inversion in finite fields of characteristic 2 有权
标题翻译：用于构造特征2有限域中反演操作的小深度和复杂度逻辑电路的方法
公开(公告)号：US07167886B2
公开(公告)日：2007-01-23
申请号：US10430446
申请日：2003-05-06
申请人： Sergei B. Gashkov , Alexander E. Andreev
发明人： Sergei B. Gashkov , Alexander E. Andreev
IPC分类号： G06F7/00
CPC分类号： G06F7/726 , G06F2207/7209
摘要： A method for constructing a logic circuit for inversion in finite field GF(2m) is described, where m=nk, and k, n are coprime numbers, using bases in subfields GF(2n) and GF(2k). The method may be applied to error correction codes, including BCH codes, Reed-Solomon codes (which are a subset of BCH codes), turbo codes, and the like.
摘要翻译：描述了在有限域GF（2）中构造用于反转的逻辑电路的方法，其中m = nk，并且k，n是互质数，使用子场GF（2 < n +）和GF（2k）。该方法可以应用于纠错码，包括BCH码，Reed-Solomon码（它们是BCH码的子集），turbo码等。

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