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1. 发明申请

US20060107247A1 Memory generation and placement 有权
标题翻译：内存生成和放置
公开(公告)号：US20060107247A1
公开(公告)日：2006-05-18
申请号：US10990589
申请日：2004-11-17
申请人： Alexandre Andreev , Ilya Neznanov , Andrey Nikitin , Ranko Scepanovic , Igor Vikhliantsev
发明人： Alexandre Andreev , Ilya Neznanov , Andrey Nikitin , Ranko Scepanovic , Igor Vikhliantsev
IPC分类号： G06F9/455 , G06F17/50
CPC分类号： G06F17/5072
摘要： A memory generation and placement flow system that receives a customer memory design and places the customer memory design within a customizable standardized integrated circuit design. The memory generation and placement flow system includes a memory librarian tool, a memory estimator tool, and a memory placer tool.
摘要翻译：存储器生成和放置流程系统，其接收客户存储器设计，并将客户存储器设计放置在可定制的标准化集成电路设计中。存储器生成和放置流程系统包括存储库管理器工具，存储器估计器工具和存储器存储器工具。

2. 发明申请

US20070136704A1 Method and apparatus for generating memory models and timing database 失效
标题翻译：用于生成内存模型和计时数据库的方法和装置
公开(公告)号：US20070136704A1
公开(公告)日：2007-06-14
申请号：US11298894
申请日：2005-12-09
申请人： Alexandre Andreev , Andrey Nikitin , Ranko Scepanovic , Igor Vikhliantsev
发明人： Alexandre Andreev , Andrey Nikitin , Ranko Scepanovic , Igor Vikhliantsev
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： A method and apparatus are provided for creating and using a memory timing database. A plurality of characterization memories are defined, which can be mapped to a memory resource. Each characterization memory has different memory parameters. A plurality of variants of tiling each characterization memory to the memory resource are also defined. Timing characteristics of each tiling variant of each characterization memory are stored in the memory timing database for the memory resource based on sets of input ramptimes and output loads.
摘要翻译：提供了一种用于创建和使用存储器定时数据库的方法和装置。定义了多个表征存储器，其可被映射到存储器资源。每个表征存储器具有不同的存储器参数。还定义了将每个表征存储器平铺到存储器资源的多种变型。每个表征存储器的每个平铺变体的时序特征基于输入夯实值和输出负载的集合存储在用于存储器资源的存储器定时数据库中。

3. 发明授权

US07155688B2 Memory generation and placement 有权
公开(公告)号：US07155688B2
公开(公告)日：2006-12-26
申请号：US10990589
申请日：2004-11-17
申请人： Alexandre Andreev , Ilya V. Neznanov , Andrey Nikitin , Ranko Scepanovic , Igor Vikhliantsev
发明人： Alexandre Andreev , Ilya V. Neznanov , Andrey Nikitin , Ranko Scepanovic , Igor Vikhliantsev
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： A memory generation and placement flow system that receives a customer memory design and places the customer memory design within a customizable standardized integrated circuit design. The memory generation and placement flow system includes a memory librarian tool, a memory estimator tool, and a memory placer tool.

4. 发明授权

US07739471B2 High performance tiling for RRAM memory 有权
标题翻译：高性能平铺的RRAM内存
公开(公告)号：US07739471B2
公开(公告)日：2010-06-15
申请号：US11256830
申请日：2005-10-24
申请人： Alexander Andreev , Igor Vikhliantsev , Ranko Scepanovic
发明人： Alexander Andreev , Igor Vikhliantsev , Ranko Scepanovic
IPC分类号： G06F12/02
CPC分类号： G11C8/12 , G11C2207/104
摘要： A method of configuring a random access memory matrix containing partially configured memories in the matrix. The method includes the steps of independently calculating a memory enable signal and a configuration signal for a partially configured memory in each memory tile of the memory matrix. Memory tiles not supported by a memory compiler are determined. A memory wrapper is provided for each tile not supported by the memory compiler. An address controller is inserted in the memory matrix for each tile in a group of tiles. Output signals from each memory location in a memory group having a common group index are combined into a single output signal. A first stripe of memory tiles containing non-configured memory having a first width is selected. A second strip of memory tiles containing configured memory having a second width is also selected.
摘要翻译：一种在矩阵中配置包含部分配置的存储器的随机存取存储器矩阵的方法。该方法包括以下步骤：对存储器矩阵的每个存储器块中的部分配置的存储器独立地计算存储器使能信号和配置信号。确定内存编译器不支持的内存片。为存储器编译器不支持的每个片提供内存包装器。在一组瓦片中的每个瓦片的存储矩阵中插入地址控制器。来自具有公共组索引的存储器组中的每个存储器位置的输出信号被组合成单个输出信号。选择包含具有第一宽度的非配置存储器的第一条存储器片。还选择包含具有第二宽度的配置存储器的第二条存储器片。

5. 发明授权

US08035537B2 Methods and apparatus for programmable decoding of a plurality of code types 有权
标题翻译：用于多种代码类型的可编程解码的方法和装置
公开(公告)号：US08035537B2
公开(公告)日：2011-10-11
申请号：US12138920
申请日：2008-06-13
申请人： Alexander Andreev , Sergey Gribok , Oleg Izyumin , Ranko Scepanovic , Igor Vikhliantsev , Vojislav Vukovic
发明人： Alexander Andreev , Sergey Gribok , Oleg Izyumin , Ranko Scepanovic , Igor Vikhliantsev , Vojislav Vukovic
IPC分类号： H03M7/00
CPC分类号： H03M13/296 , H03M13/2725 , H03M13/6508 , H03M13/6513 , H03M13/6519 , H03M13/6525 , H03M13/6544 , H03M13/6569
摘要： Methods and apparatus are provided for programmable decoding of a plurality of code types. A method is provided for decoding data encoded using one of a plurality of code types, where each of the code types correspond to a communication standard. The code type associated with the data is identified and the data is allocated to a plurality of programmable parallel decoders. The programmable parallel decoders can be reconfigured to decode data encoded using each of the plurality of code types. A method is also provided for interleaving data among M parallel decoders using a communications network. An interleaver table is employed, wherein each entry in the interleaver table identifies one of the M parallel decoders as a target decoder and a target address of a communications network for interleaved data. Data is interleaved by writing the data to the target address of the communications network. The communications network can comprise, for example, a cross-bar switch and/or one or more first-in-first-out buffers.
摘要翻译：提供了用于多种代码类型的可编程解码的方法和装置。提供了一种用于解码使用多种代码类型之一编码的数据的方法，其中每种代码类型对应于通信标准。识别与数据相关联的代码类型，并将数据分配给多个可编程并行解码器。可重新配置可编程并行解码器以对使用多种代码类型中的每一种编码的数据进行解码。还提供了一种用于使用通信网络在M个并行解码器之间交织数据的方法。使用交织器表，其中交织器表中的每个条目将M个并行解码器中的一个识别为目标解码器，并将交织数据的通信网络的目标地址标识。通过将数据写入到通信网络的目标地址来交织数据。通信网络可以包括例如交叉开关和/或一个或多个先入先出缓冲器。

6. 发明申请

US20090309770A1 METHODS AND APPARATUS FOR PROGRAMMABLE DECODING OF A PLURALITY OF CODE TYPES 有权
标题翻译：用于可编程解码大量代码类型的方法和装置
公开(公告)号：US20090309770A1
公开(公告)日：2009-12-17
申请号：US12138920
申请日：2008-06-13
申请人： Alexander Andreev , Sergey Gribok , Oleg Izyumin , Ranko Scepanovic , Igor Vikhliantsev , Vojislav Vukovic
发明人： Alexander Andreev , Sergey Gribok , Oleg Izyumin , Ranko Scepanovic , Igor Vikhliantsev , Vojislav Vukovic
IPC分类号： H03M7/00
CPC分类号： H03M13/296 , H03M13/2725 , H03M13/6508 , H03M13/6513 , H03M13/6519 , H03M13/6525 , H03M13/6544 , H03M13/6569
摘要： Methods and apparatus are provided for programmable decoding of a plurality of code types. A method is provided for decoding data encoded using one of a plurality of code types, where each of the code types correspond to a communication standard. The code type associated with the data is identified and the data is allocated to a plurality of programmable parallel decoders. The programmable parallel decoders can be reconfigured to decode data encoded using each of the plurality of code types. A method is also provided for interleaving data among M parallel decoders using a communications network. An interleaver table is employed, wherein each entry in the interleaver table identifies one of the M parallel decoders as a target decoder and a target address of a communications network for interleaved data. Data is interleaved by writing the data to the target address of the communications network. The communications network can comprise, for example, a cross-bar switch and/or one or more first-in-first-out buffers.
摘要翻译：提供了用于多种代码类型的可编程解码的方法和装置。提供了一种用于解码使用多种代码类型之一编码的数据的方法，其中每种代码类型对应于通信标准。识别与数据相关联的代码类型，并将数据分配给多个可编程并行解码器。可重新配置可编程并行解码器以对使用多种代码类型中的每一种编码的数据进行解码。还提供了一种用于使用通信网络在M个并行解码器之间交织数据的方法。使用交织器表，其中交织器表中的每个条目将M个并行解码器中的一个识别为目标解码器，并将交织数据的通信网络的目标地址标识。通过将数据写入到通信网络的目标地址来交织数据。通信网络可以包括例如交叉开关和/或一个或多个先入先出缓冲器。

7. 发明申请

US20070091105A1 High performance tiling for RRAM memory 有权
标题翻译：高性能平铺的RRAM内存
公开(公告)号：US20070091105A1
公开(公告)日：2007-04-26
申请号：US11256830
申请日：2005-10-24
申请人： Alexander Andreev , Igor Vikhliantsev , Ranko Scepanovic
发明人： Alexander Andreev , Igor Vikhliantsev , Ranko Scepanovic
IPC分类号： G06F12/02
CPC分类号： G11C8/12 , G11C2207/104
摘要： A method of configuring a random access memory matrix containing partially configured memories in the matrix. The method includes the steps of independently calculating a memory enable signal and a configuration signal for a partially configured memory in each memory tile of the memory matrix. Memory tiles not supported by a memory compiler are determined. A memory wrapper is provided for each tile not supported by the memory compiler. An address controller is inserted in the memory matrix for each tile in a group of tiles. Output signals from each memory location in a memory group having a common group index are combined into a single output signal. A first stripe of memory tiles containing non-configured memory having a first width is selected. A second strip of memory tiles containing configured memory having a second width is also selected.
摘要翻译：一种在矩阵中配置包含部分配置的存储器的随机存取存储器矩阵的方法。该方法包括以下步骤：对存储器矩阵的每个存储器块中的部分配置的存储器独立地计算存储器使能信号和配置信号。确定内存编译器不支持的内存片。为存储器编译器不支持的每个片提供内存包装器。在一组瓦片中的每个瓦片的存储矩阵中插入地址控制器。来自具有公共组索引的存储器组中的每个存储器位置的输出信号被组合成单个输出信号。选择包含具有第一宽度的非配置存储器的第一条存储器片。还选择包含具有第二宽度的配置存储器的第二条存储器片。

8. 发明申请

US20050055527A1 Controller architecture for memory mapping 失效
标题翻译：用于内存映射的控制器架构
公开(公告)号：US20050055527A1
公开(公告)日：2005-03-10
申请号：US10655191
申请日：2003-09-04
申请人： Alexander Andreev , Igor Vikhliantsev , Ranko Scepanovic
发明人： Alexander Andreev , Igor Vikhliantsev , Ranko Scepanovic
IPC分类号： G06F12/04 , G06F12/08
CPC分类号： G06F12/04
摘要： The present invention is directed to a method and apparatus for mapping a customer memory onto a plurality of physical memories. The apparatus may include: (a) a plurality of physical memories onto which a customer memory may be mapped, each of physical memories having a data width of m blocks, the customer memory having a data width of k blocks, and k and m being integers; (b) an address controller, communicatively coupled to a plurality of physical memories, for receiving first address information of the customer memory, for outputting second address information to a plurality of physical memories, and for outputting index information; (c) a data input controller, communicatively coupled to the address controller and a plurality of physical memories, for receiving data of the customer memory and the index information, and for outputting data with a data width of m blocks to a plurality of physical memories; and (d) a data output controller, communicatively coupled to a plurality of physical memories and to the address controller though a delay unit, for receiving the index information, for receiving output, with a width of said m blocks, of a plurality of physical memories, and for outputting the customer memory with a width of said k blocks.
摘要翻译：本发明涉及一种用于将顾客存储器映射到多个物理存储器上的方法和装置。该装置可以包括：（a）可以映射客户存储器的多个物理存储器，每个物理存储器具有m个块的数据宽度，该客户存储器的数据宽度为k个块，k和m为整数（b）地址控制器，通信地耦合到多个物理存储器，用于接收客户存储器的第一地址信息，用于将第二地址信息输出到多个物理存储器，并用于输出索引信息; （c）数据输入控制器，通信地耦合到地址控制器和多个物理存储器，用于接收客户存储器的数据和索引信息，并且用于将数据宽度为m个块的数据输出到多个物理存储器 ; 以及（d）数据输出控制器，通信地耦合到多个物理存储器，并通过延迟单元与地址控制器通信，用于接收索引信息，用于接收具有所述m个块的宽度的多个物理存储器，并输出具有所述k个块的宽度的客户存储器。

9. 发明申请

US20050091625A1 Process and apparatus for placement of cells in an IC during floorplan creation 有权
标题翻译：在建立平面布置图时，将单元格放置在IC中的过程和装置
公开(公告)号：US20050091625A1
公开(公告)日：2005-04-28
申请号：US10694208
申请日：2003-10-27
申请人： Alexander Andreev , Andrey Nikitin , Igor Vikhliantsev
发明人： Alexander Andreev , Andrey Nikitin , Igor Vikhliantsev
IPC分类号： G06F9/45 , G06F17/50
CPC分类号： G06F17/5072
摘要： Objects are placed in a rectangle and their coordinates of the objects and are adjusted to establish a substantially uniform density of objects in the rectangle. The evaluation of coordinates is performed by placing the wires between cells coordinates and adjusting the cell coordinates to connect the cells to the wires. The substantially uniform density is achieved by dividing the rectangle into first and second rectangles having equal free areas and into third and fourth rectangles having equal areas of objects. The coordinates of the objects are adjusted based on boundaries between the first and second rectangles and between the third and fourth rectangles.
摘要翻译：将对象放置在矩形中，并且对象的坐标进行调整，以在矩形中建立大致均匀的对象密度。坐标的评估是通过将电线放在单元之间进行坐标并调整单元坐标来连接单元与导线。通过将矩形分成具有相等空闲区域的第一和第二矩形以及具有相同面积的物体的第三和第四矩形来实现基本上均匀的密度。基于第一和第二矩形之间以及第三和第四矩形之间的边界来调整对象的坐标。

10. 发明申请

US20070230621A1 DIGITAL GAUSSIAN NOISE SIMULATOR 有权
公开(公告)号：US20070230621A1
公开(公告)日：2007-10-04
申请号：US11758975
申请日：2007-06-06
申请人： Andrey Nikitin , Alexander Andreev , Igor Vikhliantsev
发明人： Andrey Nikitin , Alexander Andreev , Igor Vikhliantsev
IPC分类号： H03K9/00
CPC分类号： G06F17/18
摘要： A Gaussian noise is simulated by discrete analogue ri,j. A first parameter α and pluralities of first and second integers i and j are selected. A plurality of points i,j are identified and a magnitude si,j is calculated for each point based on α, i and j. The discrete analogue ri,j is based on a respective si,j. Examples are given of α = 2 B - A 2 B and D>i≧0 and 2C>j≧0, where B≧0, 2B>A>0, C≧1 and D≧1, and magnitude s i , j = 1 - α i + α i · 1 - α 2 C · j ⁢ ⁢ or ⁢ ⁢ s D - 1 , j = 1 - α D - 1 + α D - 1 · 1 2 C · j . In some embodiments, a segment is defined based on α and i. The segment is divided into points based on respective values of j, and the magnitude is calculated for each point of the segment. The defining and dividing segments and calculating the magnitude is iteratively repeated for each value of i.

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