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1. 发明申请

US20180294921A1 ENCODER DEVICE, DECODER DEVICE AND TRANSMISSION APPARATUS 审中-公开
公开(公告)号：US20180294921A1
公开(公告)日：2018-10-11
申请号：US15570666
申请日：2015-09-07
申请人： Mitsubishi Electric Corporation
发明人： Yoshikuni MIYATA , Kenya SUGIHARA , Hideo YOSHIDA
IPC分类号： H04L1/00 , H03M13/27
CPC分类号： H04L1/0071 , H03M13/2703 , H03M13/2792 , H03M13/2796 , H03M13/6508 , H03M13/6561 , H03M13/6563 , H04J3/1652 , H04J2203/0089 , H04L1/0041
摘要： An error correction encoder (10) includes an interleaver circuit (31), encoding circuits (321, 322) and a deinterleaver circuit (33). The interleaver circuit (31) generates, in a standard speed mode, a single series of yet-to-be-coded bit sequences (IL1) on the basis of the bits in plural columns that are arranged at an interval of C columns in a single series of transmission frames, and generates, in a two-times speed mode, two series of yet-to-be-coded bit sequences (IL1, IL2) on the basis of the bits in plural columns that are arranged at an interval of C/2 columns in each of two series of transmission frames. The encoding circuits (321, 322) apply error-correction coding to either the single series of yet-to-be-coded bit sequences (IL1) or the two series of yet-to-be-coded bit sequences (IL1, IL2).

2. 发明授权

US10063259B2 Interleaving method and apparatus for adaptively determining interleaving depth 有权
公开(公告)号：US10063259B2
公开(公告)日：2018-08-28
申请号：US14944428
申请日：2015-11-18
申请人： Samsung Electronics Co., Ltd.
发明人： Jaewook Shim , Chang Soon Park
IPC分类号： H03M13/00 , H03M13/27
CPC分类号： H03M13/2707 , H03M13/2789 , H03M13/6356 , H03M13/6508
摘要： An interleaving method and apparatus for adaptively determining an interleaving depth of each of one or more interleaving blocks based on a maximum interleaving depth and a number of codewords of a packet, and interleaving the interleaving blocks based on the interleaving depth. The adaptively determining the interleaving depth includes: calculating a number of remaining codewords by performing a modulo operation on a basic interleaving depth and the number of the codewords; and determining the interleaving depth by adjusting the basic interleaving depth based on the number of the remaining codewords.

3. 发明申请

US20170041024A1 METHOD AND APPARATUS FOR REDUCING IDLE CYCLES DURING LDPC DECODING 审中-公开
标题翻译：用于在LDPC解码期间减少空闲周期的方法和装置
公开(公告)号：US20170041024A1
公开(公告)日：2017-02-09
申请号：US15284060
申请日：2016-10-03
申请人： Marvell International Ltd.
发明人： Yuan-Mao Chang , Engling Yeo
IPC分类号： H03M13/11 , H03M13/25 , H03M13/00
CPC分类号： H03M13/112 , H03M13/1102 , H03M13/1105 , H03M13/1111 , H03M13/255 , H03M13/3715 , H03M13/616 , H03M13/6337 , H03M13/6508 , H03M13/6561 , H03M13/6577
摘要： There is provided, in accordance with an embodiment, a method of decoding codewords in conjunction with a low-density parity-check (LDPC) code that defines variable nodes and check nodes, the method comprising receiving a codeword over a data channel; evaluating quality of the data channel; and iteratively updating values of the variable nodes to decode the codeword; wherein the values of the variable nodes are updated at different levels of numeric precision depending on the evaluated quality of the data channel.
摘要翻译：根据实施例，提供了一种解码码字的方法，该方法结合定义可变节点和校验节点的低密度奇偶校验（LDPC）码，该方法包括：在数据信道上接收码字; 评估数据通道的质量; 并迭代地更新可变节点的值以解码码字; 其中根据数据信道的评估质量，以不同的数值精度更新可变节点的值。

4. 发明授权

US09520900B2 Convolutional interleaver having a plurality of delay portions 有权
标题翻译：卷积交织器具有多个延迟部分
公开(公告)号：US09520900B2
公开(公告)日：2016-12-13
申请号：US14780223
申请日：2014-03-27
申请人： SONY CORPORATION
发明人： Matthew Paul Athol Taylor
IPC分类号： H03M13/03 , H03M13/27 , G06F11/10 , H04L1/00 , H03M13/00
CPC分类号： H03M13/2732 , G06F11/10 , H03M13/2782 , H03M13/2789 , H03M13/2792 , H03M13/6508 , H04L1/0041
摘要： A transmitter for transmitting a signal including an interleaved symbol stream includes a convolutional interleaver including a plurality of delay portions, each of which is arranged to delay symbols from an uninterleaved symbol stream from an input to an output by a different amount, the delay portions being arranged in a sequence. An input selector inputs the symbols from the uninterleaved symbol stream to the delay portions so that successive symbols are input in accordance with the sequence of the delay portions. An output selector reads the symbols from the delay portions by successively selecting the symbols from the outputs of the delay portions in accordance with the sequence of the delay portions to form an interleaved symbol stream.
摘要翻译：用于发送包括交错符号流的信号的发送器包括卷积交织器，该卷积交织器包括多个延迟部分，每个延迟部分被布置为将符号从未输入的符号流从输入延迟到输出不同的量，延迟部分按顺序排列。输入选择器将来自未交织的符号流的符号输入到延迟部分，使得根据延迟部分的顺序输入连续的符号。输出选择器通过根据延迟部分的顺序从延迟部分的输出中连续选择符号来从延迟部分读取符号，以形成交织符号流。

5. 发明授权

US09484958B2 Method and system for controlling an interleaver 有权
公开(公告)号：US09484958B2
公开(公告)日：2016-11-01
申请号：US14950127
申请日：2015-11-24
申请人： AT&T INTELLECTUAL PROPERTY I, LP
发明人： Thomas J. J. Starr
IPC分类号： H03M13/00 , H03M13/27 , H04L1/00 , H04L1/20 , G06F21/56 , H03M13/35
CPC分类号： H03M13/2792 , G06F21/56 , H03M13/2789 , H03M13/353 , H03M13/6508 , H04L1/0001 , H04L1/0003 , H04L1/0015 , H04L1/0021 , H04L1/0025 , H04L1/0026 , H04L1/0045 , H04L1/0071 , H04L1/0075 , H04L1/20
摘要： Systems and Methods for controlling an interleaver are disclosed. Generally, a first and second signal are received, wherein the first and second signals are selected from the group consisting of a signal to noise ration signal, a data rate signal, and a bit error rate signal. An interleaver control signal is then generated based on the first and second signals.

6. 发明授权

US09484956B2 Method for correcting messages containing bit stuffing 有权
公开(公告)号：US09484956B2
公开(公告)日：2016-11-01
申请号：US13977787
申请日：2012-01-03
申请人： Raoul Prevost , David Bonacci , Martial Coulon , Jean-Yves Tourneret , Julia Le Maitre , Jean-Pierre Millerioux
发明人： Raoul Prevost , David Bonacci , Martial Coulon , Jean-Yves Tourneret , Julia Le Maitre , Jean-Pierre Millerioux
IPC分类号： H03M13/03 , H03M13/25 , H03M13/39 , H03M13/41 , H03M13/00
CPC分类号： H03M13/256 , H03M13/3994 , H03M13/41 , H03M13/4146 , H03M13/6508
摘要： The invention relates to a method for correcting a message the generation of which involves transforming an initial message and inserting bit stuffing into the transformed message, which method comprises providing an observation sequence containing the message to be corrected. A number of path hypotheses are generated via a trellis diagram associated with the transformation. The nodes of the trellis diagram each represent a state of a finite-state machine capable of transforming the initial message and the branches represent the possible transitions between nodes. Among the branches of the trellis diagram, certain represent conditional transitions that may be made only when bit stuffing is present. During the generation of a path hypothesis, bit stuffing is detected and the branches taken are those associated with the detected bit stuffing. The most likely path hypothesis relative to the observation sequence is finally retained.

7. 发明申请

US20160241274A1 Multi Mode Viterbi Decoder 有权
标题翻译：多模维特比解码器
公开(公告)号：US20160241274A1
公开(公告)日：2016-08-18
申请号：US14624872
申请日：2015-02-18
申请人： eTopus Technology Inc.
发明人： Kai Keung Chan , Yu Kou , Tze Yin Cheung , Danfeng Xu
IPC分类号： H03M13/39 , H03M13/41
CPC分类号： H03M13/3961 , H03M13/4107 , H03M13/4161 , H03M13/6508
摘要： A multi-mode viterbi decoder supporting different decoding modes. The viterbi decoder comprises circuitry to output one or more data symbol values. The circuitry sets the one or more data symbol values to a first quantity of unit intervals in a first decoding mode (e.g. PAM-4). The circuitry sets the one or more data symbol values to a second quantity of unit intervals in a second decoding mode (e.g. NRZ). The second quantity of unit intervals is greater than the first quantity of unit intervals. A branch metric circuit is adapted to, in the first decoding mode, generate a set of viterbi branch metrics based on the data symbol values for the first quantity of unit intervals. The branch metric circuit is adapted to, in the second decoding mode, generate the set of viterbi branch metrics based on the data symbol values for the second quantity of unit intervals.
摘要翻译：支持不同解码模式的多模式维特比解码器。维特比解码器包括用于输出一个或多个数据符号值的电路。电路将第一解码模式（例如，PAM-4）中的一个或多个数据符号值设置为第一数量的单位间隔。电路在第二解码模式（例如NRZ）中将一个或多个数据符号值设置为第二数量的单位间隔。单位间隔的第二数量大于第一单位间隔数量。分支度量电路适于在第一解码模式中，基于第一数量单位间隔的数据符号值生成一组维特比分支度量。分支度量电路适于在第二解码模式中，基于第二数量单位间隔的数据符号值生成维特比分支量度集合。

8. 发明申请

US20160234813A1 METHOD AND APPARATUS FOR TRANSMITTING AND RECEIVING R-PDCCH 审中-公开
公开(公告)号：US20160234813A1
公开(公告)日：2016-08-11
申请号：US15099797
申请日：2016-04-15
申请人： LG Electronics Inc.
发明人： Hakseong Kim , Hanbyul Seo , Kijun Kim
IPC分类号： H04W72/04 , H04L5/00 , H04L1/00
CPC分类号： H04W72/042 , H03M13/271 , H03M13/3723 , H03M13/6508 , H03M13/6525 , H04J11/0073 , H04L1/0046 , H04L1/0071 , H04L1/0072 , H04L5/0007 , H04L5/0053 , H04W72/04 , H04W84/047 , H04W88/08
摘要： A method and apparatus for transmitting and receiving a Relay Physical Downlink Control Channel (R-PDCCH) being a control channel for a relay node (RN) in a wireless communication system are disclosed. To transmit an R-PDCCH to a RN, a BS includes a processor for interleaving a predetermined number of Control Channel Elements (CCEs), mapping the interleaved CCEs to at least one Virtual Resource Block (VRB) configured for R-PDCCH transmission, mapping the at least one VRB to at least one Physical Resource Block (PRB), and a transmitter for transmitting the R-PDCCH to the RN through the at least one PRB.

9. 发明申请

US20160094244A1 APPARATUS AND METHOD FOR RESOURCE ALLOCATION 审中-公开
标题翻译：设备和资源分配方法
公开(公告)号：US20160094244A1
公开(公告)日：2016-03-31
申请号：US14496183
申请日：2014-09-25
申请人： Ali Misfer ALKATHAMI
发明人： Ali Misfer ALKATHAMI
IPC分类号： H03M13/09 , H03M13/00
CPC分类号： H03M13/095 , G06F11/10 , G06F11/1068 , G06F12/0207 , H03M13/09 , H03M13/116 , H03M13/1165 , H03M13/1168 , H03M13/255 , H03M13/2721 , H03M13/356 , H03M13/616 , H03M13/6508 , H03M13/6516 , H04J13/10 , H04J13/16 , H04L1/005 , H04L1/0061 , H04L9/304
摘要： An apparatus and a method for allocating network resources in a fair manner. The method includes determining for a first matrix of a certain dimension and a corresponding set of predetermined numbers, a second allocation matrix, wherein the numbers allocated to cells of the second matrix are such that the sum of the numbers in any row, column, diagonal, or anti-diagonal equal the same number. Based on predetermined priorities, a row, column, diagonal, or an anti-diagonal of the second allocation matrix is selected to correspond to the
摘要翻译：一种以公平的方式分配网络资源的装置和方法。该方法包括确定特定尺寸的第一矩阵和相应的一组预定数量的第二分配矩阵，其中分配给第二矩阵的单元的数量使得任何行，列，对角线中的数字之和，或反对角线相等的数字。基于预定的优先级，选择第二分配矩阵的行，列，对角线或反对角线以对应于

10. 发明申请

US20160080000A1 METHOD AND SYSTEM FOR CONTROLLING AN INTERLEAVER 有权
标题翻译：用于控制交互的方法和系统
公开(公告)号：US20160080000A1
公开(公告)日：2016-03-17
申请号：US14950127
申请日：2015-11-24
申请人： AT&T INTELLECTUAL PROPERTY I, LP
发明人： Thomas J.J. Starr
IPC分类号： H03M13/27 , H03M13/35
CPC分类号： H03M13/2792 , G06F21/56 , H03M13/2789 , H03M13/353 , H03M13/6508 , H04L1/0001 , H04L1/0003 , H04L1/0015 , H04L1/0021 , H04L1/0025 , H04L1/0026 , H04L1/0045 , H04L1/0071 , H04L1/0075 , H04L1/20
摘要： Systems and Methods for controlling an interleaver are disclosed. Generally, a first and second signal are received, wherein the first and second signals are selected from the group consisting of a signal to noise ration signal, a data rate signal, and a bit error rate signal. An interleaver control signal is then generated based on the first and second signals.
摘要翻译：公开了用于控制交织器的系统和方法。通常，接收第一和第二信号，其中第一和第二信号从由信噪比信号，数据速率信号和误比特率信号组成的组中选择。然后基于第一和第二信号产生交织器控制信号。

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