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1. 发明授权

US08132036B2 Reducing latency in data transfer between asynchronous clock domains 失效
标题翻译：减少异步时钟域之间数据传输的延迟
公开(公告)号：US08132036B2
公开(公告)日：2012-03-06
申请号：US12109483
申请日：2008-04-25
申请人： Anil Pothireddy , Kirtish Karlekar , David Grant Wheeler
发明人： Anil Pothireddy , Kirtish Karlekar , David Grant Wheeler
IPC分类号： G06F1/12 , H04L7/00 , G06F13/20
CPC分类号： H04L7/0012
摘要： A method and an interfacing circuit are disclosed for transmitting data between a first clock domain operating at a first clock frequency C1 and a second clock domain operating at a second clock frequency C2. In accordance with this invention, data are transmitted from the first domain, through the interfacing circuitry, and to the second domain. Also, the interfacing circuitry includes a synchronization section that operates at a third frequency C3, which, in one embodiment, is greater than and a whole number multiple of C2. Preferably, C3 is an even whole number multiple of C2. In the preferred embodiment, a clock signal A is used to operate the second clock domain at frequency C2, and a clock signal B is used to operate the synchronization section of the interfacing circuitry at frequency C3, and clock signals A and B are source synchronized.
摘要翻译：公开了用于在以第一时钟频率C1操作的第一时钟域和在第二时钟频率C2操作的第二时钟域之间传送数据的方法和接口电路。根据本发明，数据通过接口电路从第一域发送到第二域。此外，接口电路包括在第三频率C3操作的同步部分，其在一个实施例中大于C2的整数倍。优选地，C3是C2的偶数倍数。在优选实施例中，时钟信号A用于以频率C2操作第二时钟域，并且时钟信号B用于在频率C3处操作接口电路的同步部分，并且时钟信号A和B是源同步的。

2. 发明申请

US20090271651A1 Method and System for Reducing Latency in Data Transfer Between Asynchronous Clock Domains 失效
标题翻译：减少异步时钟域之间数据传输延迟的方法和系统
公开(公告)号：US20090271651A1
公开(公告)日：2009-10-29
申请号：US12109483
申请日：2008-04-25
申请人： Anil Pothireddy , Kirtish Karlekar , David Grant Wheeler
发明人： Anil Pothireddy , Kirtish Karlekar , David Grant Wheeler
IPC分类号： G06F1/12
CPC分类号： H04L7/0012
摘要： A method and an interfacing circuit are disclosed for transmitting data between a first clock domain operating at a first clock frequency C1 and a second clock domain operating at a second clock frequency C2. In accordance with this invention, data are transmitted from the first domain, through the interfacing circuitry, and to the second domain. Also, the interfacing circuitry includes a synchronization section that operates at a third frequency C3, which, in one embodiment, is greater than and a whole number multiple of C2. Preferably, C3 is an even whole number multiple of C2. In the preferred embodiment, a clock signal A is used to operate the second clock domain at frequency C2, and a clock signal B is used to operate the synchronization section of the interfacing circuitry at frequency C3, and clock signals A and B are source synchronized.
摘要翻译：公开了用于在以第一时钟频率C1操作的第一时钟域和在第二时钟频率C2操作的第二时钟域之间传送数据的方法和接口电路。根据本发明，数据通过接口电路从第一域发送到第二域。此外，接口电路包括在第三频率C3操作的同步部分，其在一个实施例中大于C2的整数倍。优选地，C3是C2的偶数倍数。在优选实施例中，时钟信号A用于以频率C2操作第二时钟域，并且时钟信号B用于在频率C3处操作接口电路的同步部分，并且时钟信号A和B是源同步的。

3. 发明授权

US07500132B1 Method of asynchronously transmitting data between clock domains 失效
标题翻译：在时钟域之间异步传输数据的方法
公开(公告)号：US07500132B1
公开(公告)日：2009-03-03
申请号：US12101939
申请日：2008-04-11
申请人： Anil Pothireddy , Kirtish Karlekar , Grant D. Wheeler
发明人： Anil Pothireddy , Kirtish Karlekar , Grant D. Wheeler
IPC分类号： G06F1/04
CPC分类号： G06F5/06
摘要： A method of asynchronously transmitting data from a first clock domain to a second clock domain by transmitting the data from the first domain to a first register; after a first period of time, transmitting the data from the first register to a second register; after a second period of time, transmitting the data from the second register to a third register; and after a third period of time, transmitting the data from the third register to the second clock domain, where the first clock domain operates at a first frequency C1, and the second clock domain operates at a second frequency C2, C1 being faster than C2; and where: the first period of time is determined by C1; and the second and third periods of time are determined by a third frequency C3 that is greater than and a whole number multiple of C2.
摘要翻译：一种通过将数据从第一域发送到第一寄存器来将数据从第一时钟域异步发送到第二时钟域的方法; 在第一时间段之后，将数据从第一寄存器传送到第二寄存器; 在第二时间段之后，将数据从第二寄存器发送到第三寄存器; 并且在第三时间段之后，将数据从第三寄存器发送到第二时钟域，其中第一时钟域以第一频率C1操作，并且第二时钟域以第二频率C2操作，C1比C2快 ; 其中：第一个时间段由C1决定; 并且第二和第三时间段由大于C2的整数倍的第三频率C3确定。

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