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1. 发明授权

US08779551B2 Gated diode structure for eliminating RIE damage from cap removal 失效
标题翻译：门二极管结构，用于消除去除盖子的RIE损坏
公开(公告)号：US08779551B2
公开(公告)日：2014-07-15
申请号：US13489537
申请日：2012-06-06
申请人： Anthony I. Chou , Arvind Kumar , Edward P. Maciejewski , Shreesh Narasimha , Dustin K. Slisher
发明人： Anthony I. Chou , Arvind Kumar , Edward P. Maciejewski , Shreesh Narasimha , Dustin K. Slisher
IPC分类号： H01L27/06
CPC分类号： H01L21/8238 , H01L21/265 , H01L21/77 , H01L21/823835 , H01L27/0629 , H01L27/1203 , H01L29/42364 , H01L29/7391 , H01L29/861
摘要： A semiconductor structure provided with a plurality of gated-diodes having a silicided anode (p-doped region) and cathode (n-doped region) and a high-K gate stack made of non-silicided gate material, the gated-diodes being adjacent to FETs, each of which having a silicided source, a silicided drain and a silicided HiK gate stack. The semiconductor structure eliminates a cap removal RIE in a gate first High-K metal gate flow from the region of the gated-diode. The lack of silicide and the presence of a nitride barrier on the gate of the diode are preferably made during the gate first process flow. The absence of the cap removal RIE is beneficial in that diffusions of the diode are not subjected to the cap removal RIE, which avoids damage and allows retaining its highly ideal junction characteristics.
摘要翻译：一种半导体结构，其具有多个具有硅化阳极（p掺杂区域）和阴极（n掺杂区域）的门控二极管和由非硅化栅极材料制成的高K栅极堆叠，该门控二极管相邻其中每一个具有硅化源，硅化物漏极和硅化HiK栅极叠层。半导体结构消除了栅极第一高K金属栅极流从栅极二极管的区域流出的帽去除RIE。优选在栅极第一工艺流程期间，在二极管的栅极上缺少硅化物和存在氮化物阻挡层。没有帽去除RIE是有益的，因为二极管的扩散不经受帽去除RIE，这避免了损伤并且允许保持其高度理想的结特性。

2. 发明申请

US20130328124A1 GATED DIODE STRUCTURE FOR ELIMINATING RIE DAMAGE FROM CAP REMOVAL 失效
标题翻译：用于消除从盖拆卸中的RIE损伤的栅极二极管结构
公开(公告)号：US20130328124A1
公开(公告)日：2013-12-12
申请号：US13489537
申请日：2012-06-06
申请人： Anthony I. Chou , Arvind Kumar , Edward P. Maciejewski , Shreesh Narasimha , Dustin K. Slisher
发明人： Anthony I. Chou , Arvind Kumar , Edward P. Maciejewski , Shreesh Narasimha , Dustin K. Slisher
IPC分类号： H01L27/06 , H01L21/8238
CPC分类号： H01L21/8238 , H01L21/265 , H01L21/77 , H01L21/823835 , H01L27/0629 , H01L27/1203 , H01L29/42364 , H01L29/7391 , H01L29/861
摘要： A semiconductor structure provided with a plurality of gated-diodes having a silicided anode (p-doped region) and cathode (n-doped region) and a high-K gate stack made of non-silicided gate material, the gated-diodes being adjacent to FETs, each of which having a silicided source, a silicided drain and a silicided HiK gate stack. The semiconductor structure eliminates a cap removal RIE in a gate first High-K metal gate flow from the region of the gated-diode. The lack of silicide and the presence of a nitride barrier on the gate of the diode are preferably made during the gate first process flow. The absence of the cap removal RIE is beneficial in that diffusions of the diode are not subjected to the cap removal RIE, which avoids damage and allows retaining its highly ideal junction characteristics.
摘要翻译：一种半导体结构，其具有多个具有硅化阳极（p掺杂区域）和阴极（n掺杂区域）的门控二极管和由非硅化栅极材料制成的高K栅极堆叠，该门控二极管相邻其中每一个具有硅化源，硅化物漏极和硅化HiK栅极叠层。半导体结构消除了栅极第一高K金属栅极流从栅极二极管的区域流出的帽去除RIE。优选在栅极第一工艺流程期间，在二极管的栅极上缺少硅化物和存在氮化物阻挡层。没有帽去除RIE是有益的，因为二极管的扩散不经受帽去除RIE，这避免了损伤并且允许保持其高度理想的结特性。

3. 发明授权

US08232599B2 Bulk substrate FET integrated on CMOS SOI 有权
标题翻译：集成在CMOS SOI上的散装衬底FET
公开(公告)号：US08232599B2
公开(公告)日：2012-07-31
申请号：US12683456
申请日：2010-01-07
申请人： Anthony I. Chou , Arvind Kumar , Shreesh Narasimha , Ning Su , Huiling Shang
发明人： Anthony I. Chou , Arvind Kumar , Shreesh Narasimha , Ning Su , Huiling Shang
IPC分类号： H01L27/12 , H01L21/86
CPC分类号： H01L27/1207 , H01L21/84
摘要： An integrated circuit is provided that integrates an bulk FET and an SOI FET on the same chip, where the bulk FET includes a gate conductor over a gate oxide formed over a bulk substrate, where the gate dielectric of the bulk FET has the same thickness and is substantially coplanar with the buried insulating layer of the SOI FET. In a preferred embodiment, the bulk FET is formed from an SOI wafer by forming bulk contact trenches through the SOI layer and the buried insulating layer of the SOI wafer adjacent an active region of the SOI layer in a designated bulk device region. The active region of the SOI layer adjacent the bulk contact trenches forms the gate conductor of the bulk FET which overlies a portion of the underlying buried insulating layer, which forms the gate dielectric of the bulk FET.
摘要翻译：提供了一种集成电路，其将同一芯片上的体FET和SOI FET集成在一起，其中，本体FET包括在大块衬底上形成的栅极氧化物上的栅极导体，其中本体FET的栅极电介质具有相同的厚度，与SOI FET的掩埋绝缘层基本共面。在优选实施例中，通过在指定的大容量器件区域中与SOI层的有源区相邻的SOI层和SOI晶片的掩埋绝缘层形成体接触沟槽，从SOI晶片形成本体FET。邻近体接触沟槽的SOI层的有源区域形成体FET的栅极导体，其覆盖形成本体FET的栅极电介质的下层掩埋绝缘层的一部分。

4. 发明申请

US20120187492A1 BULK SUBSTRATE FET INTEGRATED ON CMOS SOI 有权
标题翻译：集成在CMOS SOI上的基极FET
公开(公告)号：US20120187492A1
公开(公告)日：2012-07-26
申请号：US13425681
申请日：2012-03-21
申请人： Anthony I. Chou , Arvind Kumar , Shreesh Narasimha , Ning Su , Huiling Shang
发明人： Anthony I. Chou , Arvind Kumar , Shreesh Narasimha , Ning Su , Huiling Shang
IPC分类号： H01L27/088
CPC分类号： H01L27/1207 , H01L21/84
摘要： An integrated circuit is provided that integrates an bulk FET and an SOI FET on the same chip, where the bulk FET includes a gate conductor over a gate oxide formed over a bulk substrate, where the gate dielectric of the bulk FET has the same thickness and is substantially coplanar with the buried insulating layer of the SOI FET. In a preferred embodiment, the bulk FET is formed from an SOI wafer by forming bulk contact trenches through the SOI layer and the buried insulating layer of the SOI wafer adjacent an active region of the SOI layer in a designated bulk device region. The active region of the SOI layer adjacent the bulk contact trenches forms the gate conductor of the bulk FET which overlies a portion of the underlying buried insulating layer, which forms the gate dielectric of the bulk FET.
摘要翻译：提供了一种集成电路，其将同一芯片上的体FET和SOI FET集成在一起，其中，本体FET包括在大块衬底上形成的栅极氧化物上的栅极导体，其中本体FET的栅极电介质具有相同的厚度，与SOI FET的掩埋绝缘层基本共面。在优选实施例中，通过在指定的大容量器件区域中与SOI层的有源区相邻的SOI层和SOI晶片的掩埋绝缘层形成体接触沟槽，从SOI晶片形成本体FET。邻近体接触沟槽的SOI层的有源区域形成体FET的栅极导体，其覆盖形成本体FET的栅极电介质的下层掩埋绝缘层的一部分。

5. 发明授权

US07956415B2 SOI transistor having a carrier recombination structure in a body 失效
标题翻译：在体内具有载流子复合结构的SOI晶体管
公开(公告)号：US07956415B2
公开(公告)日：2011-06-07
申请号：US12133686
申请日：2008-06-05
申请人： Anthony I. Chou , Andres Bryant , Arvind Kumar , Shreesh Narasimha
发明人： Anthony I. Chou , Andres Bryant , Arvind Kumar , Shreesh Narasimha
IPC分类号： H01L27/12
CPC分类号： H01L29/66772 , H01L29/78603 , H01L29/78612
摘要： A top semiconductor layer is formed with two different thicknesses such that a step is formed underneath a body region of a semiconductor-on-insulator (SOI) field effect transistor at the interface between a top semiconductor layer and an underlying buried insulator layer. The interface and the accompanying interfacial defects in the body region provide recombination centers, which increase the recombination rate between the holes and electrons in the body region. Optionally, a spacer portion, comprising a material that functions as recombination centers, is formed on sidewalls of the step to provide an enhanced recombination rate between holes and electrons in the body region, which increases the bipolar breakdown voltage of a SOI field effect transistor.
摘要翻译：顶部半导体层形成有两个不同的厚度，使得在顶部半导体层和下面的掩埋绝缘体层之间的界面处在绝缘体上半导体（SOI）场效应晶体管的体区之下形成台阶。身体区域中的界面和伴随的界面缺陷提供了复合中心，这增加了身体区域中的空穴和电子之间的复合速率。任选地，包括作为复合中心的材料的间隔物部分形成在台阶的侧壁上，以在体区中的空穴和电子之间提供增强的复合率，这增加了SOI场效应晶体管的双极击穿电压。

6. 发明申请

US20110163383A1 BULK SUBSTRATE FET INTEGRATED ON CMOS SOI 有权
标题翻译：集成在CMOS SOI上的基极FET
公开(公告)号：US20110163383A1
公开(公告)日：2011-07-07
申请号：US12683456
申请日：2010-01-07
申请人： Anthony I. Chou , Arvind Kumar , Shreesh Narasimha , Ning Su , Huiling Shang
发明人： Anthony I. Chou , Arvind Kumar , Shreesh Narasimha , Ning Su , Huiling Shang
IPC分类号： H01L27/12 , H01L21/86
CPC分类号： H01L27/1207 , H01L21/84
摘要： An integrated circuit is provided that integrates an bulk FET and an SOI FET on the same chip, where the bulk FET includes a gate conductor over a gate oxide formed over a bulk substrate, where the gate dielectric of the bulk FET has the same thickness and is substantially coplanar with the buried insulating layer of the SOI FET. In a preferred embodiment, the bulk FET is formed from an SOI wafer by forming bulk contact trenches through the SOI layer and the buried insulating layer of the SOI wafer adjacent an active region of the SOI layer in a designated bulk device region. The active region of the SOI layer adjacent the bulk contact trenches forms the gate conductor of the bulk FET which overlies a portion of the underlying buried insulating layer, which forms the gate dielectric of the bulk FET.
摘要翻译：提供了一种集成电路，其将同一芯片上的体FET和SOI FET集成在一起，其中，本体FET包括在大块衬底上形成的栅极氧化物上的栅极导体，其中本体FET的栅极电介质具有相同的厚度，与SOI FET的掩埋绝缘层基本共面。在优选实施例中，通过在指定的大容量器件区域中与SOI层的有源区相邻的SOI层和SOI晶片的掩埋绝缘层形成体接触沟槽，从SOI晶片形成本体FET。邻近体接触沟槽的SOI层的有源区域形成体FET的栅极导体，其覆盖形成本体FET的栅极电介质的下层掩埋绝缘层的一部分。

7. 发明申请

US20130264679A1 PLANAR POLYSILICON REGIONS FOR PRECISION RESISTORS AND ELECTRICAL FUSES AND METHOD OF FABRICATION 有权
标题翻译：用于精密电阻器和电熔体的平面多晶硅区域和制造方法
公开(公告)号：US20130264679A1
公开(公告)日：2013-10-10
申请号：US13440172
申请日：2012-04-05
申请人： Arvind Kumar , Anthony I. Chou , Renee T. Mo , Shreesh Narasimha
发明人： Arvind Kumar , Anthony I. Chou , Renee T. Mo , Shreesh Narasimha
IPC分类号： H01L29/86 , H01L21/02
CPC分类号： H01L23/5256 , H01L21/84 , H01L28/20 , H01L29/86 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor structure providing a precision resistive element and method of fabrication is disclosed. Polysilicon is embedded in a silicon substrate. The polysilicon may be doped to control the resistance. Embodiments may include resistors, eFuses, and silicon-on-insulator structures. Some embodiments may include non-rectangular cross sections.
摘要翻译：公开了提供精密电阻元件的半导体结构和制造方法。多晶硅嵌入在硅衬底中。可以掺杂多晶硅以控制电阻。实施例可以包括电阻器，eFuse和绝缘体上硅结构。一些实施例可以包括非矩形横截面。

8. 发明申请

US20090302386A1 SOI TRANSISTOR HAVING A CARRIER RECOMBINATION STRUCTURE IN A BODY 失效
标题翻译：具有体内载体重构结构的SOI晶体管
公开(公告)号：US20090302386A1
公开(公告)日：2009-12-10
申请号：US12133686
申请日：2008-06-05
申请人： Anthony I. Chou , Andres Bryant , Arvind Kumar , Shreesh Narasimha
发明人： Anthony I. Chou , Andres Bryant , Arvind Kumar , Shreesh Narasimha
IPC分类号： H01L29/786 , H01L21/336
CPC分类号： H01L29/66772 , H01L29/78603 , H01L29/78612
摘要： A top semiconductor layer is formed with two different thicknesses such that a step is formed underneath a body region of a semiconductor-on-insulator (SOI) field effect transistor at the interface between a top semiconductor layer and an underlying buried insulator layer. The interface and the accompanying interfacial defects in the body region provide recombination centers, which increase the recombination rate between the holes and electrons in the body region. Optionally, a spacer portion, comprising a material that functions as recombination centers, is formed on sidewalls of the step to provide an enhanced recombination rate between holes and electrons in the body region, which increases the bipolar breakdown voltage of a SOI field effect transistor.
摘要翻译：顶部半导体层形成有两个不同的厚度，使得在顶部半导体层和下面的掩埋绝缘体层之间的界面处在绝缘体上半导体（SOI）场效应晶体管的体区之下形成台阶。身体区域中的界面和伴随的界面缺陷提供了复合中心，这增加了身体区域中的空穴和电子之间的复合速率。任选地，包括作为复合中心的材料的间隔物部分形成在台阶的侧壁上，以在体区中的空穴和电子之间提供增强的复合率，这增加了SOI场效应晶体管的双极击穿电压。

9. 发明授权

US08558313B2 Bulk substrate FET integrated on CMOS SOI 有权
标题翻译：集成在CMOS SOI上的散装衬底FET
公开(公告)号：US08558313B2
公开(公告)日：2013-10-15
申请号：US13425681
申请日：2012-03-21
申请人： Anthony I. Chou , Arvind Kumar , Shreesh Narasimha , Ning Su , Huiling Shang
发明人： Anthony I. Chou , Arvind Kumar , Shreesh Narasimha , Ning Su , Huiling Shang
IPC分类号： H01L27/088
CPC分类号： H01L27/1207 , H01L21/84
摘要： An integrated circuit is provided that integrates an bulk FET and an SOI FET on the same chip, where the bulk FET includes a gate conductor over a gate oxide formed over a bulk substrate, where the gate dielectric of the bulk FET has the same thickness and is substantially coplanar with the buried insulating layer of the SOI FET. In a preferred embodiment, the bulk FET is formed from an SOI wafer by forming bulk contact trenches through the SOI layer and the buried insulating layer of the SOI wafer adjacent an active region of the SOI layer in a designated bulk device region. The active region of the SOI layer adjacent the bulk contact trenches forms the gate conductor of the bulk FET which overlies a portion of the underlying buried insulating layer, which forms the gate dielectric of the bulk FET.
摘要翻译：提供了一种集成电路，其将同一芯片上的体FET和SOI FET集成在一起，其中，本体FET包括在大块衬底上形成的栅极氧化物上的栅极导体，其中本体FET的栅极电介质具有相同的厚度，与SOI FET的掩埋绝缘层基本共面。在优选实施例中，通过在指定的大容量器件区域中与SOI层的有源区相邻的SOI层和SOI晶片的掩埋绝缘层形成体接触沟槽，从SOI晶片形成体FET。邻近体接触沟槽的SOI层的有源区域形成体FET的栅极导体，其覆盖形成本体FET的栅极电介质的下层掩埋绝缘层的一部分。

10. 发明授权

US08343781B2 Electrical mask inspection 失效
标题翻译：电气面罩检查
公开(公告)号：US08343781B2
公开(公告)日：2013-01-01
申请号：US12886612
申请日：2010-09-21
申请人： Arvind Kumar , Anthony I-Chih Chou , Shreesh Narasimha
发明人： Arvind Kumar , Anthony I-Chih Chou , Shreesh Narasimha
IPC分类号： G01R31/26 , H01L21/66
CPC分类号： H01L23/544 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： An apparatus and method for electrical mask inspection is disclosed. A scan chain is formed amongst two metal layers and a via layer. One of the three layers is a functional layer under test, and the other two layers are test layers. A resistance measurement of the scan chain is used to determine if a potential defect exists within one of the vias or metal segments comprising the scan chain.
摘要翻译：公开了一种用于电气掩模检查的装置和方法。在两个金属层和通孔层之间形成扫描链。三层之一是被测功能层，另外两层是测试层。使用扫描链的电阻测量来确定在包括扫描链的通孔或金属段之一内是否存在潜在缺陷。

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