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1. 发明授权

US08779551B2 Gated diode structure for eliminating RIE damage from cap removal 失效
标题翻译：门二极管结构，用于消除去除盖子的RIE损坏
公开(公告)号：US08779551B2
公开(公告)日：2014-07-15
申请号：US13489537
申请日：2012-06-06
申请人： Anthony I. Chou , Arvind Kumar , Edward P. Maciejewski , Shreesh Narasimha , Dustin K. Slisher
发明人： Anthony I. Chou , Arvind Kumar , Edward P. Maciejewski , Shreesh Narasimha , Dustin K. Slisher
IPC分类号： H01L27/06
CPC分类号： H01L21/8238 , H01L21/265 , H01L21/77 , H01L21/823835 , H01L27/0629 , H01L27/1203 , H01L29/42364 , H01L29/7391 , H01L29/861
摘要： A semiconductor structure provided with a plurality of gated-diodes having a silicided anode (p-doped region) and cathode (n-doped region) and a high-K gate stack made of non-silicided gate material, the gated-diodes being adjacent to FETs, each of which having a silicided source, a silicided drain and a silicided HiK gate stack. The semiconductor structure eliminates a cap removal RIE in a gate first High-K metal gate flow from the region of the gated-diode. The lack of silicide and the presence of a nitride barrier on the gate of the diode are preferably made during the gate first process flow. The absence of the cap removal RIE is beneficial in that diffusions of the diode are not subjected to the cap removal RIE, which avoids damage and allows retaining its highly ideal junction characteristics.
摘要翻译：一种半导体结构，其具有多个具有硅化阳极（p掺杂区域）和阴极（n掺杂区域）的门控二极管和由非硅化栅极材料制成的高K栅极堆叠，该门控二极管相邻其中每一个具有硅化源，硅化物漏极和硅化HiK栅极叠层。半导体结构消除了栅极第一高K金属栅极流从栅极二极管的区域流出的帽去除RIE。优选在栅极第一工艺流程期间，在二极管的栅极上缺少硅化物和存在氮化物阻挡层。没有帽去除RIE是有益的，因为二极管的扩散不经受帽去除RIE，这避免了损伤并且允许保持其高度理想的结特性。

2. 发明申请

US20130328124A1 GATED DIODE STRUCTURE FOR ELIMINATING RIE DAMAGE FROM CAP REMOVAL 失效
标题翻译：用于消除从盖拆卸中的RIE损伤的栅极二极管结构
公开(公告)号：US20130328124A1
公开(公告)日：2013-12-12
申请号：US13489537
申请日：2012-06-06
申请人： Anthony I. Chou , Arvind Kumar , Edward P. Maciejewski , Shreesh Narasimha , Dustin K. Slisher
发明人： Anthony I. Chou , Arvind Kumar , Edward P. Maciejewski , Shreesh Narasimha , Dustin K. Slisher
IPC分类号： H01L27/06 , H01L21/8238
CPC分类号： H01L21/8238 , H01L21/265 , H01L21/77 , H01L21/823835 , H01L27/0629 , H01L27/1203 , H01L29/42364 , H01L29/7391 , H01L29/861
摘要： A semiconductor structure provided with a plurality of gated-diodes having a silicided anode (p-doped region) and cathode (n-doped region) and a high-K gate stack made of non-silicided gate material, the gated-diodes being adjacent to FETs, each of which having a silicided source, a silicided drain and a silicided HiK gate stack. The semiconductor structure eliminates a cap removal RIE in a gate first High-K metal gate flow from the region of the gated-diode. The lack of silicide and the presence of a nitride barrier on the gate of the diode are preferably made during the gate first process flow. The absence of the cap removal RIE is beneficial in that diffusions of the diode are not subjected to the cap removal RIE, which avoids damage and allows retaining its highly ideal junction characteristics.
摘要翻译：一种半导体结构，其具有多个具有硅化阳极（p掺杂区域）和阴极（n掺杂区域）的门控二极管和由非硅化栅极材料制成的高K栅极堆叠，该门控二极管相邻其中每一个具有硅化源，硅化物漏极和硅化HiK栅极叠层。半导体结构消除了栅极第一高K金属栅极流从栅极二极管的区域流出的帽去除RIE。优选在栅极第一工艺流程期间，在二极管的栅极上缺少硅化物和存在氮化物阻挡层。没有帽去除RIE是有益的，因为二极管的扩散不经受帽去除RIE，这避免了损伤并且允许保持其高度理想的结特性。

3. 发明授权

US07227204B2 Structure for improved diode ideality 有权
标题翻译：改善二极管理想的结构
公开(公告)号：US07227204B2
公开(公告)日：2007-06-05
申请号：US10906366
申请日：2005-02-16
申请人： Edward P. Maciejewski , Sherry A. Womack , Shreesh Narasimha , Christopher D. Sheraw
发明人： Edward P. Maciejewski , Sherry A. Womack , Shreesh Narasimha , Christopher D. Sheraw
IPC分类号： H01L29/76 , H01L31/119 , H01L23/58 , H01L29/861 , H01L29/00
CPC分类号： H01L27/0629 , H01L27/0814 , H01L29/66136 , H01L29/861
摘要： A device is provided which includes a single-crystal semiconductor region disposed in a substrate. The single-crystal region includes a first semiconductor material and a diode disposed in the single-crystal region. The diode includes an anode region including a first alloy region, being an alloy of the first semiconductor material with a second semiconductor material, and a second region which consists essentially of the first semiconductor material, the diode further including a cathode region.
摘要翻译：提供一种器件，其包括设置在衬底中的单晶半导体区域。单晶区域包括设置在单晶区域中的第一半导体材料和二极管。该二极管包括一个阳极区域，该阳极区域包括第一合金区域，该第一合金区域是第一半导体材料与第二半导体材料的合金，以及第二区域，该第二区域基本上由第一半导体材料组成，二极管还包括阴极区域。

4. 发明授权

US06991979B2 Method for avoiding oxide undercut during pre-silicide clean for thin spacer FETs 有权
公开(公告)号：US06991979B2
公开(公告)日：2006-01-31
申请号：US10605311
申请日：2003-09-22
申请人： Atul C. Ajmera , Andres Bryant , Percy V. Gilbert , Michael A Gribelyuk , Edward P. Maciejewski , Renee T. Mo , Shreesh Narasimha
发明人： Atul C. Ajmera , Andres Bryant , Percy V. Gilbert , Michael A Gribelyuk , Edward P. Maciejewski , Renee T. Mo , Shreesh Narasimha
IPC分类号： H01L21/8238
CPC分类号： H01L21/02063 , H01L21/31116 , H01L21/823835 , H01L21/823864 , H01L29/665 , H01L29/6653 , H01L29/6656 , H01L2924/0002 , H01L2924/00
摘要： A method for forming a CMOS device in a manner so as to avoid dielectric layer undercut during a pre-silicide cleaning step is described. During formation of CMOS device comprising a gate stack on a semiconductor substrate surface, the patterned gate stack including gate dielectric below a conductor with vertical sidewalls, a dielectric layer is formed thereover and over the substrate surfaces. Respective nitride spacer elements overlying the dielectric layer are formed at each vertical sidewall. The dielectric layer on the substrate surface is removed using an etch process such that a portion of the dielectric layer underlying each spacer remains. Then, a nitride layer is deposited over the entire sample (the gate stack, the spacer elements at each gate sidewall, and substrate surfaces) and subsequently removed by an etch process such that only a portion of said nitride film (the “plug”) remains. The plug seals and encapsulates the dielectric layer underlying each said spacer, thus preventing the dielectric material from being undercut during the subsequent pre-silicide clean process. By preventing undercut, this invention also prevents the etch-stop film (deposited prior to contact formation) from coming into contact with the gate oxide. Thus, the integration of thin-spacer transistor geometries, which are required for improving transistor drive current, is enabled.

5. 发明授权

US07091128B2 Method for avoiding oxide undercut during pre-silicide clean for thin spacer FETs 失效
标题翻译：避免氧化物底切在薄间隔FET预硅化物清洗过程中的方法
公开(公告)号：US07091128B2
公开(公告)日：2006-08-15
申请号：US11266855
申请日：2005-11-04
申请人： Atul C. Ajmera , Andres Bryant , Percy V. Gilbert , Michael A. Gribelyuk , Edward P. Maciejewski , Renee T. Mo , Shreesh Narasimha
发明人： Atul C. Ajmera , Andres Bryant , Percy V. Gilbert , Michael A. Gribelyuk , Edward P. Maciejewski , Renee T. Mo , Shreesh Narasimha
IPC分类号： H01L21/302
CPC分类号： H01L21/02063 , H01L21/31116 , H01L21/823835 , H01L21/823864 , H01L29/665 , H01L29/6653 , H01L29/6656 , H01L2924/0002 , H01L2924/00
摘要： A method for forming a CMOS device in a manner so as to avoid dielectric layer undercut during a pre-silicide cleaning step is described. During formation of CMOS device comprising a gate stack on a semiconductor substrate surface, the patterned gate stack including gate dielectric below a conductor with vertical sidewalls, a dielectric layer is formed thereover and over the substrate surfaces. Respective nitride spacer elements overlying the dielectric layer are formed at each vertical sidewall. The dielectric layer on the substrate surface is removed using an etch process such that a portion of the dielectric layer underlying each spacer remains. Then, a nitride layer is deposited over the entire sample (the gate stack, the spacer elements at each gate sidewall, and substrate surfaces) and subsequently removed by an etch process such that only a portion of said nitride film (the “plug”) remains. The plug seals and encapsulates the dielectric layer underlying each said spacer, thus preventing the dielectric material from being undercut during the subsequent pre-silicide clean process. By preventing undercut, this invention also prevents the etch-stop film (deposited prior to contact formation) from coming into contact with the gate oxide. Thus, the integration of thin-spacer transistor geometries, which are required for improving transistor drive current, is enabled.
摘要翻译：描述了在预硅化物清洁步骤期间以避免电介质层底切的方式形成CMOS器件的方法。在形成包括半导体衬底表面上的栅极堆叠的CMOS器件的情况下，图案化栅极堆叠包括在具有垂直侧壁的导体下方的栅极电介质，在衬底表面之上和之上形成介电层。在每个垂直侧壁处形成覆盖在电介质层上的各种氮化物间隔元件。使用蚀刻工艺去除衬底表面上的电介质层，使得保留每个间隔物下面的介电层的一部分。然后，在整个样品（栅极堆叠，每个栅极侧壁和衬底表面处的间隔元件）上沉积氮化物层，然后通过蚀刻工艺去除，使得仅一部分所述氮化物膜（“插塞”）遗迹。插头密封并封装每个所述间隔件下面的电介质层，从而防止在随后的硅化物前处理过程中电介质材料被切削。通过防止底切，本发明还防止蚀刻停止膜（在接触形成之前沉积）与栅极氧化物接触。因此，能够实现提高晶体管驱动电流所需的薄间隔晶体管几何形状的集成。

6. 发明授权

US08912626B2 eFuse and method of fabrication 有权
标题翻译： eFuse和制造方法
公开(公告)号：US08912626B2
公开(公告)日：2014-12-16
申请号：US13013055
申请日：2011-01-25
申请人： Edward P. Maciejewski , Dustin Kenneth Slisher , Stefan Zollner
发明人： Edward P. Maciejewski , Dustin Kenneth Slisher , Stefan Zollner
IPC分类号： H01L23/525
CPC分类号： H01L23/5256 , H01L21/3065 , H01L21/31116 , H01L21/32053 , H01L2924/0002 , H01L2924/00
摘要： An improved eFuse and method of fabrication is disclosed. A cavity is formed in a substrate, which results in a polysilicon line having an increased depth in the area of the fuse, while having a reduced depth in areas outside of the fuse. The increased depth reduces the chance of the polysilicon line entering the fully silicided state. The cavity may be formed with a wet or dry etch.
摘要翻译：公开了改进的eFuse和制造方法。在衬底中形成腔，这导致多晶硅线在熔丝的面积上具有增加的深度，同时在熔丝外部的区域具有减小的深度。增加的深度降低了多晶硅线路进入完全硅化状态的机会。空腔可以用湿或干蚀刻形成。

7. 发明授权

US08513085B2 Structure and method to improve threshold voltage of MOSFETs including a high k dielectric 有权
标题翻译：提高包括高k电介质的MOSFET的阈值电压的结构和方法
公开(公告)号：US08513085B2
公开(公告)日：2013-08-20
申请号：US13409693
申请日：2012-03-01
申请人： Sunfei Fang , Brian J. Greene , Effendi Leobandung , Qingqing Liang , Edward P. Maciejewski , Yanfeng Wang
发明人： Sunfei Fang , Brian J. Greene , Effendi Leobandung , Qingqing Liang , Edward P. Maciejewski , Yanfeng Wang
IPC分类号： H01L21/8238
CPC分类号： H01L21/823857 , H01L21/28247 , H01L21/823842 , H01L21/823864 , H01L29/517 , H01L29/6659 , H01L29/66636
摘要： Threshold voltage controlled semiconductor structures are provided in which a conformal nitride-containing liner is located on at least exposed sidewalls of a patterned gate dielectric material having a dielectric constant of greater than silicon oxide. The conformal nitride-containing liner is a thin layer that is formed using a low temperature (less than 500° C.) nitridation process.
摘要翻译：提供了阈值电压控制的半导体结构，其中共形含氮化物的衬垫位于具有大于氧化硅的介电常数的图案化栅极电介质材料的至少暴露的侧壁上。含氮氮化物的内衬是使用低温（小于500℃）的氮化工艺形成的薄层。

8. 发明申请

US20110031554A1 STRUCTURE AND METHOD TO IMPROVE THRESHOLD VOLTAGE OF MOSFETS INCLUDING A HIGH K DIELECTRIC 有权
标题翻译：提高包括高K电介质的MOSFET的阈值电压的结构和方法
公开(公告)号：US20110031554A1
公开(公告)日：2011-02-10
申请号：US12535183
申请日：2009-08-04
申请人： Sunfei Fang , Brian J. Greene , Effendi Leobandung , Qingqing Liang , Edward P. Maciejewski , Yanfeng Wang
发明人： Sunfei Fang , Brian J. Greene , Effendi Leobandung , Qingqing Liang , Edward P. Maciejewski , Yanfeng Wang
IPC分类号： H01L27/092 , H01L21/336 , H01L29/78
CPC分类号： H01L21/823857 , H01L21/28247 , H01L21/823842 , H01L21/823864 , H01L29/517 , H01L29/6659 , H01L29/66636
摘要： A method of forming threshold voltage controlled semiconductor structures is provided in which a conformal nitride-containing liner is formed on at least exposed sidewalls of a patterned gate dielectric material having a dielectric constant of greater than silicon oxide. The conformal nitride-containing liner is a thin layer that is formed using a low temperature (less than 500° C.) nitridation process.
摘要翻译：提供了形成阈值电压控制的半导体结构的方法，其中在至少暴露的具有大于氧化硅的介电常数的栅极介电材料的侧壁上形成共形氮化物衬里。含氮氮化物的内衬是使用低温（小于500℃）的氮化工艺形成的薄层。

9. 发明授权

US07504875B2 Methods and apparatus for characterizing electronic fuses used to personalize an integrated circuit 失效
标题翻译：用于表征用于个性化集成电路的电子保险丝的方法和装置
公开(公告)号：US07504875B2
公开(公告)日：2009-03-17
申请号：US11923932
申请日：2007-10-25
申请人： Manjul Bhushan , Mark B. Ketchen , Chandrasekharan Kothandaraman , Edward P. Maciejewski
发明人： Manjul Bhushan , Mark B. Ketchen , Chandrasekharan Kothandaraman , Edward P. Maciejewski
IPC分类号： H01H37/76
CPC分类号： G01R31/31853 , G01R31/30 , G01R31/3004
摘要： An integrated circuit device having at least one fuse capable of being blown in order to provide measurements of fuse current-voltage characteristics is provided. The integrated circuit device also provides at least one pulse generation circuit associated with the fuse and capable of generating a pulse to blow the fuse through one or more DC input signals.
摘要翻译：提供一种具有至少一个能够被熔断以便提供熔丝电流 - 电压特性测量的熔断器的集成电路器件。集成电路装置还提供与熔丝相关联的至少一个脉冲发生电路，并且能够产生脉冲以通过一个或多个DC输入信号来熔断熔丝。

10. 发明授权

US08354309B2 Method of providing threshold voltage adjustment through gate dielectric stack modification 有权
标题翻译：通过栅介质叠层修改提供阈值电压调整的方法
公开(公告)号：US08354309B2
公开(公告)日：2013-01-15
申请号：US13347014
申请日：2012-01-10
申请人： Brian J. Greene , Michael P. Chudzik , Shu-Jen Han , William K. Henson , Yue Liang , Edward P. Maciejewski , Myung-Hee Na , Edward J. Nowak , Xiaojun Yu
发明人： Brian J. Greene , Michael P. Chudzik , Shu-Jen Han , William K. Henson , Yue Liang , Edward P. Maciejewski , Myung-Hee Na , Edward J. Nowak , Xiaojun Yu
IPC分类号： H01L21/00 , H01L21/84
CPC分类号： H01L21/823462 , H01L21/28229 , H01L21/84 , H01L27/1203
摘要： Multiple types of gate stacks are formed on a doped semiconductor well. A high dielectric constant (high-k) gate dielectric is formed on the doped semiconductor well. A metal gate layer is formed in one device area, while the high-k gate dielectric is exposed in other device areas. Threshold voltage adjustment oxide layers having different thicknesses are formed in the other device areas. A conductive gate material layer is then formed over the threshold voltage adjustment oxide layers. One type of field effect transistors includes a gate dielectric including a high-k gate dielectric portion. Other types of field effect transistors include a gate dielectric including a high-k gate dielectric portion and a first threshold voltage adjustment oxide portions having different thicknesses. Field effect transistors having different threshold voltages are provided by employing different gate dielectric stacks and doped semiconductor wells having the same dopant concentration.
摘要翻译：在掺杂半导体阱上形成多种类型的栅叠层。在掺杂半导体阱上形成高介电常数（高k）栅极电介质。在一个器件区域中形成金属栅极层，而在其他器件区域中暴露高k栅极电介质。在其他器件区域中形成具有不同厚度的阈值电压调节氧化物层。然后在阈值电压调整氧化物层上形成导电栅极材料层。一种类型的场效应晶体管包括包括高k栅极电介质部分的栅极电介质。其他类型的场效应晶体管包括包括高k栅极电介质部分的栅极电介质和具有不同厚度的第一阈值电压调整氧化物部分。具有不同阈值电压的场效应晶体管通过采用具有相同掺杂剂浓度的不同栅极电介质叠层和掺杂半导体阱来提供。

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