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1. 发明授权

US09407262B2 Dynamic voltage and frequency management 有权
公开(公告)号：US09407262B2
公开(公告)日：2016-08-02
申请号：US14942375
申请日：2015-11-16
申请人： Apple Inc.
发明人： Vincent R. von Kaenel
IPC分类号： H03K19/00 , G06F1/32
CPC分类号： H03K19/0008 , G06F1/3203 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： In one embodiment, an integrated circuit includes a self calibration unit configured to iterate a test on a logic circuit in the integrated circuit at respectively lower supply voltage magnitudes until the test fails. A lowest supply voltage magnitude at which the test passes is used to generate a requested supply voltage magnitude for the integrated circuit. In an embodiment, an integrated circuit includes a series connection of logic gates physically distributed over an area of the integrated circuit, and a measurement unit configured to launch a logical transition into the series and detect a corresponding transition at the output of the series. The amount of time between the launch and the detection is used to request a supply voltage magnitude for the integrated circuit.

2. 发明授权

US09218049B2 Dynamic voltage and frequency management 有权
标题翻译：动态电压和频率管理
公开(公告)号：US09218049B2
公开(公告)日：2015-12-22
申请号：US13915850
申请日：2013-06-12
申请人： Apple Inc.
发明人： Vincent R. von Kaenel
IPC分类号： H03K19/00 , G06F1/32
CPC分类号： H03K19/0008 , G06F1/3203 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： In one embodiment, an integrated circuit includes a self calibration unit configured to iterate a test on a logic circuit in the integrated circuit at respectively lower supply voltage magnitudes until the test fails. A lowest supply voltage magnitude at which the test passes is used to generate a requested supply voltage magnitude for the integrated circuit. In an embodiment, an integrated circuit includes a series connection of logic gates physically distributed over an area of the integrated circuit, and a measurement unit configured to launch a logical transition into the series and detect a corresponding transition at the output of the series. The amount of time between the launch and the detection is used to request a supply voltage magnitude for the integrated circuit.
摘要翻译：在一个实施例中，集成电路包括自校准单元，其被配置为在分别较低的电源电压幅度下对集成电路中的逻辑电路进行测试，直到测试失败为止。测试通过的最低电源电压幅度用于为集成电路产生所请求的电源电压幅度。在一个实施例中，集成电路包括物理分布在集成电路的区域上的逻辑门的串联连接，以及测量单元，被配置为将逻辑跃迁发射到该系列中，并且检测在该系列的输出处的对应转变。发射和检测之间的时间量用于请求集成电路的电源电压幅值。

3. 发明授权

US09129708B2 Integrated circuit with separate supply voltage for memory that is different from logic circuit supply voltage 有权
标题翻译：具有不同于逻辑电路电源电压的存储器的单独电源电压的集成电路
公开(公告)号：US09129708B2
公开(公告)日：2015-09-08
申请号：US14467633
申请日：2014-08-25
申请人： Apple Inc.
发明人： Brian J. Campbell , Vincent R. von Kaenel , Daniel C. Murray , Gregory S. Scott , Sribalan Santhanam
IPC分类号： G11C7/00 , G11C11/419 , G11C5/14 , G11C8/08 , G11C11/417 , G11C7/12
CPC分类号： G11C11/419 , G11C5/143 , G11C7/00 , G11C7/12 , G11C8/08 , G11C11/417 , H03K3/35613 , H03K19/018528
摘要： In one embodiment, an integrated circuit includes at least one logic circuit supplied by a first supply voltage and at least one memory circuit coupled to the logic circuit and supplied by a second supply voltage. The memory circuit is configured to be read and written responsive to the logic circuit even if the first supply voltage is less than the second supply voltage during use. In another embodiment, a method includes a logic circuit reading a memory cell, the logic circuit supplied by a first supply voltage; and the memory cell responding to the read using signals that are referenced to the first supply voltage, wherein the memory cell is supplied with a second supply voltage that is greater than the first supply voltage during use.
摘要翻译：在一个实施例中，集成电路包括由第一电源电压提供的至少一个逻辑电路和耦合到逻辑电路并由第二电源电压提供的至少一个存储器电路。即使在使用期间第一电源电压小于第二电源电压，存储器电路被配置为响应于逻辑电路被读取和写入。在另一个实施例中，一种方法包括：读取存储单元的逻辑电路，由第一电源电压提供的逻辑电路; 并且所述存储单元响应于所读取的使用参考于所述第一电源电压的信号，其中所述存储单元被提供在使用期间大于所述第一电源电压的第二电源电压。

4. 发明申请

US20200026345A1 COMPUTER SYSTEM POWER MONITORING 审中-公开
公开(公告)号：US20200026345A1
公开(公告)日：2020-01-23
申请号：US16039842
申请日：2018-07-19
申请人： Apple Inc.
发明人： Jay B. Fletcher , Karthik Manickam , Bo Yang , Vincent R. von Kaenel , Shawn Searles , Hubert Attah , Nir Dahan , Olivier Girard
IPC分类号： G06F1/32 , G01R31/28
摘要： A voltage regulator circuit included in a computer system may generate a voltage level on a power supply signal using a source power supply signal and based initial values of one or more operation parameters derived from wafer-level test data. One or more operation characteristics of the voltage regulator circuit may be sampled, by a measurement circuit, at multiple time points to generated measurement data. A control circuit may adapt operation of the voltage regulator circuit based on the measurement data.

5. 发明申请

US20160307621A1 Integrated Circuit With Separate Supply Voltage For Memory That Is Different From Logic Circuit Supply Voltage 审中-公开
公开(公告)号：US20160307621A1
公开(公告)日：2016-10-20
申请号：US15133400
申请日：2016-04-20
申请人： Apple Inc.
发明人： Brian J. Campbell , Vincent R. von Kaenel , Daniel C. Murray , Gregory S. Scott , Sribalan Santhanam
IPC分类号： G11C11/419 , H03K19/0185 , H03K3/356
CPC分类号： G11C11/419 , G11C5/143 , G11C7/00 , G11C7/12 , G11C8/08 , G11C11/417 , H03K3/35613 , H03K19/018528
摘要： In one embodiment, an integrated circuit includes at least one logic circuit supplied by a first supply voltage and at least one memory circuit coupled to the logic circuit and supplied by a second supply voltage. The memory circuit is configured to be read and written responsive to the logic circuit even if the first supply voltage is less than the second supply voltage during use. In another embodiment, a method includes a logic circuit reading a memory cell, the logic circuit supplied by a first supply voltage; and the memory cell responding to the read using signals that are referenced to the first supply voltage, wherein the memory cell is supplied with a second supply voltage that is greater than the first supply voltage during use.

6. 发明授权

US08848463B2 Integrated circuit with separate supply voltage for memory that is different from logic circuit supply voltage 有权
公开(公告)号：US08848463B2
公开(公告)日：2014-09-30
申请号：US14095648
申请日：2013-12-03
申请人： Apple Inc.
发明人： Brian J. Campbell , Vincent R. von Kaenel , Daniel C. Murray , Gregory S. Scott , Sribalan Santhanam
IPC分类号： G11C7/00 , G11C11/417 , G11C11/419 , G11C8/08 , G11C7/12 , G11C5/14
CPC分类号： G11C11/419 , G11C5/143 , G11C7/00 , G11C7/12 , G11C8/08 , G11C11/417 , H03K3/35613 , H03K19/018528
摘要： In one embodiment, an integrated circuit includes at least one logic circuit supplied by a first supply voltage and at least one memory circuit coupled to the logic circuit and supplied by a second supply voltage. The memory circuit is configured to be read and written responsive to the logic circuit even if the first supply voltage is less than the second supply voltage during use. In another embodiment, a method includes a logic circuit reading a memory cell, the logic circuit supplied by a first supply voltage; and the memory cell responding to the read using signals that are referenced to the first supply voltage, wherein the memory cell is supplied with a second supply voltage that is greater than the first supply voltage during use.

7. 发明授权

US08625368B2 Integrated circuit with separate supply voltage for memory that is different from logic circuit supply voltage 有权
标题翻译：具有不同于逻辑电路电源电压的存储器的单独电源电压的集成电路
公开(公告)号：US08625368B2
公开(公告)日：2014-01-07
申请号：US13787894
申请日：2013-03-07
申请人： Apple Inc.
发明人： Brian J. Campbell , Vincent R. von Kaenel , Daniel C. Murray , Gregory S. Scott , Sribalan Santhanam
IPC分类号： G11C7/00
CPC分类号： G11C11/419 , G11C5/143 , G11C7/00 , G11C7/12 , G11C8/08 , G11C11/417 , H03K3/35613 , H03K19/018528
摘要： In one embodiment, an integrated circuit includes at least one logic circuit supplied by a first supply voltage and at least one memory circuit coupled to the logic circuit and supplied by a second supply voltage. The memory circuit is configured to be read and written responsive to the logic circuit even if the first supply voltage is less than the second supply voltage during use. In another embodiment, a method includes a logic circuit reading a memory cell, the logic circuit supplied by a first supply voltage; and the memory cell responding to the read using signals that are referenced to the first supply voltage, wherein the memory cell is supplied with a second supply voltage that is greater than the first supply voltage during use.
摘要翻译：在一个实施例中，集成电路包括由第一电源电压提供的至少一个逻辑电路和耦合到逻辑电路并由第二电源电压提供的至少一个存储器电路。即使在使用期间第一电源电压小于第二电源电压，存储器电路被配置为响应于逻辑电路被读取和写入。在另一个实施例中，一种方法包括：读取存储单元的逻辑电路，由第一电源电压提供的逻辑电路; 并且所述存储单元响应于所读取的使用参考于所述第一电源电压的信号，其中所述存储单元被提供在使用期间大于所述第一电源电压的第二电源电压。

8. 发明授权

US10482952B2 Integrated circuit with separate supply voltage for memory that is different from logic circuit supply voltage 有权
公开(公告)号：US10482952B2
公开(公告)日：2019-11-19
申请号：US15861308
申请日：2018-01-03
申请人： Apple Inc.
发明人： Brian J. Campbell , Vincent R. von Kaenel , Daniel C. Murray , Gregory S. Scott , Sribalan Santhanam
IPC分类号： G11C7/00 , G11C11/419 , G11C5/14 , H03K19/0185 , G11C8/08 , G11C11/417 , H03K3/356 , G11C7/12
摘要： In one embodiment, an integrated circuit includes at least one logic circuit supplied by a first supply voltage and at least one memory circuit coupled to the logic circuit and supplied by a second supply voltage. The memory circuit is configured to be read and written responsive to the logic circuit even if the first supply voltage is less than the second supply voltage during use. In another embodiment, a method includes a logic circuit reading a memory cell, the logic circuit supplied by a first supply voltage; and the memory cell responding to the read using signals that are referenced to the first supply voltage, wherein the memory cell is supplied with a second supply voltage that is greater than the first supply voltage during use.

9. 发明授权

US09672901B2 Integrated circuit with separate supply voltage for memory that is different from logic circuit supply voltage 有权
公开(公告)号：US09672901B2
公开(公告)日：2017-06-06
申请号：US15133400
申请日：2016-04-20
申请人： Apple Inc.
发明人： Brian J. Campbell , Vincent R. von Kaenel , Daniel C. Murray , Gregory S. Scott , Sribalan Santhanam
IPC分类号： G11C7/00 , G11C11/419 , G11C5/14 , G11C8/08 , G11C11/417 , G11C7/12 , H03K3/356 , H03K19/0185
CPC分类号： G11C11/419 , G11C5/143 , G11C7/00 , G11C7/12 , G11C8/08 , G11C11/417 , H03K3/35613 , H03K19/018528
摘要： In one embodiment, an integrated circuit includes at least one logic circuit supplied by a first supply voltage and at least one memory circuit coupled to the logic circuit and supplied by a second supply voltage. The memory circuit is configured to be read and written responsive to the logic circuit even if the first supply voltage is less than the second supply voltage during use. In another embodiment, a method includes a logic circuit reading a memory cell, the logic circuit supplied by a first supply voltage; and the memory cell responding to the read using signals that are referenced to the first supply voltage, wherein the memory cell is supplied with a second supply voltage that is greater than the first supply voltage during use.

10. 发明申请

US20130271179A1 Dynamic Voltage and Frequency Management 审中-公开
标题翻译：动态电压和频率管理
公开(公告)号：US20130271179A1
公开(公告)日：2013-10-17
申请号：US13915850
申请日：2013-06-12
申请人： Apple Inc.
发明人： Vincent R. von Kaenel
IPC分类号： G06F1/32
CPC分类号： H03K19/0008 , G06F1/3203 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： In one embodiment, an integrated circuit includes a self calibration unit configured to iterate a test on a logic circuit in the integrated circuit at respectively lower supply voltage magnitudes until the test fails. A lowest supply voltage magnitude at which the test passes is used to generate a requested supply voltage magnitude for the integrated circuit. In an embodiment, an integrated circuit includes a series connection of logic gates physically distributed over an area of the integrated circuit, and a measurement unit configured to launch a logical transition into the series and detect a corresponding transition at the output of the series. The amount of time between the launch and the detection is used to request a supply voltage magnitude for the integrated circuit.
摘要翻译：在一个实施例中，集成电路包括自校准单元，其被配置为在分别较低的电源电压幅度下对集成电路中的逻辑电路进行测试，直到测试失败为止。测试通过的最低电源电压幅度用于为集成电路产生所请求的电源电压幅度。在一个实施例中，集成电路包括物理分布在集成电路的区域上的逻辑门的串联连接，以及测量单元，被配置为将逻辑跃迁发射到该系列中，并且检测在该系列的输出处的对应转变。发射和检测之间的时间量用于请求集成电路的电源电压幅值。

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