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1. 发明申请

US20210143058A1 3D NAND GATE STACK REINFORCEMENT 有权
公开(公告)号：US20210143058A1
公开(公告)日：2021-05-13
申请号：US17089221
申请日：2020-11-04
申请人： Applied Materials, Inc.
发明人： Praket Prakash Jha , Shuchi Sunil Ojha , Jingmei Liang , Abhijit Basu Mallik , Shankar Venkataraman
IPC分类号： H01L21/768 , H01L21/02 , H01L21/3205 , H01L21/311 , H01L21/3213
摘要： Exemplary methods of forming a semiconductor structure may include forming a first silicon oxide layer overlying a semiconductor substrate. The methods may include forming a first silicon layer overlying the first silicon oxide layer. The methods may include forming a silicon nitride layer overlying the first silicon layer. The methods may include forming a second silicon layer overlying the silicon nitride layer. The methods may include forming a second silicon oxide layer overlying the second silicon layer. The methods may include removing the silicon nitride layer. The methods may include removing the first silicon layer and the second silicon layer. The methods may include forming a metal layer between and contacting each of the first silicon oxide layer and the second silicon oxide layer.

2. 发明申请

US20190385823A1 CHEMICAL CONTROL FEATURES IN WAFER PROCESS EQUIPMENT 审中-公开
公开(公告)号：US20190385823A1
公开(公告)日：2019-12-19
申请号：US16511990
申请日：2019-07-15
申请人： Applied Materials, Inc.
发明人： Qiwei Liang , Xinglong Chen , Kien Chuc , Dmitry Lubomirsky , Soonam Park , Jang-Gyoo Yang , Shankar Venkataraman , Toan Tran , Kimberly Hinckley , Saurabh Garg
IPC分类号： H01J37/32 , H01L21/67 , C23C16/50 , B05B1/18 , C23C16/455 , C23C16/452 , B05B1/00
摘要： Gas distribution assemblies are described including an annular body, an upper plate, and a lower plate. The upper plate may define a first plurality of apertures, and the lower plate may define a second and third plurality of apertures. The upper and lower plates may be coupled with one another and the annular body such that the first and second apertures produce channels through the gas distribution assemblies, and a volume is defined between the upper and lower plates.

3. 发明申请

US20190259580A1 OPTICAL EMISSION SPECTROSCOPY (OES) FOR REMOTE PLASMA MONITORING 审中-公开
公开(公告)号：US20190259580A1
公开(公告)日：2019-08-22
申请号：US16400615
申请日：2019-05-01
申请人： Applied Materials, Inc.
发明人： Tae Seung Cho , Soonam Park , Junghoon Kim , Dmitry Lubomirsky , Shankar Venkataraman
IPC分类号： H01J37/32 , H01L21/67 , H01L21/311 , G01J3/02 , G01N21/73 , G01J3/443
摘要： Methods and systems for etching substrates using a remote plasma are described. Remotely excited etchants are formed in a remote plasma and flowed through a showerhead into a substrate processing region to etch the substrate. Optical emission spectra are acquired from the substrate processing region just above the substrate. The optical emission spectra may be used to determine an endpoint of the etch, determine the etch rate or otherwise characterize the etch process. A weak plasma may be present in the substrate processing region. The weak plasma may have much lower intensity than the remote plasma. In cases where no bias plasma is used above the substrate in an etch process, a weak plasma may be ignited near a viewport disposed near the side of the substrate processing region to characterize the etchants.

4. 发明授权

US10256079B2 Semiconductor processing systems having multiple plasma configurations 有权
公开(公告)号：US10256079B2
公开(公告)日：2019-04-09
申请号：US13791074
申请日：2013-03-08
申请人： Applied Materials, Inc.
发明人： Dmitry Lubomirsky , Xinglong Chen , Shankar Venkataraman
IPC分类号： C23C16/00 , C23F1/00 , H01L21/306 , H01J37/32 , H01L21/3213 , C23C16/54 , C23C16/455 , C23C16/505 , H01L21/67
摘要： An exemplary system may include a chamber configured to contain a semiconductor substrate in a processing region of the chamber. The system may include a first remote plasma unit fluidly coupled with a first access of the chamber and configured to deliver a first precursor into the chamber through the first access. The system may still further include a second remote plasma unit fluidly coupled with a second access of the chamber and configured to deliver a second precursor into the chamber through the second access. The first and second access may be fluidly coupled with a mixing region of the chamber that is separate from and fluidly coupled with the processing region of the chamber. The mixing region may be configured to allow the first and second precursors to interact with each other externally from the processing region of the chamber.

5. 发明授权

US10032606B2 Semiconductor processing with DC assisted RF power for improved control 有权
公开(公告)号：US10032606B2
公开(公告)日：2018-07-24
申请号：US15187211
申请日：2016-06-20
申请人： Applied Materials, Inc.
发明人： Jang-Gyoo Yang , Xinglong Chen , Soonam Park , Jonghoon Baek , Saurabh Garg , Shankar Venkataraman
IPC分类号： C23C16/503 , H01J37/32 , H01L21/3065 , H01L21/67 , C23C16/50 , C23C16/505 , C23C16/509 , H01L21/3213 , H01L21/02 , H01L21/285 , H01L21/311
CPC分类号： H01J37/32091 , C23C16/50 , C23C16/503 , C23C16/505 , C23C16/509 , C23C16/5093 , H01J37/32146 , H01J37/32422 , H01J37/3244 , H01J37/32568 , H01J2237/332 , H01J2237/334 , H01L21/02274 , H01L21/0262 , H01L21/28556 , H01L21/3065 , H01L21/31116 , H01L21/31138 , H01L21/32136 , H01L21/67069 , H01L21/67075
摘要： Semiconductor processing systems are described including a process chamber. The process chamber may include a lid assembly, grid electrode, conductive insert, and ground electrode. Each component may be coupled with one or more power supplies operable to produce a plasma within the process chamber. Each component may be electrically isolated through the positioning of a plurality of insulation members. The one or more power supplies may be electrically coupled with the process chamber with the use of switching mechanisms. The switches may be switchable to electrically couple the one or more power supplies to the components of the process chamber.

6. 发明申请

US20170309509A1 HIGH TEMPERATURE CHUCK FOR PLASMA PROCESSING SYSTEMS 审中-公开
公开(公告)号：US20170309509A1
公开(公告)日：2017-10-26
申请号：US15642977
申请日：2017-07-06
申请人： Applied Materials, Inc.
发明人： Toan Q. Tran , Sultan Malik , Dmitry Lubomirsky , Shambhu N. Roy , Satoru Kobayashi , Tae Seung Cho , Soonam Park , Shankar Venkataraman
IPC分类号： H01L21/683 , H01L21/67 , H01L21/3065
CPC分类号： H01L21/6833 , H01L21/3065 , H01L21/67103
摘要： A wafer chuck assembly includes a puck, a shaft and a base. An insulating material defines a top surface of the puck, a heater element is embedded within the insulating material, and a conductive plate lies beneath the insulating material. The shaft includes a housing coupled with the plate, and electrical connectors for the heater elements and the electrodes. A conductive base housing couples with the shaft housing, and the connectors pass through a terminal block within the base housing. A method of plasma processing includes loading a workpiece onto a chuck having an insulating top surface, providing a DC voltage differential across two electrodes within the top surface, heating the chuck by passing current through heater elements, providing process gases in a chamber surrounding the chuck, and providing an RF voltage between a conductive plate beneath the chuck, and one or more walls of the chamber.

7. 发明申请

US20160300694A1 SEMICONDUCTOR PROCESSING WITH DC ASSISTED RF POWER FOR IMPROVED CONTROL 审中-公开
标题翻译：直流辅助RF功率的半导体处理改进控制
公开(公告)号：US20160300694A1
公开(公告)日：2016-10-13
申请号：US15187211
申请日：2016-06-20
申请人： Applied Materials, Inc.
发明人： Jang-Gyoo Yang , Xinglong Chen , Soonam Park , Jonghoon Baek , Saurabh Garg , Shankar Venkataraman
IPC分类号： H01J37/32 , C23C16/50 , C23C16/509 , H01L21/67
CPC分类号： H01J37/32091 , C23C16/50 , C23C16/503 , C23C16/505 , C23C16/509 , C23C16/5093 , H01J37/32146 , H01J37/32422 , H01J37/3244 , H01J37/32568 , H01J2237/332 , H01J2237/334 , H01L21/02274 , H01L21/0262 , H01L21/28556 , H01L21/3065 , H01L21/31116 , H01L21/31138 , H01L21/32136 , H01L21/67069 , H01L21/67075
摘要： Semiconductor processing systems are described including a process chamber. The process chamber may include a lid assembly, grid electrode, conductive insert, and ground electrode. Each component may be coupled with one or more power supplies operable to produce a plasma within the process chamber. Each component may be electrically isolated through the positioning of a plurality of insulation members. The one or more power supplies may be electrically coupled with the process chamber with the use of switching mechanisms. The switches may be switchable to electrically couple the one or more power supplies to the components of the process chamber.
摘要翻译：描述了包括处理室的半导体处理系统。处理室可以包括盖组件，栅格电极，导电插入件和接地电极。每个部件可以与可操作以在处理室内产生等离子体的一个或多个电源耦合。每个部件可以通过定位多个绝缘部件而被电隔离。一个或多个电源可以利用开关机构与处理室电耦合。开关可以切换以将一个或多个电源电耦合到处理室的组件。

8. 发明申请

US20160284556A1 ENHANCED ETCHING PROCESSES USING REMOTE PLASMA SOURCES 有权
标题翻译：使用远程等离子体源的增强蚀刻工艺
公开(公告)号：US20160284556A1
公开(公告)日：2016-09-29
申请号：US15173824
申请日：2016-06-06
申请人： Applied Materials, Inc.
发明人： Nitin K. Ingle , Dmitry Lubomirsky , Xinglong Chen , Shankar Venkataraman
IPC分类号： H01L21/3065 , H01J37/32
摘要： Methods of etching a patterned substrate may include flowing an oxygen-containing precursor into a first remote plasma region fluidly coupled with a substrate processing region. The oxygen-containing precursor may be flowed into the region while forming a plasma in the first remote plasma region to produce oxygen-containing plasma effluents. The methods may also include flowing a fluorine-containing precursor into a second remote plasma region fluidly coupled with the substrate processing region while forming a plasma in the second remote plasma region to produce fluorine-containing plasma effluents. The methods may include flowing the oxygen-containing plasma effluents and fluorine-containing plasma effluents into the processing region, and using the effluents to etch a patterned substrate housed in the substrate processing region.
摘要翻译：蚀刻图案化衬底的方法可以包括使含氧前体流入与衬底处理区流体耦合的第一远程等离子体区域。可以在第一远程等离子体区域中形成等离子体的同时将含氧前体流入该区域以产生含氧等离子体流出物。所述方法还可以包括使含氟前体流入与基板处理区流体耦合的第二远程等离子体区域，同时在第二远程等离子体区域中形成等离子体以产生含氟等离子体流出物。所述方法可以包括将含氧等离子体流出物和含氟等离子体流出物流入处理区域，并且使用流出物蚀刻容纳在基板处理区域中的图案化基板。

9. 发明授权

US09449850B2 Processing systems and methods for halide scavenging 有权
公开(公告)号：US09449850B2
公开(公告)日：2016-09-20
申请号：US14703299
申请日：2015-05-04
申请人： Applied Materials, Inc.
发明人： Anchuan Wang , Xinglong Chen , Zihui Li , Hiroshi Hamana , Zhijun Chen , Ching-Mei Hsu , Jiayin Huang , Nitin K. Ingle , Dmitry Lubomirsky , Shankar Venkataraman , Randhir Thakur
IPC分类号： H01L21/324 , H01L21/3065 , H01L21/306 , H01L21/311
CPC分类号： H01L21/324 , C23C16/4405 , H01J37/32357 , H01J37/32862 , H01L21/02041 , H01L21/02057 , H01L21/0206 , H01L21/263 , H01L21/2686 , H01L21/30604 , H01L21/3065 , H01L21/3105 , H01L21/31111 , H01L21/31116 , H01L21/31144 , H01L21/32136 , H01L21/32137 , H01L21/67069 , H01L21/67075 , H01L21/6708 , H01L21/67109 , H01L21/67115 , H01L21/67184 , H01L21/6719 , H01L21/67196 , H01L21/67201 , H01L21/67207 , H01L21/67248 , H01L21/67253 , H01L21/67288 , H01L21/67703 , H01L21/67739 , H01L21/67742 , H01L21/6831
摘要： Systems, chambers, and processes are provided for controlling process defects caused by moisture contamination. The systems may provide configurations for chambers to perform multiple operations in a vacuum or controlled environment. The chambers may include configurations to provide additional processing capabilities in combination chamber designs. The methods may provide for the limiting, prevention, and correction of aging defects that may be caused as a result of etching processes performed by system tools.

10. 发明申请

US20160035614A1 INTEGRATED BIT-LINE AIRGAP FORMATION AND GATE STACK POST CLEAN 有权
标题翻译：集成的位线空气格栅和门盖清洗
公开(公告)号：US20160035614A1
公开(公告)日：2016-02-04
申请号：US14448059
申请日：2014-07-31
申请人： Applied Materials, Inc.
发明人： Vinod R. Purayath , Randhir Thakur , Shankar Venkataraman , Nitin K. Ingle
IPC分类号： H01L21/764 , H01L29/06 , H01L21/311 , H01L29/49 , H01L21/02 , H01L27/115
CPC分类号： H01L21/764 , H01J37/32357 , H01L21/02071 , H01L21/28273 , H01L21/28282 , H01L21/31116 , H01L21/67069 , H01L21/67103 , H01L21/68764 , H01L27/11568 , H01L29/0649 , H01L29/0653 , H01L29/66833 , H01L29/7887
摘要： Methods of forming flash memory cells are described which incorporate air gaps for improved performance. The methods are useful for so-called “2-d flat cell” flash architectures. 2-d flat cell flash memory involves a reactive ion etch to dig trenches into multi-layers containing high work function and other metal layers. The methods described herein remove the metal oxide debris from the sidewalls of the multi-layer trench and then, without breaking vacuum, selectively remove shallow trench isolation (STI) oxidation which become the air gaps. Both the metal oxide removal and the STI oxidation removal are carried out in the same mainframe with highly selective etch processes using remotely excited fluorine plasma effluents.
摘要翻译：描述形成闪速存储器单元的方法，其包括用于改善性能的气隙。这些方法对于所谓的“2-d平坦单元”闪存架构是有用的。 2-d平板电池闪存包括反应离子蚀刻，以将沟槽挖掘成包含高功函数和其它金属层的多层。本文描述的方法从多层沟槽的侧壁去除金属氧化物碎屑，然后在不破坏真空的情况下选择性地去除成为气隙的浅沟槽隔离（STI）氧化。金属氧化物去除和STI氧化去除都是使用远程激发的氟等离子体流出物，在相同的主机中进行高选择性蚀刻工艺。

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