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1. 发明申请

US20180267257A1 CONTROL DEVICE AND METHOD FOR CONTROLLING BIASING OF MULTIPLE LIGHT SOURCES OF MULTIPLE CHANNELS OF A MULTI-CHANNEL OPTICAL COMMUNICATIONS MODULE 审中-公开
公开(公告)号：US20180267257A1
公开(公告)日：2018-09-20
申请号：US15638988
申请日：2017-06-30
申请人： Avago Technologies General IP (Singapore) Pte. Ltd
发明人： Samir Aboulhouda , Faouzi Chaahoub , Ahmed Rashid Syed , Kartikeya Gupta , Kazi Asaduzzaman
IPC分类号： G02B6/38 , G02B6/42 , H01S5/068 , H04B10/50 , H04B10/516
CPC分类号： G02B6/3885 , G02B6/421 , G02B6/4249 , G02B6/428 , H01S5/068 , H04B10/504 , H04B10/516
摘要： A control device that may be implemented in a single IC chip is provided that is capable of controlling EAM bias voltages and DFB bias currents and of monitoring the EAM photocurrents and received signal strength indicators (RSSIs) in a multi-channel optical transceiver module. The control device IC chip can be manufactured at relatively low cost with relatively high yield, and can be implemented in a relatively small area. To implement the control device in a single IC chip, multiple supply voltage domains are used in the IC chip, one of which is a negative supply voltage domain and one of which is a positive supply voltage domain. In order to provide these different supply voltage domains, a level shift circuit is employed in the IC chip that converts signals from the positive to the negative supply voltage domain, and vice versa, and changes the voltage levels, as needed.

2. 发明授权

US09571263B2 Integrated circuit incorporating a low power data retiming circuit 有权
标题翻译：集成电路结合了低功率数据重定时电路
公开(公告)号：US09571263B2
公开(公告)日：2017-02-14
申请号：US14728575
申请日：2015-06-02
申请人： Avago Technologies General IP (Singapore) Pte. Ltd.
发明人： Chakravartula Nallani , Samir Aboulhouda , Ramana Murty Malladi
IPC分类号： H04L7/00 , H04L7/033 , H03L7/08
CPC分类号： H04L7/0045 , H03L7/08 , H03L7/0802 , H04L7/0004 , H04L7/033 , H04L7/0332
摘要： A low power data retiming circuit incorporates CMOS components in certain sections that operate at a lower frequency in comparison to certain other sections that use components based on bipolar technology for operating at a relatively higher frequency. The data retiming circuit includes a clock recovery circuit wherein a voltage controlled oscillator provides a recovered clock to a clock generator circuit for generating a latched clock that is provided to a phase detector and a data serializer. The data serializer operates as a synchronous multiplexer for generating a retimed data output signal from a pair of latched data input signals. The phase detector and the data serializer operate in a half-rate mode wherein high and low voltage levels of the latched clock are used for clocking data. The half-rate mode of operation permits the use of a clock frequency that is half that of an input data rate.
摘要翻译：与使用基于双极技术的组件以相对较高频率工作的某些其他部分相比，低功率数据重定时电路在某些部分中集成了CMOS部件，其工作频率较低。数据重定时电路包括时钟恢复电路，其中压控振荡器将恢复的时钟提供给时钟发生器电路，用于产生提供给相位检测器和数据串行器的锁存时钟。数据串行器用作同步多路复用器，用于从一对锁存数据输入信号产生重定时数据输出信号。相位检测器和数据串行器以半速率模式工作，其中锁存时钟的高电平和低电压电平用于计时数据。半速率操作模式允许使用的时钟频率是输入数据速率的一半。

3. 发明申请

US20160359611A1 INTEGRATED CIRCUIT INCORPORATING A LOW POWER DATA RETIMING CIRCUIT 有权
标题翻译：并入一个低功率数据退化电路的集成电路
公开(公告)号：US20160359611A1
公开(公告)日：2016-12-08
申请号：US14728575
申请日：2015-06-02
申请人： Avago Technologies General IP (Singapore) Pte. Ltd
发明人： Chakravartula Nallani , Samir Aboulhouda , Ramana Murty Malladi
IPC分类号： H04L7/00 , H04L7/033
CPC分类号： H04L7/0045 , H03L7/08 , H03L7/0802 , H04L7/0004 , H04L7/033 , H04L7/0332
摘要： A low power data retiming circuit incorporates CMOS components in certain sections that operate at a lower frequency in comparison to certain other sections that use components based on bipolar technology for operating at a relatively higher frequency. The data retiming circuit includes a clock recovery circuit wherein a voltage controlled oscillator provides a recovered clock to a clock generator circuit for generating a latched clock that is provided to a phase detector and a data serializer. The data serializer operates as a synchronous multiplexer for generating a retimed data output signal from a pair of latched data input signals. The phase detector and the data serializer operate in a half-rate mode wherein high and low voltage levels of the latched clock are used for clocking data. The half-rate mode of operation permits the use of a clock frequency that is half that of an input data rate.
摘要翻译：与使用基于双极技术的组件以相对较高频率工作的某些其他部分相比，低功率数据重定时电路在某些部分中集成了CMOS部件，其工作频率较低。数据重定时电路包括时钟恢复电路，其中压控振荡器将恢复的时钟提供给时钟发生器电路，用于产生提供给相位检测器和数据串行器的锁存时钟。数据串行器用作同步多路复用器，用于从一对锁存数据输入信号产生重定时数据输出信号。相位检测器和数据串行器以半速率模式工作，其中锁存时钟的高电平和低电压电平用于计时数据。半速率操作模式允许使用的时钟频率是输入数据速率的一半。

4. 发明授权

US09065696B2 Adaptive equalizer 有权
标题翻译：自适应均衡器
公开(公告)号：US09065696B2
公开(公告)日：2015-06-23
申请号：US13969534
申请日：2013-08-17
申请人： Avago Technologies General IP (Singapore) Pte. Ltd.
发明人： Georgios Asmanis , Faouzi Chaahoub , Samir Aboulhouda , Sriramkumar Sundararaman , Ajay Kumar Yadav
IPC分类号： H03H7/30 , H03H7/40 , H03K5/159 , H04L25/03
CPC分类号： H04L25/03006 , H04L25/03019 , H04L2025/03707
摘要： An equalizer that includes equalizer circuitry, a mean squared error (MSE) system, and adaptive control logic includes features that inhibit undesirable convergence to local minima.
摘要翻译：包括均衡器电路，均方误差（MSE）系统和自适应控制逻辑的均衡器包括抑制不希望的收敛到局部最小值的特征。

5. 发明申请

US20150117510A1 RATE-ADAPTIVE EQUALIZER THAT AUTOMATICALLY INITIALIZES ITSELF BASED ON DETECTED CHANNEL CONDITIONS, AND A METHOD 有权
标题翻译：根据检测到的通道条件自动初始化ITSELF的自适应均衡器和方法
公开(公告)号：US20150117510A1
公开(公告)日：2015-04-30
申请号：US14069338
申请日：2013-10-31
申请人： Avago Technologies General IP (Singapore) Pte. Ltd.
发明人： Faouzi Chaahoub , Georgios Asmanis , Sriramkumar Sundararaman , Samir Aboulhouda
IPC分类号： H04L25/03
CPC分类号： H04L25/03885 , H04L25/03012 , H04L2025/03668
摘要： A rate-adaptive equalizer automatically initializes its tap coefficients to values. During an initialization process, a linear search algorithm is performed that sweeps the tap coefficients through different combinations of tap coefficients while assessing information about an eye associated with an input signal received over a communications channel. When the eye information indicates that the eye is open, the current tap coefficients are selected as the initial tap coefficients to be used at the beginning of the main adaptation algorithm.
摘要翻译：速率自适应均衡器自动将其抽头系数初始化为值。在初始化过程中，执行线性搜索算法，其通过抽头系数的不同组合扫描抽头系数，同时评估与通过通信信道接收的输入信号相关联的眼睛的信息。当眼睛信息表示眼睛打开时，选择当前抽头系数作为要在主适应算法开始时使用的初始抽头系数。

6. 发明授权

US09020024B1 Rate-adaptive equalizer that automatically initializes itself based on detected channel conditions, and a method 有权
标题翻译：基于检测到的信道条件自动初始化自身的速率自适应均衡器，以及一种方法
公开(公告)号：US09020024B1
公开(公告)日：2015-04-28
申请号：US14069338
申请日：2013-10-31
申请人： Avago Technologies General IP (Singapore) Pte. Ltd.
发明人： Faouzi Chaahoub , Georgios Asmanis , Sriramkumar Sundararaman , Samir Aboulhouda
IPC分类号： H03H7/30 , H04L25/03
CPC分类号： H04L25/03885 , H04L25/03012 , H04L2025/03668
摘要： A rate-adaptive equalizer automatically initializes its tap coefficients to values. During an initialization process, a linear search algorithm is performed that sweeps the tap coefficients through different combinations of tap coefficients while assessing information about an eye associated with an input signal received over a communications channel. When the eye information indicates that the eye is open, the current tap coefficients are selected as the initial tap coefficients to be used at the beginning of the main adaptation algorithm.
摘要翻译：速率自适应均衡器自动将其抽头系数初始化为值。在初始化过程中，执行线性搜索算法，其通过抽头系数的不同组合扫描抽头系数，同时评估与通过通信信道接收的输入信号相关联的眼睛的信息。当眼睛信息表示眼睛打开时，选择当前抽头系数作为要在主适应算法开始时使用的初始抽头系数。

7. 发明申请

US20150049797A1 ADAPTIVE EQUALIZER 有权
标题翻译：自适应均衡器
公开(公告)号：US20150049797A1
公开(公告)日：2015-02-19
申请号：US13969534
申请日：2013-08-17
申请人： Avago Technologies General IP (Singapore) Pte. Ltd
发明人： Georgios Asmanis , Faouzi Chaahoub , Samir Aboulhouda , Sriramkumar Sundararaman , Ajay Kumar Yadav
IPC分类号： H04L25/03
CPC分类号： H04L25/03006 , H04L25/03019 , H04L2025/03707
摘要： An equalizer that includes equalizer circuitry, a mean squared error (MSE) system, and adaptive control logic includes features that inhibit undesirable convergence to local minima.
摘要翻译：包括均衡器电路，均方误差（MSE）系统和自适应控制逻辑的均衡器包括抑制不希望的收敛到局部最小值的特征。

8. 发明申请

US20180006799A1 CLOCK-AND-DATA RECOVERY (CDR) CIRCUITRY FOR PERFORMING AUTOMATIC RATE NEGOTIATION 审中-公开
公开(公告)号：US20180006799A1
公开(公告)日：2018-01-04
申请号：US15199721
申请日：2016-06-30
申请人： Avago Technologies General IP (Singapore) Pte. Ltd.
发明人： Ajay Yadav , Samir Aboulhouda , Faouzi Chaahoub
IPC分类号： H04L7/00 , H04B10/61 , H04L7/033 , H04L29/08
CPC分类号： H04B10/616 , H03L7/0807 , H04B10/69 , H04L7/0004 , H04L7/033
摘要： A CDR circuit for use in an optical receiver is provided that performs automatic rate negotiation. The CDR circuit is configured to determine whether the incoming data signal has a first, second or third data rate. If the CDR circuit determines that the incoming data signal has the first data rate, the CDR circuit places itself in a bypass mode of operations so that CDR is not performed. If the CDR circuit determines that the incoming data signal has the second or third data rates, the CDR circuit places itself in a CDR mode of operations and performs CDR on the incoming data signal.

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