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1. 发明授权

US08462033B2 Reconfigurable delta-sigma modulator ADC using noise coupling 有权
标题翻译：可重构的Δ-Σ调制器ADC使用噪声耦合
公开(公告)号：US08462033B2
公开(公告)日：2013-06-11
申请号：US13188470
申请日：2011-07-22
申请人： Ayman Shabra , Halil Kiper
发明人： Ayman Shabra , Halil Kiper
IPC分类号： H03M3/00
CPC分类号： H03M3/326 , H03M3/39 , H03M3/396
摘要： A reconfigurable analog-to-digital (ADC) modulator structure that includes a plurality of ADC structures being coupled to each other through their respective noise quantization transfer functions. Each ADC structure receives as input an analog signal and each ADC structure outputting a plurality of first output signals. An adder module receives the first output signals and performs addition on the first output signals and generates a second output signal. A division module receives the second output signal and performs division on the second output signal by a predetermined factor.
摘要翻译：一种可重新配置的模数（ADC）调制器结构，其包括通过它们各自的噪声量化传递函数彼此耦合的多个ADC结构。每个ADC结构接收模拟信号作为输入，并且每个ADC结构输出多个第一输出信号。加法器模块接收第一输出信号并对第一输出信号执行加法并产生第二输出信号。分割模块接收第二输出信号，并以预定的因子对第二输出信号进行分频。

2. 发明申请

US20130021180A1 RECONFIGURABLE DELTA-SIGMA MODULATOR ADC USING NOISE COUPLING 有权
标题翻译：使用噪声耦合的可重构三角形调制器ADC
公开(公告)号：US20130021180A1
公开(公告)日：2013-01-24
申请号：US13188470
申请日：2011-07-22
申请人： Ayman Shabra , Halil Kiper
发明人： Ayman Shabra , Halil Kiper
IPC分类号： H03M1/12 , H03M3/02
CPC分类号： H03M3/326 , H03M3/39 , H03M3/396
摘要： A reconfigurable analog-to-digital (ADC) modulator structure that includes a plurality of ADC structures being coupled to each other through their respective noise quantization transfer functions. Each ADC structure receives as input an analog signal and each ADC structure outputting a plurality of first output signals. An adder module receives the first output signals and performs addition on the first output signals and generates a second output signal. A division module receives the second output signal and performs division on the second output signal by a predetermined factor.
摘要翻译：一种可重新配置的模数（ADC）调制器结构，其包括通过它们各自的噪声量化传递函数彼此耦合的多个ADC结构。每个ADC结构接收模拟信号作为输入，并且每个ADC结构输出多个第一输出信号。加法器模块接收第一输出信号并对第一输出信号执行加法并产生第二输出信号。分割模块接收第二输出信号，并以预定的因子对第二输出信号进行分频。

3. 发明授权

US08417750B2 Filters for communication systems 有权
标题翻译：通讯系统过滤器
公开(公告)号：US08417750B2
公开(公告)日：2013-04-09
申请号：US11249930
申请日：2005-10-13
申请人： Aiguo Yan , Ayman Shabra
发明人： Aiguo Yan , Ayman Shabra
IPC分类号： G06F17/17
CPC分类号： H03H17/0657 , H03H17/0664 , H04L25/03834
摘要： The invention relates to a cascaded scheme in which an RRC filter, a modified RRC filter or other digital filter is implemented at a relatively low data rate, such as twice the symbol or chip rate, or 2×. Interpolation filters are used to increase the data rate to a higher data rate, such as 8×. Decimation filters are used to reduce the data rate from a higher rate, such as 8×, to a lower rate, such as 2×. The coefficients of the digital filter may be adjusted to compensate for characteristics of other components across the entire filter chain. Most of the implementation complexity of the filter chain is consolidated into the relatively low rate (such as 2×) digital filter while interpolation or decimation filters can be implemented at very low cost. The compensation capability provided by the digital filter makes design of simple decimation or interpolation filters much easier. The compensation capability provided by the digital filter, along with the relatively high over-sampling rate for the output of the interpolation filter (or the input of the decimation filter), also makes the design of the preceding (or following) analog filters much easier.
摘要翻译：本发明涉及一种级联方案，其中以相对较低的数据速率（例如符号或码片速率的两倍）或2×来实现RRC滤波器，修改的RRC滤波器或其他数字滤波器。内插滤波器用于将数据速率提高到更高的数据速率，如8×。抽取滤波器用于将数据速率从较高速率（例如8×）降低到较低的速率，例如2×。可以调整数字滤波器的系数以补偿整个滤波器链上的其它部件的特性。滤波器链的大部分实现复杂度被整合为相对较低的速率（例如2×）数字滤波器，而插值或抽取滤波器可以以非常低的成本实现。由数字滤波器提供的补偿功能使得简单抽取或插值滤波器的设计更容易。数字滤波器提供的补偿能力以及内插滤波器（或抽取滤波器的输入）的相对较高的过采样率也使得前一个（或之后）模拟滤波器的设计变得更加容易。

4. 发明申请

US20120056661A1 HIGH VOLTAGE MULTIPLEXER ELEMENT AND MULTIPLEXER SYSTEM USING SAME 审中-公开
标题翻译：高电压多用户元件和多用户系统
公开(公告)号：US20120056661A1
公开(公告)日：2012-03-08
申请号：US12877111
申请日：2010-09-08
申请人： Ayman Shabra
发明人： Ayman Shabra
IPC分类号： H03K17/687
CPC分类号： H03K17/693 , H03K17/6871 , H03K2217/0054 , H03M3/474 , H03M3/494
摘要： This invention features a high voltage multiplexer element including a voltage to current converting input resistance connected to the input of the element, first and second MOSFET switches connected in series between the input resistance and the output of the multiplexer element, and a third MOS switch connected between the junction of the first and second MOSFET switches and a voltage equal to or less than the supply; the first MOSFET switch being drain engineered and having drain-source breakdown voltage higher than the supply.
摘要翻译：本发明的特征在于一种高电压多路复用器元件，包括电压到电流转换连接到元件的输入端的输入电阻，第一和第二MOSFET开关串联连接在输入电阻和多路复用器元件的输出之间，第三MOS开关连接在第一和第二MOSFET开关的接合点和等于或小于电源的电压之间; 第一个MOSFET开关被漏极设计，并具有高于电源的漏极 - 源极击穿电压。

5. 发明申请

US20060083297A1 Filters for communication systems 有权
标题翻译：通讯系统过滤器
公开(公告)号：US20060083297A1
公开(公告)日：2006-04-20
申请号：US11249930
申请日：2005-10-13
申请人： Aiguo Yan , Ayman Shabra
发明人： Aiguo Yan , Ayman Shabra
IPC分类号： H03K5/159
CPC分类号： H03H17/0657 , H03H17/0664 , H04L25/03834
摘要： The invention relates to a cascaded scheme in which an RRC filter, a modified RRC filter or other digital filter is implemented at a relatively low data rate, such as twice the symbol or chip rate, or 2×. Interpolation filters are used to increase the data rate to a higher data rate, such as 8×. Decimation filters are used to reduce the data rate from a higher rate, such as 8×, to a lower rate, such as 2×. The coefficients of the digital filter may be adjusted to compensate for characteristics of other components across the entire filter chain. Most of the implementation complexity of the filter chain is consolidated into the relatively low rate (such as 2×) digital filter while interpolation or decimation filters can be implemented at very low cost. The compensation capability provided by the digital filter makes design of simple decimation or interpolation filters much easier. The compensation capability provided by the digital filter, along with the relatively high over-sampling rate for the output of the interpolation filter (or the input of the decimation filter), also makes the design of the preceding (or following) analog filters much easier.
摘要翻译：本发明涉及一种级联方案，其中在相对低的数据速率（例如符号或码片速率的两倍）或2x上实现RRC滤波器，修改的RRC滤波器或其他数字滤波器。内插滤波器用于将数据速率提高到更高的数据速率，例如8x。抽取滤波器用于将数据速率从较高速率（例如8x）降低到较低的速率，例如2x。可以调整数字滤波器的系数以补偿整个滤波器链上的其它部件的特性。滤波器链的大部分实现复杂度被整合为相对较低的速率（例如2x）数字滤波器，而插值或抽取滤波器可以以非常低的成本实现。由数字滤波器提供的补偿功能使得简单抽取或插值滤波器的设计更容易。数字滤波器提供的补偿能力以及内插滤波器（或抽取滤波器的输入）的相对较高的过采样率也使得前一个（或之后）模拟滤波器的设计变得更加容易。

6. 发明申请

US20130015987A1 MIMO DELTA-SIGMA DELTA ANALOG-TO-DIGITAL CONVERTER USING NOISE CANCELING 有权
标题翻译：使用噪声消除的MIMO DELTA-SIGMA DELTA模拟到数字转换器
公开(公告)号：US20130015987A1
公开(公告)日：2013-01-17
申请号：US13183438
申请日：2011-07-15
申请人： Ayman Shabra
发明人： Ayman Shabra
IPC分类号： H03M1/12 , H03M1/00 , H05K13/00 , H03M3/02
CPC分类号： H03M3/326 , H03M3/39 , H04B7/0413 , Y10T29/49002
摘要： A multi-input-multi-output-system (MIMO) is provided that includes a first input signal and a second input signal. A plurality of analog-to-digital converter (ADC) cell structures receive as input a combination of the first input signal and the second input signal as well as a combination of quantization noise signals from the respective other ADC cell structures of the plurality of ADC cell structures. The ADC cell structures generate a plurality of first output signals and the noise quantization signals. A plurality of adder modules receive the first output signals and performing either addition or subtraction on a selected combination of the first output signals, the adder modules generate a plurality of second output signals. A plurality of division modules receive the second output signals and perform a division operation on the second output signals by a predetermined factor. The division modules generate a plurality of final output signals of the MIMO.
摘要翻译：提供了一种包括第一输入信号和第二输入信号的多输入多输出系统（MIMO）。多个模数转换器（ADC）单元结构作为输入接收第一输入信号和第二输入信号的组合，以及来自多个ADC的各个其它ADC单元结构的量化噪声信号的组合细胞结构。 ADC单元结构产生多个第一输出信号和噪声量化信号。多个加法器模块接收第一输出信号并对所选择的第一输出信号的组合执行加法或减法，加法器模块产生多个第二输出信号。多个分割模块接收第二输出信号，并以预定的因素对第二输出信号执行除法运算。分割模块产生MIMO的多个最终输出信号。

7. 发明授权

US07936298B2 Integrated circuit and electronic device comprising threshold generation circuitry and method therefor 有权
标题翻译：集成电路和电子设备，包括阈值生成电路及其方法
公开(公告)号：US07936298B2
公开(公告)日：2011-05-03
申请号：US12562144
申请日：2009-09-18
申请人： Ayman Shabra
发明人： Ayman Shabra
IPC分类号： H03M1/12
CPC分类号： H03M1/0604 , H03M1/0682 , H03M1/365
摘要： An integrated circuit comprises a threshold generation circuitry for generating at least one differential voltage signal. The threshold generation circuitry comprises at least one common mode current generation circuit arranged to generate at least one common mode current signal, whereby said at least one common mode current signal is combined with at least one input current signal to produce a combined current signal comprising a combined signal common mode component. Conversion circuitry is arranged to receive the combined current signal and convert the combined current signal into the at least one differential voltage signal for use within the comparator circuit. The threshold generation circuitry further comprises feedback circuitry arranged to receive an indication of the combined signal common mode component, compare the received indication to a reference value, and regulate the at least one common mode current signal based at least partly on the comparison results.
摘要翻译：集成电路包括用于产生至少一个差分电压信号的阈值产生电路。阈值产生电路包括至少一个共模电流产生电路，其被布置成产生至少一个共模电流信号，由此所述至少一个共模电流信号与至少一个输入电流信号组合以产生组合电流信号，该组合电流信号包括组合信号共模分量。转换电路被布置成接收组合的电流信号并将组合的电流信号转换成用于比较器电路内的至少一个差分电压信号。阈值产生电路还包括反馈电路，其被布置为接收组合信号共模分量的指示，将接收到的指示与参考值进行比较，并且至少部分地基于比较结果来调节至少一个共模电流信号。

8. 发明授权

US07693923B2 Digital filter system whose stopband roots lie on unit circle of complex plane and associated method 有权
标题翻译：数字滤波系统，其阻带根位于复平面的单位圆和相关方法上
公开(公告)号：US07693923B2
公开(公告)日：2010-04-06
申请号：US11260443
申请日：2005-10-27
申请人： Ayman Shabra , Aiguo Yan
发明人： Ayman Shabra , Aiguo Yan
IPC分类号： G06F17/10
CPC分类号： H03H17/0219
摘要： A method is disclosed for providing a digital filter system for providing a low pass filter function to a digital input. The method includes the steps of determining a finite impulse response of the input, determining a transfer function of the finite impulse response and providing a polynomial, identifying a plurality of stopband roots of the polymonial that lie in a complex plane, identifying real and complex conjugate pairs for the plurality of stopband roots, and providing coefficients for a complex polynomial that realizes the real and complex conjugate pairs such that a plurality of adjusted stopband roots lie on a unit circle of said complex plane.
摘要翻译：公开了一种用于提供用于向数字输入提供低通滤波器功能的数字滤波器系统的方法。该方法包括以下步骤：确定输入的有限脉冲响应，确定有限脉冲响应的传递函数并提供多项式，识别位于复平面中的多音节的多个阻带根，识别实数和复共轭并且提供用于实现真实和复共轭对的复数多项式的系数，使得多个调整的阻带根位于所述复平面的单位圆上。

9. 发明申请

US20110068846A1 INTEGRATED CIRCUIT AND ELECTRONIC DEVICE COMPRISING THRESHOLD GENERATION CIRCUITRY AND METHOD THEREFOR 有权
标题翻译：集成电路和包含阈值生成电路的电子设备及其方法
公开(公告)号：US20110068846A1
公开(公告)日：2011-03-24
申请号：US12562144
申请日：2009-09-18
申请人： Ayman Shabra
发明人： Ayman Shabra
IPC分类号： H03L5/00
CPC分类号： H03M1/0604 , H03M1/0682 , H03M1/365
摘要： An integrated circuit comprises a threshold generation circuitry for generating at least one differential voltage signal. The threshold generation circuitry comprises at least one common mode current generation circuit arranged to generate at least one common mode current signal, whereby said at least one common mode current signal is combined with at least one input current signal to produce a combined current signal comprising a combined signal common mode component. Conversion circuitry is arranged to receive the combined current signal and convert the combined current signal into the at least one differential voltage signal for use within the comparator circuit. The threshold generation circuitry further comprises feedback circuitry arranged to receive an indication of the combined signal common mode component, compare the received indication to a reference value, and regulate the at least one common mode current signal based at least partly on the comparison results.
摘要翻译：集成电路包括用于产生至少一个差分电压信号的阈值产生电路。阈值产生电路包括至少一个共模电流产生电路，其被布置成产生至少一个共模电流信号，由此所述至少一个共模电流信号与至少一个输入电流信号组合以产生组合电流信号，该组合电流信号包括组合信号共模分量。转换电路被布置成接收组合的电流信号并将组合的电流信号转换成用于比较器电路内的至少一个差分电压信号。阈值产生电路还包括反馈电路，其被布置为接收组合信号共模分量的指示，将接收到的指示与参考值进行比较，并且至少部分地基于比较结果来调节至少一个共模电流信号。

10. 发明申请

US20060106906A1 Digital filter system and method 有权
标题翻译：数字滤波系统及方法
公开(公告)号：US20060106906A1
公开(公告)日：2006-05-18
申请号：US11260443
申请日：2005-10-27
申请人： Ayman Shabra , Aiguo Yan
发明人： Ayman Shabra , Aiguo Yan
IPC分类号： G06F17/10
CPC分类号： H03H17/0219
摘要： A method is disclosed for providing a digital filter system for providing a low pass filter function to a digital input. The method includes the steps of determining a finite impulse response of the input, determining a transfer function of the finite impulse response and providing a polynomial, identifying a plurality of stopband roots of the polymonial that lie in a complex plane, identifying real and complex conjugate pairs for the plurality of stopband roots, and providing coefficients for a complex polynomial that realizes the real and complex conjugate pairs such that a plurality of adjusted stopband roots lie on a unit circle of said complex plane.
摘要翻译：公开了一种用于提供用于向数字输入提供低通滤波器功能的数字滤波器系统的方法。该方法包括以下步骤：确定输入的有限脉冲响应，确定有限脉冲响应的传递函数并提供多项式，识别位于复平面中的多音节的多个阻带根，识别实数和复共轭并且提供用于实现真实和复共轭对的复数多项式的系数，使得多个调整的阻带根位于所述复平面的单位圆上。

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