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1. 发明授权

US08462033B2 Reconfigurable delta-sigma modulator ADC using noise coupling 有权
标题翻译：可重构的Δ-Σ调制器ADC使用噪声耦合
公开(公告)号：US08462033B2
公开(公告)日：2013-06-11
申请号：US13188470
申请日：2011-07-22
申请人： Ayman Shabra , Halil Kiper
发明人： Ayman Shabra , Halil Kiper
IPC分类号： H03M3/00
CPC分类号： H03M3/326 , H03M3/39 , H03M3/396
摘要： A reconfigurable analog-to-digital (ADC) modulator structure that includes a plurality of ADC structures being coupled to each other through their respective noise quantization transfer functions. Each ADC structure receives as input an analog signal and each ADC structure outputting a plurality of first output signals. An adder module receives the first output signals and performs addition on the first output signals and generates a second output signal. A division module receives the second output signal and performs division on the second output signal by a predetermined factor.
摘要翻译：一种可重新配置的模数（ADC）调制器结构，其包括通过它们各自的噪声量化传递函数彼此耦合的多个ADC结构。每个ADC结构接收模拟信号作为输入，并且每个ADC结构输出多个第一输出信号。加法器模块接收第一输出信号并对第一输出信号执行加法并产生第二输出信号。分割模块接收第二输出信号，并以预定的因子对第二输出信号进行分频。

2. 发明申请

US20130021180A1 RECONFIGURABLE DELTA-SIGMA MODULATOR ADC USING NOISE COUPLING 有权
标题翻译：使用噪声耦合的可重构三角形调制器ADC
公开(公告)号：US20130021180A1
公开(公告)日：2013-01-24
申请号：US13188470
申请日：2011-07-22
申请人： Ayman Shabra , Halil Kiper
发明人： Ayman Shabra , Halil Kiper
IPC分类号： H03M1/12 , H03M3/02
CPC分类号： H03M3/326 , H03M3/39 , H03M3/396
摘要： A reconfigurable analog-to-digital (ADC) modulator structure that includes a plurality of ADC structures being coupled to each other through their respective noise quantization transfer functions. Each ADC structure receives as input an analog signal and each ADC structure outputting a plurality of first output signals. An adder module receives the first output signals and performs addition on the first output signals and generates a second output signal. A division module receives the second output signal and performs division on the second output signal by a predetermined factor.
摘要翻译：一种可重新配置的模数（ADC）调制器结构，其包括通过它们各自的噪声量化传递函数彼此耦合的多个ADC结构。每个ADC结构接收模拟信号作为输入，并且每个ADC结构输出多个第一输出信号。加法器模块接收第一输出信号并对第一输出信号执行加法并产生第二输出信号。分割模块接收第二输出信号，并以预定的因子对第二输出信号进行分频。

3. 发明申请

US20100144304A1 Reciever dynamically switching to pseudo differential mode for SOC spur reduction 有权
标题翻译：接收器动态切换到伪差分模式，以减少SOC刺激
公开(公告)号：US20100144304A1
公开(公告)日：2010-06-10
申请号：US12315926
申请日：2008-12-08
申请人： Charles G. Lin , Burak Kelleci , Halil Kiper , Yuanying Deng
发明人： Charles G. Lin , Burak Kelleci , Halil Kiper , Yuanying Deng
IPC分类号： H04B1/16
CPC分类号： H04B15/06
摘要： A low noise amplifier in an integrated circuit, the circuit having a digital portion and an analog portion on a common substrate, the digital portion having at least one clocking frequency, includes an input configured to receive a signal at a tuned frequency and an output circuit. The output circuit is configurable to operate in either a single-ended mode or a pseudo differential-ended mode, wherein the output circuit is configured in the pseudo differential-ended mode when the tuned frequency is substantially similar to the at least one clocking frequency or one of its harmonics and otherwise configured in the single-ended mode.
摘要翻译：一种集成电路中的低噪声放大器，该电路在公共基板上具有数字部分和模拟部分，数字部分具有至少一个时钟频率，包括被配置为接收调谐频率的信号的输入端和输出电路。输出电路可配置为以单端模式或伪差分端模式工作，其中当调谐频率基本上类似于至少一个时钟频率时，输出电路被配置为伪差分端模式，或者其中一个谐波，否则以单端模式配置。

4. 发明授权

US08023919B2 Receiver dynamically switching to pseudo differential mode for SOC spur reduction 有权
标题翻译：接收机动态地切换到伪差分模式，以减少SOC刺激
公开(公告)号：US08023919B2
公开(公告)日：2011-09-20
申请号：US12315926
申请日：2008-12-08
申请人： Charles G. Lin , Burak Kelleci , Halil Kiper , Yuanying Deng
发明人： Charles G. Lin , Burak Kelleci , Halil Kiper , Yuanying Deng
IPC分类号： H04B1/10
CPC分类号： H04B15/06
摘要： A low noise amplifier in an integrated circuit, the circuit having a digital portion and an analog portion on a common substrate, the digital portion having at least one clocking frequency, includes an input configured to receive a signal at a tuned frequency and an output circuit. The output circuit is configurable to operate in either a single-ended mode or a pseudo differential-ended mode, wherein the output circuit is configured in the pseudo differential-ended mode when the tuned frequency is substantially similar to the at least one clocking frequency or one of its harmonics and otherwise configured in the single-ended mode.
摘要翻译：一种集成电路中的低噪声放大器，该电路在公共基板上具有数字部分和模拟部分，数字部分具有至少一个时钟频率，包括被配置为接收调谐频率的信号的输入端和输出电路。输出电路可配置为以单端模式或伪差分端模式工作，其中当调谐频率基本上类似于至少一个时钟频率时，输出电路被配置为伪差分端模式，或者其中一个谐波，否则以单端模式配置。

5. 发明申请

US20100238059A1 ADAPTIVE DIGITAL AUDIO PRE-DISTORTION IN AN AUDIO DIGITAL TO ANALOG CONVERTER 有权
标题翻译：音频数字到模拟转换器的自适应数字音频预失真
公开(公告)号：US20100238059A1
公开(公告)日：2010-09-23
申请号：US12383351
申请日：2009-03-23
申请人： Halil Kiper , Srinath Mathur Ramaswamy , Gangadhar Burra
发明人： Halil Kiper , Srinath Mathur Ramaswamy , Gangadhar Burra
IPC分类号： H03M1/66 , G06F17/00
CPC分类号： H03M3/388 , H03M3/50
摘要： An adaptive digital pre-distortion block is used to cancel device nonlinearities to improve the overall linearity of a Delta-Sigma DAC system. In particular, the pre-distortion block may be implemented all in digital components and utilize programmable registers that change the pre-distortion transfer function either statically or dynamically, or both. Static changes can be for variation in process corners during production, whereas, dynamic changes can be used to correct nonlinear changes that can occur from environmental reasons such as voltage, temperature, aging and device stress.
摘要翻译：使用自适应数字预失真块来消除器件非线性以提高Delta-Sigma DAC系统的整体线性度。特别地，预失真块可以全部以数字组件实现，并且利用可以静态地或动态地改变预失真传递函数的可编程寄存器，或者两者。静态变化可以用于生产中过程拐角的变化，而动态变化可用于校正可能由环境原因（如电压，温度，老化和器件应力）引起的非线性变化。

6. 发明授权

US07786915B1 Adaptive digital audio pre-distortion in an audio digital to analog converter 有权
标题翻译：音频数模转换器中的自适应数字音频预失真
公开(公告)号：US07786915B1
公开(公告)日：2010-08-31
申请号：US12383351
申请日：2009-03-23
申请人： Halil Kiper , Srinath Mathur Ramaswamy , Gangadhar Burra
发明人： Halil Kiper , Srinath Mathur Ramaswamy , Gangadhar Burra
IPC分类号： H03M1/66
CPC分类号： H03M3/388 , H03M3/50
摘要： An adaptive digital pre-distortion block is used to cancel device nonlinearities to improve the overall linearity of a Delta-Sigma DAC system. In particular, the pre-distortion block may be implemented all in digital components and utilize programmable registers that change the pre-distortion transfer function either statically or dynamically, or both. Static changes can be for variation in process corners during production, whereas, dynamic changes can be used to correct nonlinear changes that can occur from environmental reasons such as voltage, temperature, aging and device stress.
摘要翻译：使用自适应数字预失真块来消除器件非线性以提高Delta-Sigma DAC系统的整体线性度。特别地，预失真块可以全部以数字组件实现，并且利用可以静态地或动态地改变预失真传递函数的可编程寄存器，或者两者。静态变化可以用于生产中过程拐角的变化，而动态变化可用于校正可能由环境原因（如电压，温度，老化和器件应力）引起的非线性变化。

7. 发明授权

US08456341B2 Three-level digital-to-analog converter 有权
标题翻译：三电平数模转换器
公开(公告)号：US08456341B2
公开(公告)日：2013-06-04
申请号：US13134301
申请日：2011-06-03
申请人： Rahmi Hezar , Baher Haroun , Halil Kiper , Mounir Fares , Ajay Kumar
发明人： Rahmi Hezar , Baher Haroun , Halil Kiper , Mounir Fares , Ajay Kumar
IPC分类号： H03M1/66
CPC分类号： H03M1/66 , H03M1/747 , H03M3/464
摘要： A system for processing a signal includes a detector configured to detect a two-level stream of bits; a converter configured to generate a three-level control signal based on two adjacent values within the two-level stream of bits; and a switch configured to determine which of three different paths to couple a current source to based on a value of the three-level control signal. Thus, based on adjacent values of the output stream a three-level control signal is generated which controls coupling of the current source to one of three different paths. This type of three-level digital-to-analog converter can be, for example, part of the feedback loop of an analog-to-digital converter. Similar techniques can also be utilized in a multi-segment digital-to-analog converter in which each segment of the DAC is controlled by a 3-level control signal and the DAC is implement using PMOS devices. The current source for each DAC segment is diverted to ground, the M-node, or the P-node depending on the value of the 3-level control signal.
摘要翻译：一种用于处理信号的系统包括：检测器，被配置为检测两级比特流; 转换器，被配置为基于所述两级比特流内的两个相邻值生成三电平控制信号; 以及开关，被配置为基于三电平控制信号的值来确定三个不同路径中的哪一个耦合电流源。因此，基于输出流的相邻值，生成三电平控制信号，其控制电流源与三个不同路径之一的耦合。这种类型的三电平数模转换器可以是例如模数转换器的反馈回路的一部分。类似技术也可以用在多段数模转换器中，其中DAC的每个段由3电平控制信号控制，并且使用PMOS器件来实现DAC。每个DAC段的电流源根据3电平控制信号的值转移到地，M节点或P节点。

8. 发明申请

US20120306678A1 Three-level digital-to-analog converter 有权
标题翻译：三电平数模转换器
公开(公告)号：US20120306678A1
公开(公告)日：2012-12-06
申请号：US13134301
申请日：2011-06-03
申请人： Rahmi Hezar , Baher Haroun , Halil Kiper , Mounir Fares , Ajay Kumar
发明人： Rahmi Hezar , Baher Haroun , Halil Kiper , Mounir Fares , Ajay Kumar
IPC分类号： H03M1/72
CPC分类号： H03M1/66 , H03M1/747 , H03M3/464
摘要： A system for processing a signal includes a detector configured to detect a two-level stream of bits; a converter configured to generate a three-level control signal based on two adjacent values within the two-level stream of bits; and a switch configured to determine which of three different paths to couple a current source to based on a value of the three-level control signal. Thus, based on adjacent values of the output stream a three-level control signal is generated which controls coupling of the current source to one of three different paths. This type of three-level digital-to-analog converter can be, for example, part of the feedback loop of an analog-to-digital converter. Similar techniques can also be utilized in a multi-segment digital-to-analog converter in which each segment of the DAC is controlled by a 3-level control signal and the DAC is implement using PMOS devices. The current source for each DAC segment is diverted to ground, the M-node, or the P-node depending on the value of the 3-level control signal.
摘要翻译：一种用于处理信号的系统包括：检测器，被配置为检测两级比特流; 转换器，被配置为基于所述两级比特流内的两个相邻值生成三电平控制信号; 以及开关，被配置为基于三电平控制信号的值来确定三个不同路径中的哪一个耦合电流源。因此，基于输出流的相邻值，生成三电平控制信号，其控制电流源与三个不同路径之一的耦合。这种类型的三电平数模转换器可以是例如模数转换器的反馈回路的一部分。类似的技术也可以用在多段数模转换器中，其中DAC的每个段由3电平控制信号控制，并且使用PMOS器件实现DAC。每个DAC段的电流源根据3电平控制信号的值转移到地，M节点或P节点。

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